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85xx: Fix memory test range on MPC8536DS
[people/ms/u-boot.git] / include / asm-ppc / immap_85xx.h
CommitLineData
42d1f039
WD		 1/*
2 * MPC85xx Internal Memory Map
3 *
a07bf180 4 * Copyright 2007-2009 Freescale Semiconductor, Inc.
837f1ba0 5 *
42d1f039
WD		 6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com)
8 *
9 */
10
11#ifndef __IMMAP_85xx__
12#define __IMMAP_85xx__
13
3dfa9cfd 14#include <asm/types.h>
b1f12650 15#include <asm/fsl_dma.h>
3dfa9cfd 16#include <asm/fsl_i2c.h>
4e190b03 17#include <asm/fsl_lbc.h>
3dfa9cfd 18
de1d0a69
JL		 19/*
20 * Local-Access Registers and ECM Registers(0x0000-0x2000)
21 */
42d1f039
WD		 22typedef struct ccsr_local_ecm {
23 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
24 char res1[4];
25 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
26 char res2[4];
27 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
28 char res3[12];
29 uint bptr; /* 0x20 - Boot Page Translation Register */
30 char res4[3044];
31 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
32 char res5[4];
33 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
34 char res6[20];
35 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
36 char res7[4];
37 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
38 char res8[20];
39 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
40 char res9[4];
41 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
42 char res10[20];
43 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
44 char res11[4];
45 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
46 char res12[20];
47 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
48 char res13[4];
49 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
50 char res14[20];
51 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
52 char res15[4];
53 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
54 char res16[20];
55 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
56 char res17[4];
57 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
58 char res18[20];
59 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
60 char res19[4];
61 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
8d949aff
SS		 62 char res19_8a[20];
63 uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */
64 char res19_8b[4];
65 uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */
66 char res19_9a[20];
67 uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */
68 char res19_9b[4];
69 uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */
70 char res19_10a[20];
71 uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */
72 char res19_10b[4];
73 uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */
74 char res19_11a[20];
75 uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */
76 char res19_11b[4];
77 uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */
78 char res20[652];
42d1f039
WD		 79 uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
80 char res21[12];
81 uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
82 char res22[3564];
83 uint eedr; /* 0x1e00 - ECM Error Detect Register */
84 char res23[4];
85 uint eeer; /* 0x1e08 - ECM Error Enable Register */
86 uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */
87 uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */
88 char res24[492];
89} ccsr_local_ecm_t;
90
de1d0a69
JL		 91/*
92 * DDR memory controller registers(0x2000-0x3000)
93 */
42d1f039
WD		 94typedef struct ccsr_ddr {
95 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
96 char res1[4];
97 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
98 char res2[4];
99 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
100 char res3[4];
101 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
102 char res4[100];
103 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
104 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
105 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
106 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
5893b3d0
JY		 107 char res4a[48];
108 uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */
109 uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */
110 uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */
111 uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */
112 char res5[48];
45239cf4 113 uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */
d9b94f28 114 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
42d1f039
WD		 115 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
116 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
117 uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
d9b94f28 118 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */
42d1f039 119 uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
d9b94f28
JL		 120 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/
121 uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */
42d1f039 122 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
d9b94f28
JL		 123 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */
124 char res6[4];
547b4cb2 125 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
d9b94f28 126 char res7[20];
ef7d30b1
KG		 127 uint init_addr; /* 0x2148 - DDR training initialization address */
128 uint init_ext_addr; /* 0x214C - DDR training initialization extended address */
5893b3d0
JY		 129 char res8_1[16];
130 uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */
131 uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */
132 char reg8_1a[8];
133 uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/
134 uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/
135 uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/
136 uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
137 uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
138 uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
8d949aff
SS		 139 char res8_1b[2456];
140 uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */
141 uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */
142 uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */
143 uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */
144 char res8_1c[200];
d9b94f28
JL		 145 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */
146 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */
147 char res8_2[512];
42d1f039
WD		 148 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
149 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
150 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
151 char res9[20];
152 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
153 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
154 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
155 char res10[20];
156 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
157 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
158 uint err_int_en; /* 0x2e48 - DDR */
159 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
160 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
161 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
162 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
163 char res11[164];
164 uint debug_1; /* 0x2f00 */
165 uint debug_2;
166 uint debug_3;
167 uint debug_4;
168 char res12[240];
169} ccsr_ddr_t;
170
de1d0a69
JL		 171/*
172 * I2C Registers(0x3000-0x4000)
173 */
42d1f039 174typedef struct ccsr_i2c {
3dfa9cfd
JL		 175 struct fsl_i2c i2c[1];
176 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
42d1f039
WD		 177} ccsr_i2c_t;
178
03f5c550
WD		 179#if defined(CONFIG_MPC8540) \
180 || defined(CONFIG_MPC8541) \
d9b94f28 181 || defined(CONFIG_MPC8548) \
03f5c550 182 || defined(CONFIG_MPC8555)
42d1f039
WD		 183/* DUART Registers(0x4000-0x5000) */
184typedef struct ccsr_duart {
185 char res1[1280];
186 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
187 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
188 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
189 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
190 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
191 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
192 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
193 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
194 char res2[8];
195 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
196 char res3[239];
197 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
198 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
199 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
200 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
201 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
202 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
203 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
204 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
205 char res4[8];
206 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
207 char res5[2543];
208} ccsr_duart_t;
209#else /* MPC8560 uses UART on its CPM */
210typedef struct ccsr_duart {
211 char res[4096];
212} ccsr_duart_t;
213#endif
214
215/* Local Bus Controller Registers(0x5000-0x6000) */
216/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
217
218typedef struct ccsr_lbc {
219 uint br0; /* 0x5000 - LBC Base Register 0 */
220 uint or0; /* 0x5004 - LBC Options Register 0 */
221 uint br1; /* 0x5008 - LBC Base Register 1 */
222 uint or1; /* 0x500c - LBC Options Register 1 */
223 uint br2; /* 0x5010 - LBC Base Register 2 */
224 uint or2; /* 0x5014 - LBC Options Register 2 */
225 uint br3; /* 0x5018 - LBC Base Register 3 */
226 uint or3; /* 0x501c - LBC Options Register 3 */
227 uint br4; /* 0x5020 - LBC Base Register 4 */
228 uint or4; /* 0x5024 - LBC Options Register 4 */
229 uint br5; /* 0x5028 - LBC Base Register 5 */
230 uint or5; /* 0x502c - LBC Options Register 5 */
231 uint br6; /* 0x5030 - LBC Base Register 6 */
232 uint or6; /* 0x5034 - LBC Options Register 6 */
233 uint br7; /* 0x5038 - LBC Base Register 7 */
234 uint or7; /* 0x503c - LBC Options Register 7 */
235 char res1[40];
236 uint mar; /* 0x5068 - LBC UPM Address Register */
237 char res2[4];
238 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
239 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
240 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
241 char res3[8];
242 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
243 uint mdr; /* 0x5088 - LBC UPM Data Register */
244 char res4[8];
245 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
246 char res5[8];
247 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
248 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
249 char res6[8];
250 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
251 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
252 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
253 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
254 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
255 char res7[12];
256 uint lbcr; /* 0x50d0 - LBC Configuration Register */
257 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
5893b3d0 258 char res8[3880];
42d1f039
WD		 259} ccsr_lbc_t;
260
7fa96a9a
MH		 261/*
262 * eSPI Registers(0x7000-0x8000)
263 */
264typedef struct ccsr_espi {
265 uint mode; /* 0x00 - eSPI mode register */
266 uint event; /* 0x04 - eSPI event register */
267 uint mask; /* 0x08 - eSPI mask register */
268 uint com; /* 0x0c - eSPI command register */
269 uint tx; /* 0x10 - eSPI transmit FIFO access register */
270 uint rx; /* 0x14 - eSPI receive FIFO access register */
271 char res1[8]; /* reserved */
272 uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */
273 char res2[4048]; /* fill up to 0x1000 */
274} ccsr_espi_t;
275
de1d0a69
JL		 276/*
277 * PCI Registers(0x8000-0x9000)
de1d0a69 278 */
42d1f039
WD		 279typedef struct ccsr_pcix {
280 uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
281 uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
282 uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */
283 char res1[3060];
284 uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
285 uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
286 uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
287 uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
288 uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
289 char res2[12];
290 uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
291 uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
292 uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
293 uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
294 uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
295 char res3[12];
296 uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
297 uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
298 uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
299 uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
300 uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
301 char res4[12];
302 uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
303 uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
304 uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
305 uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
306 uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
307 char res5[12];
308 uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
309 uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
310 uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
311 uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
312 uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
313 char res6[268];
314 uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */
315 uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
316 uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
317 uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
318 uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
319 char res7[12];
320 uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */
321 uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
322 uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
323 uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
324 uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
325 char res8[12];
326 uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */
327 uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
328 uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
329 char res9[4];
330 uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
331 char res10[12];
332 uint pedr; /* 0x8e00 - PCIX Error Detect Register */
333 uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */
334 uint peer; /* 0x8e08 - PCIX Error Enable Register */
335 uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */
336 uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */
337 uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
338 uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
339 uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
97074ed9
MM		 340 uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */
341 char res11[476];
42d1f039
WD		 342} ccsr_pcix_t;
343
546b1032
PA		 344typedef struct ccsr_gpio {
345 uint gpdir;
346 uint gpodr;
347 uint gpdat;
348 uint gpier;
349 uint gpimr;
350 uint gpicr;
351} ccsr_gpio_t;
352
97074ed9
MM		 353#define PCIX_COMMAND 0x62
354#define POWAR_EN 0x80000000
355#define POWAR_IO_READ 0x00080000
356#define POWAR_MEM_READ 0x00040000
357#define POWAR_IO_WRITE 0x00008000
358#define POWAR_MEM_WRITE 0x00004000
359#define POWAR_MEM_512M 0x0000001c
360#define POWAR_IO_1M 0x00000013
361
362#define PIWAR_EN 0x80000000
363#define PIWAR_PF 0x20000000
364#define PIWAR_LOCAL 0x00f00000
365#define PIWAR_READ_SNOOP 0x00050000
366#define PIWAR_WRITE_SNOOP 0x00005000
367#define PIWAR_MEM_2G 0x0000001e
368
369
de1d0a69
JL		 370/*
371 * L2 Cache Registers(0x2_0000-0x2_1000)
372 */
42d1f039
WD		 373typedef struct ccsr_l2cache {
374 uint l2ctl; /* 0x20000 - L2 configuration register 0 */
375 char res1[12];
376 uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */
377 char res2[4];
378 uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */
379 char res3[4];
380 uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */
381 char res4[4];
382 uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */
383 char res5[4];
384 uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */
385 char res6[4];
386 uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */
387 char res7[4];
388 uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */
389 char res8[4];
390 uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */
391 char res9[180];
392 uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */
393 char res10[4];
394 uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */
395 char res11[3316];
396 uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */
397 uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */
398 uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */
399 char res12[20];
400 uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */
401 uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */
402 uint l2captecc; /* 0x20e28 - L2 error ECC capture register */
403 char res13[20];
404 uint l2errdet; /* 0x20e40 - L2 error detect register */
405 uint l2errdis; /* 0x20e44 - L2 error disable register */
406 uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */
407 uint l2errattr; /* 0x20e4c - L2 error attributes capture register */
408 uint l2erraddr; /* 0x20e50 - L2 error address capture register */
409 char res14[4];
410 uint l2errctl; /* 0x20e58 - L2 error control register */
411 char res15[420];
412} ccsr_l2cache_t;
413
de1d0a69
JL		 414/*
415 * DMA Registers(0x2_1000-0x2_2000)
416 */
42d1f039
WD		 417typedef struct ccsr_dma {
418 char res1[256];
b1f12650 419 struct fsl_dma dma[4];
42d1f039 420 uint dgsr; /* 0x21300 - DMA General Status Register */
b1f12650 421 char res2[11516];
42d1f039
WD		 422} ccsr_dma_t;
423
de1d0a69
JL		 424/*
425 * tsec1 tsec2: 24000-26000
426 */
42d1f039
WD		 427typedef struct ccsr_tsec {
428 char res1[16];
429 uint ievent; /* 0x24010 - Interrupt Event Register */
430 uint imask; /* 0x24014 - Interrupt Mask Register */
431 uint edis; /* 0x24018 - Error Disabled Register */
432 char res2[4];
433 uint ecntrl; /* 0x24020 - Ethernet Control Register */
434 uint minflr; /* 0x24024 - Minimum Frame Length Register */
435 uint ptv; /* 0x24028 - Pause Time Value Register */
436 uint dmactrl; /* 0x2402c - DMA Control Register */
437 uint tbipa; /* 0x24030 - TBI PHY Address Register */
438 char res3[88];
439 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
440 char res4[8];
441 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
442 uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
443 char res5[96];
444 uint tctrl; /* 0x24100 - Transmit Control Register */
445 uint tstat; /* 0x24104 - Transmit Status Register */
446 char res6[4];
447 uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
448 char res7[16];
449 uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
450 uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
451 char res8[88];
452 uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
453 uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
454 char res9[120];
455 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
456 uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
457 char res10[168];
458 uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
459 uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
460 uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
461 uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
462 uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
463 uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
464 uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
465 char res11[52];
466 uint rctrl; /* 0x24300 - Receive Control Register */
467 uint rstat; /* 0x24304 - Receive Status Register */
468 char res12[4];
469 uint rbdlen; /* 0x2430c - RxBD Data Length Register */
470 char res13[16];
471 uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
472 uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
473 char res14[24];
474 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
475 uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
476 char res15[56];
477 uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
478 uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
479 uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
480 uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
481 uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
482 uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
483 uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
484 uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
485 char res16[96];
486 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
487 uint rbase; /* 0x24404 - Receive Descriptor Base Address */
488 uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
489 uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
490 uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
491 uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
492 uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
493 uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
494 char res17[224];
495 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
496 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
497 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
498 uint hafdup; /* 0x2450c - Half Duplex Register */
499 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
500 char res18[12];
501 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
502 uint miimcom; /* 0x24524 - MII Management Command Register */
503 uint miimadd; /* 0x24528 - MII Management Address Register */
504 uint miimcon; /* 0x2452c - MII Management Control Register */
505 uint miimstat; /* 0x24530 - MII Management Status Register */
506 uint miimind; /* 0x24534 - MII Management Indicator Register */
507 char res19[4];
508 uint ifstat; /* 0x2453c - Interface Status Register */
509 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
510 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
511 char res20[312];
512 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
513 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
514 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
515 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
516 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
517 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
518 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
519 uint rbyt; /* 0x2469c - Receive Byte Counter */
520 uint rpkt; /* 0x246a0 - Receive Packet Counter */
521 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
522 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
523 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
524 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
525 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
526 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
527 uint raln; /* 0x246bc - Receive Alignment Error Counter */
528 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
529 uint rcde; /* 0x246c4 - Receive Code Error Counter */
530 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
531 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
532 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
533 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
534 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
535 uint rdrp; /* 0x246dc - Receive Drop Counter */
536 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
537 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
538 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
539 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
540 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
541 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
542 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
543 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
544 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
545 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
546 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
547 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
548 char res21[4];
549 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
550 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
551 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
552 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
553 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
554 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
555 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
556 uint car1; /* 0x24730 - Carry Register One */
557 uint car2; /* 0x24734 - Carry Register Two */
558 uint cam1; /* 0x24738 - Carry Mask Register One */
559 uint cam2; /* 0x2473c - Carry Mask Register Two */
560 char res22[192];
561 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
562 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
563 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
564 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
565 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
566 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
567 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
568 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
569 char res23[96];
570 uint gaddr0; /* 0x24880 - Global address register 0 */
571 uint gaddr1; /* 0x24884 - Global address register 1 */
572 uint gaddr2; /* 0x24888 - Global address register 2 */
573 uint gaddr3; /* 0x2488c - Global address register 3 */
574 uint gaddr4; /* 0x24890 - Global address register 4 */
575 uint gaddr5; /* 0x24894 - Global address register 5 */
576 uint gaddr6; /* 0x24898 - Global address register 6 */
577 uint gaddr7; /* 0x2489c - Global address register 7 */
578 char res24[96];
579 uint pmd0; /* 0x24900 - Pattern Match Data Register */
580 char res25[4];
581 uint pmask0; /* 0x24908 - Pattern Mask Register */
582 char res26[4];
583 uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
584 char res27[4];
585 uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
586 uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
587 uint pmd1; /* 0x24920 - Pattern Match Data Register */
588 char res28[4];
589 uint pmask1; /* 0x24928 - Pattern Mask Register */
590 char res29[4];
591 uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
592 char res30[4];
593 uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
594 uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
595 uint pmd2; /* 0x24940 - Pattern Match Data Register */
596 char res31[4];
597 uint pmask2; /* 0x24948 - Pattern Mask Register */
598 char res32[4];
599 uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
600 char res33[4];
601 uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
602 uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
603 uint pmd3; /* 0x24960 - Pattern Match Data Register */
604 char res34[4];
605 uint pmask3; /* 0x24968 - Pattern Mask Register */
606 char res35[4];
607 uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
608 char res36[4];
609 uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
610 uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
611 uint pmd4; /* 0x24980 - Pattern Match Data Register */
612 char res37[4];
613 uint pmask4; /* 0x24988 - Pattern Mask Register */
614 char res38[4];
615 uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
616 char res39[4];
617 uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
618 uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
619 uint pmd5; /* 0x249a0 - Pattern Match Data Register */
620 char res40[4];
621 uint pmask5; /* 0x249a8 - Pattern Mask Register */
622 char res41[4];
623 uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
624 char res42[4];
625 uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
626 uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
627 uint pmd6; /* 0x249c0 - Pattern Match Data Register */
628 char res43[4];
629 uint pmask6; /* 0x249c8 - Pattern Mask Register */
630 char res44[4];
631 uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
632 char res45[4];
633 uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
634 uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
635 uint pmd7; /* 0x249e0 - Pattern Match Data Register */
636 char res46[4];
637 uint pmask7; /* 0x249e8 - Pattern Mask Register */
638 char res47[4];
639 uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
640 char res48[4];
641 uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
642 uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
643 uint pmd8; /* 0x24a00 - Pattern Match Data Register */
644 char res49[4];
645 uint pmask8; /* 0x24a08 - Pattern Mask Register */
646 char res50[4];
647 uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
648 char res51[4];
649 uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
650 uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
651 uint pmd9; /* 0x24a20 - Pattern Match Data Register */
652 char res52[4];
653 uint pmask9; /* 0x24a28 - Pattern Mask Register */
654 char res53[4];
655 uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
656 char res54[4];
657 uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
658 uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
659 uint pmd10; /* 0x24a40 - Pattern Match Data Register */
660 char res55[4];
661 uint pmask10; /* 0x24a48 - Pattern Mask Register */
662 char res56[4];
663 uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
664 char res57[4];
665 uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
666 uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
667 uint pmd11; /* 0x24a60 - Pattern Match Data Register */
668 char res58[4];
669 uint pmask11; /* 0x24a68 - Pattern Mask Register */
670 char res59[4];
671 uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
672 char res60[4];
673 uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
674 uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
675 uint pmd12; /* 0x24a80 - Pattern Match Data Register */
676 char res61[4];
677 uint pmask12; /* 0x24a88 - Pattern Mask Register */
678 char res62[4];
679 uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
680 char res63[4];
681 uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
682 uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
683 uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
684 char res64[4];
685 uint pmask13; /* 0x24aa8 - Pattern Mask Register */
686 char res65[4];
687 uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
688 char res66[4];
689 uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
690 uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
691 uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
692 char res67[4];
693 uint pmask14; /* 0x24ac8 - Pattern Mask Register */
694 char res68[4];
695 uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
696 char res69[4];
697 uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
698 uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
699 uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
700 char res70[4];
701 uint pmask15; /* 0x24ae8 - Pattern Mask Register */
702 char res71[4];
703 uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
704 char res72[4];
705 uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
706 uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
707 char res73[248];
708 uint attr; /* 0x24bf8 - Attributes Register */
709 uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
710 char res74[1024];
711} ccsr_tsec_t;
712
de1d0a69 713/*
04db4008 714 * PIC Registers(0x4_0000-0x8_0000)
de1d0a69 715 */
42d1f039 716typedef struct ccsr_pic {
04db4008 717 char res1[64]; /* 0x40000 */
42d1f039
WD		 718 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
719 char res2[12];
720 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
721 char res3[12];
722 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
723 char res4[12];
724 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
725 char res5[12];
726 uint ctpr; /* 0x40080 - Current Task Priority Register */
727 char res6[12];
728 uint whoami; /* 0x40090 - Who Am I Register */
729 char res7[12];
730 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
731 char res8[12];
732 uint eoi; /* 0x400b0 - End Of Interrupt Register */
733 char res9[3916];
734 uint frr; /* 0x41000 - Feature Reporting Register */
735 char res10[28];
736 uint gcr; /* 0x41020 - Global Configuration Register */
343117bf
WD		 737#define MPC85xx_PICGCR_RST 0x80000000
738#define MPC85xx_PICGCR_M 0x20000000
42d1f039
WD		 739 char res11[92];
740 uint vir; /* 0x41080 - Vendor Identification Register */
741 char res12[12];
742 uint pir; /* 0x41090 - Processor Initialization Register */
743 char res13[12];
744 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
745 char res14[12];
746 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
747 char res15[12];
748 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
749 char res16[12];
750 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
751 char res17[12];
752 uint svr; /* 0x410e0 - Spurious Vector Register */
753 char res18[12];
754 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
755 char res19[12];
756 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
757 char res20[12];
758 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
759 char res21[12];
760 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
761 char res22[12];
762 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
763 char res23[12];
764 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
765 char res24[12];
766 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
767 char res25[12];
768 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
769 char res26[12];
770 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
771 char res27[12];
772 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
773 char res28[12];
774 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
775 char res29[12];
776 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
777 char res30[12];
778 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
779 char res31[12];
780 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
781 char res32[12];
782 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
783 char res33[12];
784 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
785 char res34[12];
786 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
787 char res35[268];
788 uint tcr; /* 0x41300 - Timer Control Register */
789 char res36[12];
790 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
791 char res37[12];
792 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
793 char res38[12];
794 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
795 char res39[12];
796 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
797 char res40[188];
798 uint msgr0; /* 0x41400 - Message Register 0 */
799 char res41[12];
800 uint msgr1; /* 0x41410 - Message Register 1 */
801 char res42[12];
802 uint msgr2; /* 0x41420 - Message Register 2 */
803 char res43[12];
804 uint msgr3; /* 0x41430 - Message Register 3 */
805 char res44[204];
806 uint mer; /* 0x41500 - Message Enable Register */
807 char res45[12];
808 uint msr; /* 0x41510 - Message Status Register */
809 char res46[60140];
810 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
811 char res47[12];
812 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
813 char res48[12];
814 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
815 char res49[12];
816 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
817 char res50[12];
818 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
819 char res51[12];
820 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
821 char res52[12];
822 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
823 char res53[12];
824 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
825 char res54[12];
826 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
827 char res55[12];
828 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
829 char res56[12];
830 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
831 char res57[12];
832 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
833 char res58[12];
834 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
835 char res59[12];
836 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
837 char res60[12];
838 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
839 char res61[12];
840 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
841 char res62[12];
842 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
843 char res63[12];
844 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
845 char res64[12];
846 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
847 char res65[12];
848 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
849 char res66[12];
850 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
851 char res67[12];
852 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
853 char res68[12];
854 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
855 char res69[12];
856 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
857 char res70[140];
858 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
859 char res71[12];
860 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
861 char res72[12];
862 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
863 char res73[12];
864 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
865 char res74[12];
866 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
867 char res75[12];
868 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
869 char res76[12];
870 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
871 char res77[12];
872 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
873 char res78[12];
874 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
875 char res79[12];
876 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
877 char res80[12];
878 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
879 char res81[12];
880 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
881 char res82[12];
882 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
883 char res83[12];
884 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
885 char res84[12];
886 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
887 char res85[12];
888 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
889 char res86[12];
890 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
891 char res87[12];
892 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
893 char res88[12];
894 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
895 char res89[12];
896 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
897 char res90[12];
898 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
899 char res91[12];
900 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
901 char res92[12];
902 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
903 char res93[12];
904 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
905 char res94[12];
906 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
907 char res95[12];
908 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
909 char res96[12];
910 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
911 char res97[12];
912 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
913 char res98[12];
914 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
915 char res99[12];
916 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
917 char res100[12];
918 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
919 char res101[12];
920 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
921 char res102[12];
922 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
923 char res103[12];
924 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
925 char res104[12];
926 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
927 char res105[12];
928 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
929 char res106[12];
930 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
931 char res107[12];
932 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
933 char res108[12];
934 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
935 char res109[12];
936 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
937 char res110[12];
938 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
939 char res111[12];
940 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
941 char res112[12];
942 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
943 char res113[12];
944 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
945 char res114[12];
946 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
947 char res115[12];
948 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
949 char res116[12];
950 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
951 char res117[12];
952 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
953 char res118[12];
954 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
955 char res119[12];
956 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
957 char res120[12];
958 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
959 char res121[12];
960 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
961 char res122[12];
962 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
963 char res123[12];
964 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
965 char res124[12];
966 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
967 char res125[12];
968 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
969 char res126[12];
970 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
971 char res127[12];
972 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
973 char res128[12];
974 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
975 char res129[12];
976 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
977 char res130[12];
978 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
979 char res131[12];
980 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
981 char res132[12];
982 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
983 char res133[12];
984 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
985 char res134[4108];
986 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
987 char res135[12];
988 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
989 char res136[12];
990 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
991 char res137[12];
992 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
993 char res138[12];
994 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
995 char res139[12];
996 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
997 char res140[12];
998 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
999 char res141[12];
1000 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
1001 char res142[59852];
1002 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
1003 char res143[12];
1004 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
1005 char res144[12];
1006 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
1007 char res145[12];
1008 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
1009 char res146[12];
1010 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
1011 char res147[12];
1012 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
1013 char res148[12];
1014 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
1015 char res149[12];
1016 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
1017 char res150[130892];
1018} ccsr_pic_t;
1019
de1d0a69
JL		 1020/*
1021 * CPM Block(0x8_0000-0xc_0000)
1022 */
9c4c5ae3 1023#ifndef CONFIG_CPM2
42d1f039
WD		 1024typedef struct ccsr_cpm {
1025 char res[262144];
1026} ccsr_cpm_t;
1027#else
de1d0a69
JL		 1028/*
1029 * 0x8000-0x8ffff:DPARM
1030 * 0x9000-0x90bff: General SIU
1031 */
42d1f039 1032typedef struct ccsr_cpm_siu {
53677ef1 1033 char res1[80];
42d1f039
WD		 1034 uint smaer;
1035 uint smser;
1036 uint smevr;
1037 char res2[4];
1038 uint lmaer;
1039 uint lmser;
1040 uint lmevr;
1041 char res3[2964];
1042} ccsr_cpm_siu_t;
1043
1044/* 0x90c00-0x90cff: Interrupt Controller */
1045typedef struct ccsr_cpm_intctl {
1046 ushort sicr;
1047 char res1[2];
1048 uint sivec;
1049 uint sipnrh;
1050 uint sipnrl;
1051 uint siprr;
1052 uint scprrh;
1053 uint scprrl;
1054 uint simrh;
1055 uint simrl;
1056 uint siexr;
1057 char res2[88];
1058 uint sccr;
1059 char res3[124];
1060} ccsr_cpm_intctl_t;
1061
1062/* 0x90d00-0x90d7f: input/output port */
1063typedef struct ccsr_cpm_iop {
1064 uint pdira;
1065 uint ppara;
1066 uint psora;
1067 uint podra;
1068 uint pdata;
1069 char res1[12];
1070 uint pdirb;
1071 uint pparb;
1072 uint psorb;
1073 uint podrb;
1074 uint pdatb;
1075 char res2[12];
1076 uint pdirc;
1077 uint pparc;
1078 uint psorc;
1079 uint podrc;
1080 uint pdatc;
1081 char res3[12];
1082 uint pdird;
1083 uint ppard;
1084 uint psord;
1085 uint podrd;
1086 uint pdatd;
1087 char res4[12];
1088} ccsr_cpm_iop_t;
1089
1090/* 0x90d80-0x91017: CPM timers */
1091typedef struct ccsr_cpm_timer {
1092 u_char tgcr1;
1093 char res1[3];
1094 u_char tgcr2;
1095 char res2[11];
1096 ushort tmr1;
1097 ushort tmr2;
1098 ushort trr1;
1099 ushort trr2;
1100 ushort tcr1;
1101 ushort tcr2;
1102 ushort tcn1;
1103 ushort tcn2;
1104 ushort tmr3;
1105 ushort tmr4;
1106 ushort trr3;
1107 ushort trr4;
1108 ushort tcr3;
1109 ushort tcr4;
1110 ushort tcn3;
1111 ushort tcn4;
1112 ushort ter1;
1113 ushort ter2;
1114 ushort ter3;
1115 ushort ter4;
1116 char res3[608];
1117} ccsr_cpm_timer_t;
1118
1119/* 0x91018-0x912ff: SDMA */
1120typedef struct ccsr_cpm_sdma {
1121 uchar sdsr;
53677ef1
WD		 1122 char res1[3];
1123 uchar sdmr;
1124 char res2[739];
42d1f039
WD		 1125} ccsr_cpm_sdma_t;
1126
1127/* 0x91300-0x9131f: FCC1 */
1128typedef struct ccsr_cpm_fcc1 {
1129 uint gfmr;
1130 uint fpsmr;
1131 ushort ftodr;
1132 char res1[2];
1133 ushort fdsr;
1134 char res2[2];
1135 ushort fcce;
1136 char res3[2];
1137 ushort fccm;
1138 char res4[2];
1139 u_char fccs;
1140 char res5[3];
1141 u_char ftirr_phy[4];
1142} ccsr_cpm_fcc1_t;
1143
1144/* 0x91320-0x9133f: FCC2 */
1145typedef struct ccsr_cpm_fcc2 {
1146 uint gfmr;
1147 uint fpsmr;
1148 ushort ftodr;
1149 char res1[2];
1150 ushort fdsr;
1151 char res2[2];
1152 ushort fcce;
1153 char res3[2];
1154 ushort fccm;
1155 char res4[2];
1156 u_char fccs;
1157 char res5[3];
1158 u_char ftirr_phy[4];
1159} ccsr_cpm_fcc2_t;
1160
1161/* 0x91340-0x9137f: FCC3 */
1162typedef struct ccsr_cpm_fcc3 {
1163 uint gfmr;
1164 uint fpsmr;
1165 ushort ftodr;
1166 char res1[2];
1167 ushort fdsr;
1168 char res2[2];
1169 ushort fcce;
1170 char res3[2];
1171 ushort fccm;
1172 char res4[2];
1173 u_char fccs;
1174 char res5[3];
1175 char res[36];
1176} ccsr_cpm_fcc3_t;
1177
1178/* 0x91380-0x9139f: FCC1 extended */
1179typedef struct ccsr_cpm_fcc1_ext {
1180 uint firper;
1181 uint firer;
1182 uint firsr_h;
1183 uint firsr_l;
1184 u_char gfemr;
1185 char res[15];
1186
1187} ccsr_cpm_fcc1_ext_t;
1188
1189/* 0x913a0-0x913cf: FCC2 extended */
1190typedef struct ccsr_cpm_fcc2_ext {
1191 uint firper;
1192 uint firer;
1193 uint firsr_h;
1194 uint firsr_l;
1195 u_char gfemr;
1196 char res[31];
1197} ccsr_cpm_fcc2_ext_t;
1198
1199/* 0x913d0-0x913ff: FCC3 extended */
1200typedef struct ccsr_cpm_fcc3_ext {
1201 u_char gfemr;
1202 char res[47];
1203} ccsr_cpm_fcc3_ext_t;
1204
1205/* 0x91400-0x915ef: TC layers */
1206typedef struct ccsr_cpm_tmp1 {
53677ef1 1207 char res[496];
42d1f039
WD		 1208} ccsr_cpm_tmp1_t;
1209
1210/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
1211typedef struct ccsr_cpm_brg2 {
1212 uint brgc5;
1213 uint brgc6;
1214 uint brgc7;
1215 uint brgc8;
1216 char res[608];
1217} ccsr_cpm_brg2_t;
1218
1219/* 0x91860-0x919bf: I2C */
1220typedef struct ccsr_cpm_i2c {
1221 u_char i2mod;
1222 char res1[3];
1223 u_char i2add;
1224 char res2[3];
1225 u_char i2brg;
1226 char res3[3];
1227 u_char i2com;
1228 char res4[3];
1229 u_char i2cer;
1230 char res5[3];
1231 u_char i2cmr;
1232 char res6[331];
1233} ccsr_cpm_i2c_t;
1234
1235/* 0x919c0-0x919ef: CPM core */
1236typedef struct ccsr_cpm_cp {
1237 uint cpcr;
1238 uint rccr;
1239 char res1[14];
1240 ushort rter;
1241 char res2[2];
1242 ushort rtmr;
1243 ushort rtscr;
1244 char res3[2];
1245 uint rtsr;
1246 char res4[12];
1247} ccsr_cpm_cp_t;
1248
1249/* 0x919f0-0x919ff: BRGs:1,2,3,4 */
1250typedef struct ccsr_cpm_brg1 {
1251 uint brgc1;
1252 uint brgc2;
1253 uint brgc3;
1254 uint brgc4;
1255} ccsr_cpm_brg1_t;
1256
1257/* 0x91a00-0x91a9f: SCC1-SCC4 */
1258typedef struct ccsr_cpm_scc {
1259 uint gsmrl;
1260 uint gsmrh;
1261 ushort psmr;
1262 char res1[2];
1263 ushort todr;
1264 ushort dsr;
1265 ushort scce;
1266 char res2[2];
1267 ushort sccm;
1268 char res3;
1269 u_char sccs;
1270 char res4[8];
1271} ccsr_cpm_scc_t;
1272
1273/* 0x91a80-0x91a9f */
1274typedef struct ccsr_cpm_tmp2 {
53677ef1 1275 char res[32];
42d1f039
WD		 1276} ccsr_cpm_tmp2_t;
1277
1278/* 0x91aa0-0x91aff: SPI */
1279typedef struct ccsr_cpm_spi {
1280 ushort spmode;
1281 char res1[4];
1282 u_char spie;
1283 char res2[3];
1284 u_char spim;
1285 char res3[2];
1286 u_char spcom;
1287 char res4[82];
1288} ccsr_cpm_spi_t;
1289
1290/* 0x91b00-0x91b1f: CPM MUX */
1291typedef struct ccsr_cpm_mux {
1292 u_char cmxsi1cr;
1293 char res1;
1294 u_char cmxsi2cr;
1295 char res2;
1296 uint cmxfcr;
1297 uint cmxscr;
1298 char res3[2];
1299 ushort cmxuar;
1300 char res4[16];
1301} ccsr_cpm_mux_t;
1302
1303/* 0x91b20-0xbffff: SI,MCC,etc */
1304typedef struct ccsr_cpm_tmp3 {
1305 char res[58592];
1306} ccsr_cpm_tmp3_t;
1307
1308typedef struct ccsr_cpm_iram {
1309 unsigned long iram[8192];
1310 char res[98304];
1311} ccsr_cpm_iram_t;
1312
1313typedef struct ccsr_cpm {
1314 /* Some references are into the unique and known dpram spaces,
1315 * others are from the generic base.
1316 */
53677ef1
WD		 1317#define im_dprambase im_dpram1
1318 u_char im_dpram1[16*1024];
1319 char res1[16*1024];
1320 u_char im_dpram2[16*1024];
1321 char res2[16*1024];
1322 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1323 ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
1324 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1325 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1326 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
42d1f039
WD		 1327 ccsr_cpm_fcc1_t im_cpm_fcc1;
1328 ccsr_cpm_fcc2_t im_cpm_fcc2;
1329 ccsr_cpm_fcc3_t im_cpm_fcc3;
1330 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1331 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1332 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1333 ccsr_cpm_tmp1_t im_cpm_tmp1;
1334 ccsr_cpm_brg2_t im_cpm_brg2;
1335 ccsr_cpm_i2c_t im_cpm_i2c;
1336 ccsr_cpm_cp_t im_cpm_cp;
1337 ccsr_cpm_brg1_t im_cpm_brg1;
1338 ccsr_cpm_scc_t im_cpm_scc[4];
1339 ccsr_cpm_tmp2_t im_cpm_tmp2;
1340 ccsr_cpm_spi_t im_cpm_spi;
1341 ccsr_cpm_mux_t im_cpm_mux;
1342 ccsr_cpm_tmp3_t im_cpm_tmp3;
1343 ccsr_cpm_iram_t im_cpm_iram;
1344} ccsr_cpm_t;
1345#endif
42d1f039 1346
de1d0a69
JL		 1347/*
1348 * RapidIO Registers(0xc_0000-0xe_0000)
1349 */
42d1f039
WD		 1350typedef struct ccsr_rio {
1351 uint didcar; /* 0xc0000 - Device Identity Capability Register */
1352 uint dicar; /* 0xc0004 - Device Information Capability Register */
1353 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
1354 uint aicar; /* 0xc000c - Assembly Information Capability Register */
1355 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
1356 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
1357 uint socar; /* 0xc0018 - Source Operations Capability Register */
1358 uint docar; /* 0xc001c - Destination Operations Capability Register */
1359 char res1[32];
1360 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
1361 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
1362 char res2[4];
1363 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
1364 char res3[12];
1365 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
1366 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
1367 char res4[4];
1368 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
1369 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
1370 char res5[144];
1371 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
1372 char res6[28];
1373 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
1374 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
1375 char res7[20];
1376 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
1377 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
1378 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
1379 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
1380 char res8[12];
1381 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
1382 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
1383 char res9[65184];
1384 uint cr; /* 0xd0000 - Port Control Command and Status Register */
1385 char res10[12];
1386 uint pcr; /* 0xd0010 - Port Configuration Register */
1387 uint peir; /* 0xd0014 - Port Error Injection Register */
1388 char res11[3048];
1389 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1390 char res12[12];
1391 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1392 char res13[12];
1393 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1394 char res14[4];
1395 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1396 char res15[4];
1397 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1398 char res16[12];
1399 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1400 char res17[4];
1401 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1402 char res18[4];
1403 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1404 char res19[12];
1405 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1406 char res20[4];
1407 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1408 char res21[4];
1409 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1410 char res22[12];
1411 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1412 char res23[4];
1413 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1414 char res24[4];
1415 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1416 char res25[12];
1417 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1418 char res26[4];
1419 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1420 char res27[4];
1421 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1422 char res28[12];
1423 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1424 char res29[4];
1425 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1426 char res30[4];
1427 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1428 char res31[12];
1429 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1430 char res32[4];
1431 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1432 char res33[4];
1433 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1434 char res34[12];
1435 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1436 char res35[4];
1437 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1438 char res36[4];
1439 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1440 char res37[76];
1441 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1442 char res38[4];
1443 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1444 char res39[4];
1445 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1446 char res40[12];
1447 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1448 char res41[4];
1449 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1450 char res42[4];
1451 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1452 char res43[12];
1453 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1454 char res44[4];
1455 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1456 char res45[4];
1457 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1458 char res46[12];
1459 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1460 char res47[4];
1461 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1462 char res48[4];
1463 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1464 char res49[12];
1465 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1466 char res50[12];
1467 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1468 char res51[12];
1469 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1470 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1471 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1472 uint pecr; /* 0xd0e0c - Port Error Control Register */
1473 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1474 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1475 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1476 char res52[4];
1477 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1478 char res53[4];
1479 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1480 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1481 char res54[464];
1482 uint omr; /* 0xd1000 - Outbound Mode Register */
1483 uint osr; /* 0xd1004 - Outbound Status Register */
1484 uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1485 uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
1486 uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */
1487 uint osar; /* 0xd1014 - Outbound Unit Source Address Register */
1488 uint odpr; /* 0xd1018 - Outbound Destination Port Register */
1489 uint odatr; /* 0xd101c - Outbound Destination Attributes Register */
1490 uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */
1491 uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1492 uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
1493 char res55[52];
1494 uint imr; /* 0xd1060 - Outbound Mode Register */
1495 uint isr; /* 0xd1064 - Inbound Status Register */
1496 uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1497 uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
1498 uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
1499 uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
1500 char res56[1000];
1501 uint dmr; /* 0xd1460 - Doorbell Mode Register */
1502 uint dsr; /* 0xd1464 - Doorbell Status Register */
1503 uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
1504 uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */
1505 uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
1506 uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */
1507 char res57[104];
1508 uint pwmr; /* 0xd14e0 - Port-Write Mode Register */
1509 uint pwsr; /* 0xd14e4 - Port-Write Status Register */
1510 uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */
1511 uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */
1512 char res58[60176];
1513} ccsr_rio_t;
1514
c59e4091
HW		 1515/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
1516typedef struct par_io {
1517 uint cpodr; /* 0x100 */
1518 uint cpdat; /* 0x104 */
1519 uint cpdir1; /* 0x108 */
1520 uint cpdir2; /* 0x10c */
1521 uint cppar1; /* 0x110 */
1522 uint cppar2; /* 0x114 */
1523 char res[8];
1524}par_io_t;
1525
de1d0a69
JL		 1526/*
1527 * Global Utilities Register Block(0xe_0000-0xf_ffff)
1528 */
42d1f039
WD		 1529typedef struct ccsr_gur {
1530 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
c0391111
JJ		 1531#ifdef CONFIG_MPC8536
1532#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
1533#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
1534#else
1535#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
1536#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
1537#endif
b3d7f20f
HW		 1538#define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
1539#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
42d1f039 1540 uint porbmsr; /* 0xe0004 - POR boot mode status register */
53677ef1 1541#define MPC85xx_PORBMSR_HA 0x00070000
6442b71b 1542#define MPC85xx_PORBMSR_HA_SHIFT 16
42d1f039
WD		 1543 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1544 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
837f1ba0
ES		 1545#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
1546#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
1547#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
1548#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
ef50d6c0 1549#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
9427ccde 1550#define MPC85xx_PORDEVSR_PCI1 0x00800000
4442f45b 1551#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
6442b71b 1552#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
53677ef1
WD		 1553#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
1554#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
1555#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
1556#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
1557#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
837f1ba0 1558#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
53677ef1 1559#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
837f1ba0 1560#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
42d1f039 1561 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
88353a98 1562 uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
681c02d0 1563/* The 8544 RM says this is bit 26, but it's really bit 24 */
f7d190b1 1564#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
88353a98 1565 char res1[8];
42d1f039
WD		 1566 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1567 char res2[12];
1568 uint gpiocr; /* 0xe0030 - GPIO control register */
1569 char res3[12];
22b6dbc1
HW		 1570#if defined(CONFIG_MPC8569)
1571 uint plppar1;
1572 /* 0xe0040 - Platform port pin assignment register 1 */
1573 uint plppar2;
1574 /* 0xe0044 - Platform port pin assignment register 2 */
1575 uint plpdir1;
1576 /* 0xe0048 - Platform port pin direction register 1 */
1577 uint plpdir2;
1578 /* 0xe004c - Platform port pin direction register 2 */
1579#else
42d1f039
WD		 1580 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1581 char res4[12];
22b6dbc1 1582#endif
42d1f039
WD		 1583 uint gpindr; /* 0xe0050 - General-purpose input data register */
1584 char res5[12];
1585 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
80522dc8
AF		 1586#define MPC85xx_PMUXCR_SD_DATA 0x80000000
1587#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
1588#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
42d1f039
WD		 1589 char res6[12];
1590 uint devdisr; /* 0xe0070 - Device disable control */
837f1ba0
ES		 1591#define MPC85xx_DEVDISR_PCI1 0x80000000
1592#define MPC85xx_DEVDISR_PCI2 0x40000000
1593#define MPC85xx_DEVDISR_PCIE 0x20000000
1594#define MPC85xx_DEVDISR_LBC 0x08000000
1595#define MPC85xx_DEVDISR_PCIE2 0x04000000
1596#define MPC85xx_DEVDISR_PCIE3 0x02000000
1597#define MPC85xx_DEVDISR_SEC 0x01000000
1598#define MPC85xx_DEVDISR_SRIO 0x00080000
1599#define MPC85xx_DEVDISR_RMSG 0x00040000
53677ef1
WD		 1600#define MPC85xx_DEVDISR_DDR 0x00010000
1601#define MPC85xx_DEVDISR_CPU 0x00008000
1602#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
1603#define MPC85xx_DEVDISR_TB 0x00004000
1604#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
1605#define MPC85xx_DEVDISR_CPU1 0x00002000
1606#define MPC85xx_DEVDISR_TB1 0x00001000
837f1ba0
ES		 1607#define MPC85xx_DEVDISR_DMA 0x00000400
1608#define MPC85xx_DEVDISR_TSEC1 0x00000080
1609#define MPC85xx_DEVDISR_TSEC2 0x00000040
1610#define MPC85xx_DEVDISR_TSEC3 0x00000020
1611#define MPC85xx_DEVDISR_TSEC4 0x00000010
1612#define MPC85xx_DEVDISR_I2C 0x00000004
1613#define MPC85xx_DEVDISR_DUART 0x00000002
42d1f039
WD		 1614 char res7[12];
1615 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1616 char res8[12];
1617 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1618 char res9[12];
1619 uint pvr; /* 0xe00a0 - Processor version register */
1620 uint svr; /* 0xe00a4 - System version register */
982efcf2
AF		 1621 char res10a[8];
1622 uint rstcr; /* 0xe00b0 - Reset control register */
22b6dbc1 1623#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
c59e4091
HW		 1624 char res10b[76];
1625 par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
1626 char res10c[3136];
1627#else
982efcf2 1628 char res10b[3404];
c59e4091 1629#endif
42d1f039
WD		 1630 uint clkocr; /* 0xe0e00 - Clock out select register */
1631 char res11[12];
1632 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1633 char res12[12];
1634 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
d9b94f28
JL		 1635 char res13[248];
1636 uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */
1637 uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */
1638 uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
49b5aff4 1639 uint tsec12ioovcr; /* 0xe0f28 - eTSEC 1/2 IO override control */
d9b94f28 1640 uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
837f1ba0 1641 char res15[61648]; /* 0xe0f30 to 0xefffff */
42d1f039
WD		 1642} ccsr_gur_t;
1643
6d0f6bcf
JCPV		 1644#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
1645#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
1646#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000)
1647#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
1648#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000)
1649#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
1650#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000)
1651#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
1652#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000)
1653#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
7fa96a9a
MH		 1654#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000)
1655#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
6d0f6bcf
JCPV		 1656#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000)
1657#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
1658#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000)
1659#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
546b1032
PA		 1660#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000)
1661#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
6d0f6bcf
JCPV		 1662#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000)
1663#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
1664#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000)
1665#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
1666#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000)
1667#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
1668#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000)
1669#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
1670#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000)
1671#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
1672#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000)
1673#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
1674#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000)
1675#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
1676#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000)
1677#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
1678#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100)
1679#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
a07bf180
VM		 1680#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
1681#define CONFIG_SYS_MPC85xx_USB_ADDR \
1682 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
aafeefbd 1683
42d1f039 1684#endif /*__IMMAP_85xx__*/
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