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* Fix debug code in omap5912osk flash driver
[people/ms/u-boot.git] / include / asm-ppc / immap_85xx.h
CommitLineData
42d1f039
WD		 1/*
2 * MPC85xx Internal Memory Map
3 *
4 * Copyright(c) 2002,2003 Motorola Inc.
5 * Xianghua Xiao (x.xiao@motorola.com)
6 *
7 */
8
9#ifndef __IMMAP_85xx__
10#define __IMMAP_85xx__
11
12
13/* Local-Access Registers and ECM Registers(0x0000-0x2000) */
14
15typedef struct ccsr_local_ecm {
16 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
17 char res1[4];
18 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
19 char res2[4];
20 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
21 char res3[12];
22 uint bptr; /* 0x20 - Boot Page Translation Register */
23 char res4[3044];
24 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
25 char res5[4];
26 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
27 char res6[20];
28 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
29 char res7[4];
30 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
31 char res8[20];
32 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
33 char res9[4];
34 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
35 char res10[20];
36 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
37 char res11[4];
38 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
39 char res12[20];
40 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
41 char res13[4];
42 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
43 char res14[20];
44 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
45 char res15[4];
46 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
47 char res16[20];
48 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
49 char res17[4];
50 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
51 char res18[20];
52 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
53 char res19[4];
54 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
55 char res20[780];
56 uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
57 char res21[12];
58 uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
59 char res22[3564];
60 uint eedr; /* 0x1e00 - ECM Error Detect Register */
61 char res23[4];
62 uint eeer; /* 0x1e08 - ECM Error Enable Register */
63 uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */
64 uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */
65 char res24[492];
66} ccsr_local_ecm_t;
67
68
69/* DDR memory controller registers(0x2000-0x3000) */
70
71typedef struct ccsr_ddr {
72 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
73 char res1[4];
74 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
75 char res2[4];
76 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
77 char res3[4];
78 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
79 char res4[100];
80 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
81 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
82 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
83 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
84 char res5[120];
85 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
86 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
87 uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
88 char res6[4];
89 uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
90 char res7[8];
91 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
547b4cb2
WD		 92#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
93 char res7_5[8];
94 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */
95 char res8[3276];
96#else
42d1f039 97 char res8[3288];
547b4cb2 98#endif
42d1f039
WD		 99 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
100 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
101 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
102 char res9[20];
103 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
104 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
105 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
106 char res10[20];
107 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
108 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
109 uint err_int_en; /* 0x2e48 - DDR */
110 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
111 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
112 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
113 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
114 char res11[164];
115 uint debug_1; /* 0x2f00 */
116 uint debug_2;
117 uint debug_3;
118 uint debug_4;
119 char res12[240];
120} ccsr_ddr_t;
121
122
123/* I2C Registers(0x3000-0x4000) */
124
125typedef struct ccsr_i2c {
126 u_char i2cadr; /* 0x3000 - I2C Address Register */
127#define MPC85xx_I2CADR_MASK 0xFE
128 char res1[3];
129 u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */
130#define MPC85xx_I2CFDR_MASK 0x3F
131 char res2[3];
132 u_char i2ccr; /* 0x3008 - I2C Control Register */
133#define MPC85xx_I2CCR_MEN 0x80
134#define MPC85xx_I2CCR_MIEN 0x40
135#define MPC85xx_I2CCR_MSTA 0x20
136#define MPC85xx_I2CCR_MTX 0x10
137#define MPC85xx_I2CCR_TXAK 0x08
138#define MPC85xx_I2CCR_RSTA 0x04
139#define MPC85xx_I2CCR_BCST 0x01
140 char res3[3];
141 u_char i2csr; /* 0x300c - I2C Status Register */
142#define MPC85xx_I2CSR_MCF 0x80
143#define MPC85xx_I2CSR_MAAS 0x40
144#define MPC85xx_I2CSR_MBB 0x20
145#define MPC85xx_I2CSR_MAL 0x10
146#define MPC85xx_I2CSR_BCSTM 0x08
147#define MPC85xx_I2CSR_SRW 0x04
148#define MPC85xx_I2CSR_MIF 0x02
149#define MPC85xx_I2CSR_RXAK 0x01
150 char res4[3];
151 u_char i2cdr; /* 0x3010 - I2C Data Register */
152#define MPC85xx_I2CDR_DATA 0xFF
153 char res5[3];
154 u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */
155#define MPC85xx_I2CDFSRR 0x3F
156 char res6[4075];
157} ccsr_i2c_t;
158
03f5c550
WD		 159#if defined(CONFIG_MPC8540) \
160 || defined(CONFIG_MPC8541) \
161 || defined(CONFIG_MPC8555)
42d1f039
WD		 162/* DUART Registers(0x4000-0x5000) */
163typedef struct ccsr_duart {
164 char res1[1280];
165 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
166 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
167 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
168 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
169 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
170 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
171 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
172 u_char uscr1; /* 0x4507 - UART1 Scratch Register */
173 char res2[8];
174 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
175 char res3[239];
176 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
177 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
178 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
179 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
180 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
181 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
182 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
183 u_char uscr2; /* 0x4607 - UART2 Scratch Register */
184 char res4[8];
185 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
186 char res5[2543];
187} ccsr_duart_t;
188#else /* MPC8560 uses UART on its CPM */
189typedef struct ccsr_duart {
190 char res[4096];
191} ccsr_duart_t;
192#endif
193
194/* Local Bus Controller Registers(0x5000-0x6000) */
195/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
196
197typedef struct ccsr_lbc {
198 uint br0; /* 0x5000 - LBC Base Register 0 */
199 uint or0; /* 0x5004 - LBC Options Register 0 */
200 uint br1; /* 0x5008 - LBC Base Register 1 */
201 uint or1; /* 0x500c - LBC Options Register 1 */
202 uint br2; /* 0x5010 - LBC Base Register 2 */
203 uint or2; /* 0x5014 - LBC Options Register 2 */
204 uint br3; /* 0x5018 - LBC Base Register 3 */
205 uint or3; /* 0x501c - LBC Options Register 3 */
206 uint br4; /* 0x5020 - LBC Base Register 4 */
207 uint or4; /* 0x5024 - LBC Options Register 4 */
208 uint br5; /* 0x5028 - LBC Base Register 5 */
209 uint or5; /* 0x502c - LBC Options Register 5 */
210 uint br6; /* 0x5030 - LBC Base Register 6 */
211 uint or6; /* 0x5034 - LBC Options Register 6 */
212 uint br7; /* 0x5038 - LBC Base Register 7 */
213 uint or7; /* 0x503c - LBC Options Register 7 */
214 char res1[40];
215 uint mar; /* 0x5068 - LBC UPM Address Register */
216 char res2[4];
217 uint mamr; /* 0x5070 - LBC UPMA Mode Register */
218 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
219 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
220 char res3[8];
221 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
222 uint mdr; /* 0x5088 - LBC UPM Data Register */
223 char res4[8];
224 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
225 char res5[8];
226 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
227 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
228 char res6[8];
229 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
230 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
231 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
232 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
233 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
234 char res7[12];
235 uint lbcr; /* 0x50d0 - LBC Configuration Register */
236 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
237 char res8[12072];
238} ccsr_lbc_t;
239
240
241/* PCI Registers(0x8000-0x9000) */
242/* Omitting Reserved(0x9000-0x2_0000) */
243
244typedef struct ccsr_pcix {
245 uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
246 uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
247 uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */
248 char res1[3060];
249 uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
250 uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
251 uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
252 uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
253 uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
254 char res2[12];
255 uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
256 uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
257 uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
258 uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
259 uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
260 char res3[12];
261 uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
262 uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
263 uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
264 uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
265 uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
266 char res4[12];
267 uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
268 uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
269 uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
270 uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
271 uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
272 char res5[12];
273 uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
274 uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
275 uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
276 uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
277 uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
278 char res6[268];
279 uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */
280 uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
281 uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
282 uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
283 uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
284 char res7[12];
285 uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */
286 uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
287 uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
288 uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
289 uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
290 char res8[12];
291 uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */
292 uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
293 uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
294 char res9[4];
295 uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
296 char res10[12];
297 uint pedr; /* 0x8e00 - PCIX Error Detect Register */
298 uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */
299 uint peer; /* 0x8e08 - PCIX Error Enable Register */
300 uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */
301 uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */
302 uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
303 uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
304 uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
305 char res11[94688];
306} ccsr_pcix_t;
307
308
309/* L2 Cache Registers(0x2_0000-0x2_1000) */
310
311typedef struct ccsr_l2cache {
312 uint l2ctl; /* 0x20000 - L2 configuration register 0 */
313 char res1[12];
314 uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */
315 char res2[4];
316 uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */
317 char res3[4];
318 uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */
319 char res4[4];
320 uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */
321 char res5[4];
322 uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */
323 char res6[4];
324 uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */
325 char res7[4];
326 uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */
327 char res8[4];
328 uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */
329 char res9[180];
330 uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */
331 char res10[4];
332 uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */
333 char res11[3316];
334 uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */
335 uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */
336 uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */
337 char res12[20];
338 uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */
339 uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */
340 uint l2captecc; /* 0x20e28 - L2 error ECC capture register */
341 char res13[20];
342 uint l2errdet; /* 0x20e40 - L2 error detect register */
343 uint l2errdis; /* 0x20e44 - L2 error disable register */
344 uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */
345 uint l2errattr; /* 0x20e4c - L2 error attributes capture register */
346 uint l2erraddr; /* 0x20e50 - L2 error address capture register */
347 char res14[4];
348 uint l2errctl; /* 0x20e58 - L2 error control register */
349 char res15[420];
350} ccsr_l2cache_t;
351
352
353/* DMA Registers(0x2_1000-0x2_2000) */
354
355typedef struct ccsr_dma {
356 char res1[256];
357 uint mr0; /* 0x21100 - DMA 0 Mode Register */
358 uint sr0; /* 0x21104 - DMA 0 Status Register */
359 char res2[4];
360 uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
361 uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
362 uint sar0; /* 0x21114 - DMA 0 Source Address Register */
363 uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
364 uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
365 uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
366 char res3[4];
367 uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
368 char res4[8];
369 uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
370 char res5[4];
371 uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
372 uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
373 uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
374 char res6[56];
375 uint mr1; /* 0x21180 - DMA 1 Mode Register */
376 uint sr1; /* 0x21184 - DMA 1 Status Register */
377 char res7[4];
378 uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
379 uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
380 uint sar1; /* 0x21194 - DMA 1 Source Address Register */
381 uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
382 uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
383 uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
384 char res8[4];
385 uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
386 char res9[8];
387 uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
388 char res10[4];
389 uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
390 uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
391 uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
392 char res11[56];
393 uint mr2; /* 0x21200 - DMA 2 Mode Register */
394 uint sr2; /* 0x21204 - DMA 2 Status Register */
395 char res12[4];
396 uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
397 uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
398 uint sar2; /* 0x21214 - DMA 2 Source Address Register */
399 uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
400 uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
401 uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
402 char res13[4];
403 uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
404 char res14[8];
405 uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
406 char res15[4];
407 uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
408 uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
409 uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
410 char res16[56];
411 uint mr3; /* 0x21280 - DMA 3 Mode Register */
412 uint sr3; /* 0x21284 - DMA 3 Status Register */
413 char res17[4];
414 uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
415 uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
416 uint sar3; /* 0x21294 - DMA 3 Source Address Register */
417 uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
418 uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
419 uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
420 char res18[4];
421 uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
422 char res19[8];
423 uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
424 char res20[4];
425 uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
426 uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
427 uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
428 char res21[56];
429 uint dgsr; /* 0x21300 - DMA General Status Register */
430 char res22[11516];
431} ccsr_dma_t;
432
433/* tsec1 tsec2: 24000-26000 */
434typedef struct ccsr_tsec {
435 char res1[16];
436 uint ievent; /* 0x24010 - Interrupt Event Register */
437 uint imask; /* 0x24014 - Interrupt Mask Register */
438 uint edis; /* 0x24018 - Error Disabled Register */
439 char res2[4];
440 uint ecntrl; /* 0x24020 - Ethernet Control Register */
441 uint minflr; /* 0x24024 - Minimum Frame Length Register */
442 uint ptv; /* 0x24028 - Pause Time Value Register */
443 uint dmactrl; /* 0x2402c - DMA Control Register */
444 uint tbipa; /* 0x24030 - TBI PHY Address Register */
445 char res3[88];
446 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
447 char res4[8];
448 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
449 uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
450 char res5[96];
451 uint tctrl; /* 0x24100 - Transmit Control Register */
452 uint tstat; /* 0x24104 - Transmit Status Register */
453 char res6[4];
454 uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
455 char res7[16];
456 uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
457 uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
458 char res8[88];
459 uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
460 uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
461 char res9[120];
462 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
463 uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
464 char res10[168];
465 uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
466 uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
467 uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
468 uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
469 uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
470 uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
471 uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
472 char res11[52];
473 uint rctrl; /* 0x24300 - Receive Control Register */
474 uint rstat; /* 0x24304 - Receive Status Register */
475 char res12[4];
476 uint rbdlen; /* 0x2430c - RxBD Data Length Register */
477 char res13[16];
478 uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
479 uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
480 char res14[24];
481 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
482 uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
483 char res15[56];
484 uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
485 uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
486 uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
487 uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
488 uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
489 uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
490 uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
491 uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
492 char res16[96];
493 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
494 uint rbase; /* 0x24404 - Receive Descriptor Base Address */
495 uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
496 uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
497 uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
498 uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
499 uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
500 uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
501 char res17[224];
502 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
503 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
504 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
505 uint hafdup; /* 0x2450c - Half Duplex Register */
506 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
507 char res18[12];
508 uint miimcfg; /* 0x24520 - MII Management Configuration Register */
509 uint miimcom; /* 0x24524 - MII Management Command Register */
510 uint miimadd; /* 0x24528 - MII Management Address Register */
511 uint miimcon; /* 0x2452c - MII Management Control Register */
512 uint miimstat; /* 0x24530 - MII Management Status Register */
513 uint miimind; /* 0x24534 - MII Management Indicator Register */
514 char res19[4];
515 uint ifstat; /* 0x2453c - Interface Status Register */
516 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
517 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
518 char res20[312];
519 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
520 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
521 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
522 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
523 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
524 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
525 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
526 uint rbyt; /* 0x2469c - Receive Byte Counter */
527 uint rpkt; /* 0x246a0 - Receive Packet Counter */
528 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
529 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
530 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
531 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
532 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
533 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
534 uint raln; /* 0x246bc - Receive Alignment Error Counter */
535 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
536 uint rcde; /* 0x246c4 - Receive Code Error Counter */
537 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
538 uint rund; /* 0x246cc - Receive Undersize Packet Counter */
539 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
540 uint rfrg; /* 0x246d4 - Receive Fragments Counter */
541 uint rjbr; /* 0x246d8 - Receive Jabber Counter */
542 uint rdrp; /* 0x246dc - Receive Drop Counter */
543 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
544 uint tpkt; /* 0x246e4 - Transmit Packet Counter */
545 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
546 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
547 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
548 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
549 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
550 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
551 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
552 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
553 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
554 uint tncl; /* 0x2470c - Transmit Total Collision Counter */
555 char res21[4];
556 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
557 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
558 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
559 uint txcf; /* 0x24720 - Transmit Control Frame Counter */
560 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
561 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
562 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
563 uint car1; /* 0x24730 - Carry Register One */
564 uint car2; /* 0x24734 - Carry Register Two */
565 uint cam1; /* 0x24738 - Carry Mask Register One */
566 uint cam2; /* 0x2473c - Carry Mask Register Two */
567 char res22[192];
568 uint iaddr0; /* 0x24800 - Indivdual address register 0 */
569 uint iaddr1; /* 0x24804 - Indivdual address register 1 */
570 uint iaddr2; /* 0x24808 - Indivdual address register 2 */
571 uint iaddr3; /* 0x2480c - Indivdual address register 3 */
572 uint iaddr4; /* 0x24810 - Indivdual address register 4 */
573 uint iaddr5; /* 0x24814 - Indivdual address register 5 */
574 uint iaddr6; /* 0x24818 - Indivdual address register 6 */
575 uint iaddr7; /* 0x2481c - Indivdual address register 7 */
576 char res23[96];
577 uint gaddr0; /* 0x24880 - Global address register 0 */
578 uint gaddr1; /* 0x24884 - Global address register 1 */
579 uint gaddr2; /* 0x24888 - Global address register 2 */
580 uint gaddr3; /* 0x2488c - Global address register 3 */
581 uint gaddr4; /* 0x24890 - Global address register 4 */
582 uint gaddr5; /* 0x24894 - Global address register 5 */
583 uint gaddr6; /* 0x24898 - Global address register 6 */
584 uint gaddr7; /* 0x2489c - Global address register 7 */
585 char res24[96];
586 uint pmd0; /* 0x24900 - Pattern Match Data Register */
587 char res25[4];
588 uint pmask0; /* 0x24908 - Pattern Mask Register */
589 char res26[4];
590 uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
591 char res27[4];
592 uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
593 uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
594 uint pmd1; /* 0x24920 - Pattern Match Data Register */
595 char res28[4];
596 uint pmask1; /* 0x24928 - Pattern Mask Register */
597 char res29[4];
598 uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
599 char res30[4];
600 uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
601 uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
602 uint pmd2; /* 0x24940 - Pattern Match Data Register */
603 char res31[4];
604 uint pmask2; /* 0x24948 - Pattern Mask Register */
605 char res32[4];
606 uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
607 char res33[4];
608 uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
609 uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
610 uint pmd3; /* 0x24960 - Pattern Match Data Register */
611 char res34[4];
612 uint pmask3; /* 0x24968 - Pattern Mask Register */
613 char res35[4];
614 uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
615 char res36[4];
616 uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
617 uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
618 uint pmd4; /* 0x24980 - Pattern Match Data Register */
619 char res37[4];
620 uint pmask4; /* 0x24988 - Pattern Mask Register */
621 char res38[4];
622 uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
623 char res39[4];
624 uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
625 uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
626 uint pmd5; /* 0x249a0 - Pattern Match Data Register */
627 char res40[4];
628 uint pmask5; /* 0x249a8 - Pattern Mask Register */
629 char res41[4];
630 uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
631 char res42[4];
632 uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
633 uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
634 uint pmd6; /* 0x249c0 - Pattern Match Data Register */
635 char res43[4];
636 uint pmask6; /* 0x249c8 - Pattern Mask Register */
637 char res44[4];
638 uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
639 char res45[4];
640 uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
641 uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
642 uint pmd7; /* 0x249e0 - Pattern Match Data Register */
643 char res46[4];
644 uint pmask7; /* 0x249e8 - Pattern Mask Register */
645 char res47[4];
646 uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
647 char res48[4];
648 uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
649 uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
650 uint pmd8; /* 0x24a00 - Pattern Match Data Register */
651 char res49[4];
652 uint pmask8; /* 0x24a08 - Pattern Mask Register */
653 char res50[4];
654 uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
655 char res51[4];
656 uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
657 uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
658 uint pmd9; /* 0x24a20 - Pattern Match Data Register */
659 char res52[4];
660 uint pmask9; /* 0x24a28 - Pattern Mask Register */
661 char res53[4];
662 uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
663 char res54[4];
664 uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
665 uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
666 uint pmd10; /* 0x24a40 - Pattern Match Data Register */
667 char res55[4];
668 uint pmask10; /* 0x24a48 - Pattern Mask Register */
669 char res56[4];
670 uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
671 char res57[4];
672 uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
673 uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
674 uint pmd11; /* 0x24a60 - Pattern Match Data Register */
675 char res58[4];
676 uint pmask11; /* 0x24a68 - Pattern Mask Register */
677 char res59[4];
678 uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
679 char res60[4];
680 uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
681 uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
682 uint pmd12; /* 0x24a80 - Pattern Match Data Register */
683 char res61[4];
684 uint pmask12; /* 0x24a88 - Pattern Mask Register */
685 char res62[4];
686 uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
687 char res63[4];
688 uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
689 uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
690 uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
691 char res64[4];
692 uint pmask13; /* 0x24aa8 - Pattern Mask Register */
693 char res65[4];
694 uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
695 char res66[4];
696 uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
697 uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
698 uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
699 char res67[4];
700 uint pmask14; /* 0x24ac8 - Pattern Mask Register */
701 char res68[4];
702 uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
703 char res69[4];
704 uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
705 uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
706 uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
707 char res70[4];
708 uint pmask15; /* 0x24ae8 - Pattern Mask Register */
709 char res71[4];
710 uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
711 char res72[4];
712 uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
713 uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
714 char res73[248];
715 uint attr; /* 0x24bf8 - Attributes Register */
716 uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
717 char res74[1024];
718} ccsr_tsec_t;
719
720/* PIC Registers(0x2_6000-0x4_0000-0x8_0000) */
721
722typedef struct ccsr_pic {
723 char res0[106496]; /* 0x26000-0x40000 */
724 char res1[64];
725 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
726 char res2[12];
727 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
728 char res3[12];
729 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
730 char res4[12];
731 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
732 char res5[12];
733 uint ctpr; /* 0x40080 - Current Task Priority Register */
734 char res6[12];
735 uint whoami; /* 0x40090 - Who Am I Register */
736 char res7[12];
737 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
738 char res8[12];
739 uint eoi; /* 0x400b0 - End Of Interrupt Register */
740 char res9[3916];
741 uint frr; /* 0x41000 - Feature Reporting Register */
742 char res10[28];
743 uint gcr; /* 0x41020 - Global Configuration Register */
744 char res11[92];
745 uint vir; /* 0x41080 - Vendor Identification Register */
746 char res12[12];
747 uint pir; /* 0x41090 - Processor Initialization Register */
748 char res13[12];
749 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
750 char res14[12];
751 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
752 char res15[12];
753 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
754 char res16[12];
755 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
756 char res17[12];
757 uint svr; /* 0x410e0 - Spurious Vector Register */
758 char res18[12];
759 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
760 char res19[12];
761 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
762 char res20[12];
763 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
764 char res21[12];
765 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
766 char res22[12];
767 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
768 char res23[12];
769 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
770 char res24[12];
771 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
772 char res25[12];
773 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
774 char res26[12];
775 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
776 char res27[12];
777 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
778 char res28[12];
779 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
780 char res29[12];
781 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
782 char res30[12];
783 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
784 char res31[12];
785 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
786 char res32[12];
787 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
788 char res33[12];
789 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
790 char res34[12];
791 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
792 char res35[268];
793 uint tcr; /* 0x41300 - Timer Control Register */
794 char res36[12];
795 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
796 char res37[12];
797 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
798 char res38[12];
799 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
800 char res39[12];
801 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
802 char res40[188];
803 uint msgr0; /* 0x41400 - Message Register 0 */
804 char res41[12];
805 uint msgr1; /* 0x41410 - Message Register 1 */
806 char res42[12];
807 uint msgr2; /* 0x41420 - Message Register 2 */
808 char res43[12];
809 uint msgr3; /* 0x41430 - Message Register 3 */
810 char res44[204];
811 uint mer; /* 0x41500 - Message Enable Register */
812 char res45[12];
813 uint msr; /* 0x41510 - Message Status Register */
814 char res46[60140];
815 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
816 char res47[12];
817 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
818 char res48[12];
819 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
820 char res49[12];
821 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
822 char res50[12];
823 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
824 char res51[12];
825 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
826 char res52[12];
827 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
828 char res53[12];
829 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
830 char res54[12];
831 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
832 char res55[12];
833 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
834 char res56[12];
835 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
836 char res57[12];
837 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
838 char res58[12];
839 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
840 char res59[12];
841 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
842 char res60[12];
843 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
844 char res61[12];
845 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
846 char res62[12];
847 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
848 char res63[12];
849 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
850 char res64[12];
851 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
852 char res65[12];
853 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
854 char res66[12];
855 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
856 char res67[12];
857 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
858 char res68[12];
859 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
860 char res69[12];
861 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
862 char res70[140];
863 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
864 char res71[12];
865 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
866 char res72[12];
867 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
868 char res73[12];
869 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
870 char res74[12];
871 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
872 char res75[12];
873 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
874 char res76[12];
875 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
876 char res77[12];
877 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
878 char res78[12];
879 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
880 char res79[12];
881 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
882 char res80[12];
883 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
884 char res81[12];
885 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
886 char res82[12];
887 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
888 char res83[12];
889 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
890 char res84[12];
891 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
892 char res85[12];
893 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
894 char res86[12];
895 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
896 char res87[12];
897 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
898 char res88[12];
899 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
900 char res89[12];
901 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
902 char res90[12];
903 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
904 char res91[12];
905 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
906 char res92[12];
907 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
908 char res93[12];
909 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
910 char res94[12];
911 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
912 char res95[12];
913 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
914 char res96[12];
915 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
916 char res97[12];
917 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
918 char res98[12];
919 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
920 char res99[12];
921 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
922 char res100[12];
923 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
924 char res101[12];
925 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
926 char res102[12];
927 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
928 char res103[12];
929 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
930 char res104[12];
931 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
932 char res105[12];
933 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
934 char res106[12];
935 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
936 char res107[12];
937 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
938 char res108[12];
939 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
940 char res109[12];
941 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
942 char res110[12];
943 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
944 char res111[12];
945 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
946 char res112[12];
947 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
948 char res113[12];
949 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
950 char res114[12];
951 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
952 char res115[12];
953 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
954 char res116[12];
955 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
956 char res117[12];
957 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
958 char res118[12];
959 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
960 char res119[12];
961 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
962 char res120[12];
963 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
964 char res121[12];
965 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
966 char res122[12];
967 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
968 char res123[12];
969 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
970 char res124[12];
971 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
972 char res125[12];
973 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
974 char res126[12];
975 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
976 char res127[12];
977 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
978 char res128[12];
979 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
980 char res129[12];
981 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
982 char res130[12];
983 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
984 char res131[12];
985 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
986 char res132[12];
987 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
988 char res133[12];
989 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
990 char res134[4108];
991 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
992 char res135[12];
993 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
994 char res136[12];
995 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
996 char res137[12];
997 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
998 char res138[12];
999 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
1000 char res139[12];
1001 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
1002 char res140[12];
1003 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
1004 char res141[12];
1005 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
1006 char res142[59852];
1007 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
1008 char res143[12];
1009 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
1010 char res144[12];
1011 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
1012 char res145[12];
1013 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
1014 char res146[12];
1015 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
1016 char res147[12];
1017 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
1018 char res148[12];
1019 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
1020 char res149[12];
1021 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
1022 char res150[130892];
1023} ccsr_pic_t;
1024
1025/* CPM Block(0x8_0000-0xc_0000) */
03f5c550
WD		 1026#if defined(CONFIG_MPC8540) \
1027 || defined(CONFIG_MPC8541) \
1028 || defined(CONFIG_MPC8555)
42d1f039
WD		 1029typedef struct ccsr_cpm {
1030 char res[262144];
1031} ccsr_cpm_t;
1032#else
1033/* 0x8000-0x8ffff:DPARM */
1034
1035/* 0x9000-0x90bff: General SIU */
1036typedef struct ccsr_cpm_siu {
1037 char res1[80];
1038 uint smaer;
1039 uint smser;
1040 uint smevr;
1041 char res2[4];
1042 uint lmaer;
1043 uint lmser;
1044 uint lmevr;
1045 char res3[2964];
1046} ccsr_cpm_siu_t;
1047
1048/* 0x90c00-0x90cff: Interrupt Controller */
1049typedef struct ccsr_cpm_intctl {
1050 ushort sicr;
1051 char res1[2];
1052 uint sivec;
1053 uint sipnrh;
1054 uint sipnrl;
1055 uint siprr;
1056 uint scprrh;
1057 uint scprrl;
1058 uint simrh;
1059 uint simrl;
1060 uint siexr;
1061 char res2[88];
1062 uint sccr;
1063 char res3[124];
1064} ccsr_cpm_intctl_t;
1065
1066/* 0x90d00-0x90d7f: input/output port */
1067typedef struct ccsr_cpm_iop {
1068 uint pdira;
1069 uint ppara;
1070 uint psora;
1071 uint podra;
1072 uint pdata;
1073 char res1[12];
1074 uint pdirb;
1075 uint pparb;
1076 uint psorb;
1077 uint podrb;
1078 uint pdatb;
1079 char res2[12];
1080 uint pdirc;
1081 uint pparc;
1082 uint psorc;
1083 uint podrc;
1084 uint pdatc;
1085 char res3[12];
1086 uint pdird;
1087 uint ppard;
1088 uint psord;
1089 uint podrd;
1090 uint pdatd;
1091 char res4[12];
1092} ccsr_cpm_iop_t;
1093
1094/* 0x90d80-0x91017: CPM timers */
1095typedef struct ccsr_cpm_timer {
1096 u_char tgcr1;
1097 char res1[3];
1098 u_char tgcr2;
1099 char res2[11];
1100 ushort tmr1;
1101 ushort tmr2;
1102 ushort trr1;
1103 ushort trr2;
1104 ushort tcr1;
1105 ushort tcr2;
1106 ushort tcn1;
1107 ushort tcn2;
1108 ushort tmr3;
1109 ushort tmr4;
1110 ushort trr3;
1111 ushort trr4;
1112 ushort tcr3;
1113 ushort tcr4;
1114 ushort tcn3;
1115 ushort tcn4;
1116 ushort ter1;
1117 ushort ter2;
1118 ushort ter3;
1119 ushort ter4;
1120 char res3[608];
1121} ccsr_cpm_timer_t;
1122
1123/* 0x91018-0x912ff: SDMA */
1124typedef struct ccsr_cpm_sdma {
1125 uchar sdsr;
1126 char res1[3];
1127 uchar sdmr;
1128 char res2[739];
1129} ccsr_cpm_sdma_t;
1130
1131/* 0x91300-0x9131f: FCC1 */
1132typedef struct ccsr_cpm_fcc1 {
1133 uint gfmr;
1134 uint fpsmr;
1135 ushort ftodr;
1136 char res1[2];
1137 ushort fdsr;
1138 char res2[2];
1139 ushort fcce;
1140 char res3[2];
1141 ushort fccm;
1142 char res4[2];
1143 u_char fccs;
1144 char res5[3];
1145 u_char ftirr_phy[4];
1146} ccsr_cpm_fcc1_t;
1147
1148/* 0x91320-0x9133f: FCC2 */
1149typedef struct ccsr_cpm_fcc2 {
1150 uint gfmr;
1151 uint fpsmr;
1152 ushort ftodr;
1153 char res1[2];
1154 ushort fdsr;
1155 char res2[2];
1156 ushort fcce;
1157 char res3[2];
1158 ushort fccm;
1159 char res4[2];
1160 u_char fccs;
1161 char res5[3];
1162 u_char ftirr_phy[4];
1163} ccsr_cpm_fcc2_t;
1164
1165/* 0x91340-0x9137f: FCC3 */
1166typedef struct ccsr_cpm_fcc3 {
1167 uint gfmr;
1168 uint fpsmr;
1169 ushort ftodr;
1170 char res1[2];
1171 ushort fdsr;
1172 char res2[2];
1173 ushort fcce;
1174 char res3[2];
1175 ushort fccm;
1176 char res4[2];
1177 u_char fccs;
1178 char res5[3];
1179 char res[36];
1180} ccsr_cpm_fcc3_t;
1181
1182/* 0x91380-0x9139f: FCC1 extended */
1183typedef struct ccsr_cpm_fcc1_ext {
1184 uint firper;
1185 uint firer;
1186 uint firsr_h;
1187 uint firsr_l;
1188 u_char gfemr;
1189 char res[15];
1190
1191} ccsr_cpm_fcc1_ext_t;
1192
1193/* 0x913a0-0x913cf: FCC2 extended */
1194typedef struct ccsr_cpm_fcc2_ext {
1195 uint firper;
1196 uint firer;
1197 uint firsr_h;
1198 uint firsr_l;
1199 u_char gfemr;
1200 char res[31];
1201} ccsr_cpm_fcc2_ext_t;
1202
1203/* 0x913d0-0x913ff: FCC3 extended */
1204typedef struct ccsr_cpm_fcc3_ext {
1205 u_char gfemr;
1206 char res[47];
1207} ccsr_cpm_fcc3_ext_t;
1208
1209/* 0x91400-0x915ef: TC layers */
1210typedef struct ccsr_cpm_tmp1 {
1211 char res[496];
1212} ccsr_cpm_tmp1_t;
1213
1214/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
1215typedef struct ccsr_cpm_brg2 {
1216 uint brgc5;
1217 uint brgc6;
1218 uint brgc7;
1219 uint brgc8;
1220 char res[608];
1221} ccsr_cpm_brg2_t;
1222
1223/* 0x91860-0x919bf: I2C */
1224typedef struct ccsr_cpm_i2c {
1225 u_char i2mod;
1226 char res1[3];
1227 u_char i2add;
1228 char res2[3];
1229 u_char i2brg;
1230 char res3[3];
1231 u_char i2com;
1232 char res4[3];
1233 u_char i2cer;
1234 char res5[3];
1235 u_char i2cmr;
1236 char res6[331];
1237} ccsr_cpm_i2c_t;
1238
1239/* 0x919c0-0x919ef: CPM core */
1240typedef struct ccsr_cpm_cp {
1241 uint cpcr;
1242 uint rccr;
1243 char res1[14];
1244 ushort rter;
1245 char res2[2];
1246 ushort rtmr;
1247 ushort rtscr;
1248 char res3[2];
1249 uint rtsr;
1250 char res4[12];
1251} ccsr_cpm_cp_t;
1252
1253/* 0x919f0-0x919ff: BRGs:1,2,3,4 */
1254typedef struct ccsr_cpm_brg1 {
1255 uint brgc1;
1256 uint brgc2;
1257 uint brgc3;
1258 uint brgc4;
1259} ccsr_cpm_brg1_t;
1260
1261/* 0x91a00-0x91a9f: SCC1-SCC4 */
1262typedef struct ccsr_cpm_scc {
1263 uint gsmrl;
1264 uint gsmrh;
1265 ushort psmr;
1266 char res1[2];
1267 ushort todr;
1268 ushort dsr;
1269 ushort scce;
1270 char res2[2];
1271 ushort sccm;
1272 char res3;
1273 u_char sccs;
1274 char res4[8];
1275} ccsr_cpm_scc_t;
1276
1277/* 0x91a80-0x91a9f */
1278typedef struct ccsr_cpm_tmp2 {
1279 char res[32];
1280} ccsr_cpm_tmp2_t;
1281
1282/* 0x91aa0-0x91aff: SPI */
1283typedef struct ccsr_cpm_spi {
1284 ushort spmode;
1285 char res1[4];
1286 u_char spie;
1287 char res2[3];
1288 u_char spim;
1289 char res3[2];
1290 u_char spcom;
1291 char res4[82];
1292} ccsr_cpm_spi_t;
1293
1294/* 0x91b00-0x91b1f: CPM MUX */
1295typedef struct ccsr_cpm_mux {
1296 u_char cmxsi1cr;
1297 char res1;
1298 u_char cmxsi2cr;
1299 char res2;
1300 uint cmxfcr;
1301 uint cmxscr;
1302 char res3[2];
1303 ushort cmxuar;
1304 char res4[16];
1305} ccsr_cpm_mux_t;
1306
1307/* 0x91b20-0xbffff: SI,MCC,etc */
1308typedef struct ccsr_cpm_tmp3 {
1309 char res[58592];
1310} ccsr_cpm_tmp3_t;
1311
1312typedef struct ccsr_cpm_iram {
1313 unsigned long iram[8192];
1314 char res[98304];
1315} ccsr_cpm_iram_t;
1316
1317typedef struct ccsr_cpm {
1318 /* Some references are into the unique and known dpram spaces,
1319 * others are from the generic base.
1320 */
1321#define im_dprambase im_dpram1
1322 u_char im_dpram1[16*1024];
1323 char res1[16*1024];
1324 u_char im_dpram2[16*1024];
1325 char res2[16*1024];
1326
1327 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1328 ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
1329 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1330 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1331 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
1332 ccsr_cpm_fcc1_t im_cpm_fcc1;
1333 ccsr_cpm_fcc2_t im_cpm_fcc2;
1334 ccsr_cpm_fcc3_t im_cpm_fcc3;
1335 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1336 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1337 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1338 ccsr_cpm_tmp1_t im_cpm_tmp1;
1339 ccsr_cpm_brg2_t im_cpm_brg2;
1340 ccsr_cpm_i2c_t im_cpm_i2c;
1341 ccsr_cpm_cp_t im_cpm_cp;
1342 ccsr_cpm_brg1_t im_cpm_brg1;
1343 ccsr_cpm_scc_t im_cpm_scc[4];
1344 ccsr_cpm_tmp2_t im_cpm_tmp2;
1345 ccsr_cpm_spi_t im_cpm_spi;
1346 ccsr_cpm_mux_t im_cpm_mux;
1347 ccsr_cpm_tmp3_t im_cpm_tmp3;
1348 ccsr_cpm_iram_t im_cpm_iram;
1349} ccsr_cpm_t;
1350#endif
1351/* RapidIO Registers(0xc_0000-0xe_0000) */
1352
1353typedef struct ccsr_rio {
1354 uint didcar; /* 0xc0000 - Device Identity Capability Register */
1355 uint dicar; /* 0xc0004 - Device Information Capability Register */
1356 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
1357 uint aicar; /* 0xc000c - Assembly Information Capability Register */
1358 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
1359 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
1360 uint socar; /* 0xc0018 - Source Operations Capability Register */
1361 uint docar; /* 0xc001c - Destination Operations Capability Register */
1362 char res1[32];
1363 uint msr; /* 0xc0040 - Mailbox Command And Status Register */
1364 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
1365 char res2[4];
1366 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
1367 char res3[12];
1368 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
1369 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
1370 char res4[4];
1371 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
1372 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
1373 char res5[144];
1374 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
1375 char res6[28];
1376 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
1377 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
1378 char res7[20];
1379 uint pgccsr; /* 0xc013c - Port General Command and Status Register */
1380 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
1381 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
1382 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
1383 char res8[12];
1384 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
1385 uint pccsr; /* 0xc015c - Port Control Command and Status Register */
1386 char res9[65184];
1387 uint cr; /* 0xd0000 - Port Control Command and Status Register */
1388 char res10[12];
1389 uint pcr; /* 0xd0010 - Port Configuration Register */
1390 uint peir; /* 0xd0014 - Port Error Injection Register */
1391 char res11[3048];
1392 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
1393 char res12[12];
1394 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
1395 char res13[12];
1396 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
1397 char res14[4];
1398 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
1399 char res15[4];
1400 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
1401 char res16[12];
1402 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
1403 char res17[4];
1404 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
1405 char res18[4];
1406 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
1407 char res19[12];
1408 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
1409 char res20[4];
1410 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
1411 char res21[4];
1412 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
1413 char res22[12];
1414 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
1415 char res23[4];
1416 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
1417 char res24[4];
1418 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
1419 char res25[12];
1420 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
1421 char res26[4];
1422 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
1423 char res27[4];
1424 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
1425 char res28[12];
1426 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
1427 char res29[4];
1428 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
1429 char res30[4];
1430 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
1431 char res31[12];
1432 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
1433 char res32[4];
1434 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
1435 char res33[4];
1436 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
1437 char res34[12];
1438 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
1439 char res35[4];
1440 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
1441 char res36[4];
1442 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
1443 char res37[76];
1444 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
1445 char res38[4];
1446 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
1447 char res39[4];
1448 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
1449 char res40[12];
1450 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
1451 char res41[4];
1452 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
1453 char res42[4];
1454 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
1455 char res43[12];
1456 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
1457 char res44[4];
1458 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
1459 char res45[4];
1460 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
1461 char res46[12];
1462 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
1463 char res47[4];
1464 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
1465 char res48[4];
1466 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
1467 char res49[12];
1468 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
1469 char res50[12];
1470 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
1471 char res51[12];
1472 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
1473 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
1474 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
1475 uint pecr; /* 0xd0e0c - Port Error Control Register */
1476 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
1477 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
1478 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
1479 char res52[4];
1480 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
1481 char res53[4];
1482 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
1483 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
1484 char res54[464];
1485 uint omr; /* 0xd1000 - Outbound Mode Register */
1486 uint osr; /* 0xd1004 - Outbound Status Register */
1487 uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
1488 uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
1489 uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */
1490 uint osar; /* 0xd1014 - Outbound Unit Source Address Register */
1491 uint odpr; /* 0xd1018 - Outbound Destination Port Register */
1492 uint odatr; /* 0xd101c - Outbound Destination Attributes Register */
1493 uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */
1494 uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
1495 uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
1496 char res55[52];
1497 uint imr; /* 0xd1060 - Outbound Mode Register */
1498 uint isr; /* 0xd1064 - Inbound Status Register */
1499 uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
1500 uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
1501 uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
1502 uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
1503 char res56[1000];
1504 uint dmr; /* 0xd1460 - Doorbell Mode Register */
1505 uint dsr; /* 0xd1464 - Doorbell Status Register */
1506 uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
1507 uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */
1508 uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
1509 uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */
1510 char res57[104];
1511 uint pwmr; /* 0xd14e0 - Port-Write Mode Register */
1512 uint pwsr; /* 0xd14e4 - Port-Write Status Register */
1513 uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */
1514 uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */
1515 char res58[60176];
1516} ccsr_rio_t;
1517
1518/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
1519typedef struct ccsr_gur {
1520 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
1521 uint porbmsr; /* 0xe0004 - POR boot mode status register */
1522 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
1523 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
1524 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
1525 char res1[12];
1526 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
1527 char res2[12];
1528 uint gpiocr; /* 0xe0030 - GPIO control register */
1529 char res3[12];
1530 uint gpoutdr; /* 0xe0040 - General-purpose output data register */
1531 char res4[12];
1532 uint gpindr; /* 0xe0050 - General-purpose input data register */
1533 char res5[12];
1534 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
1535 char res6[12];
1536 uint devdisr; /* 0xe0070 - Device disable control */
1537 char res7[12];
1538 uint powmgtcsr; /* 0xe0080 - Power management status and control register */
1539 char res8[12];
1540 uint mcpsumr; /* 0xe0090 - Machine check summary register */
1541 char res9[12];
1542 uint pvr; /* 0xe00a0 - Processor version register */
1543 uint svr; /* 0xe00a4 - System version register */
1544 char res10[3416];
1545 uint clkocr; /* 0xe0e00 - Clock out select register */
1546 char res11[12];
1547 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
1548 char res12[12];
1549 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
1550 char res13[61915];
1551} ccsr_gur_t;
1552
1553typedef struct immap {
1554 ccsr_local_ecm_t im_local_ecm;
1555 ccsr_ddr_t im_ddr;
1556 ccsr_i2c_t im_i2c;
1557 ccsr_duart_t im_duart;
1558 ccsr_lbc_t im_lbc;
1559 ccsr_pcix_t im_pcix;
1560 ccsr_l2cache_t im_l2cache;
1561 ccsr_dma_t im_dma;
1562 ccsr_tsec_t im_tsec1;
1563 ccsr_tsec_t im_tsec2;
1564 ccsr_pic_t im_pic;
1565 ccsr_cpm_t im_cpm;
1566 ccsr_rio_t im_rio;
1567 ccsr_gur_t im_gur;
1568} immap_t;
1569
1570extern immap_t *immr;
1571
1572#endif /*__IMMAP_85xx__*/
"Das U-Boot" Source Tree