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935ecca1 WD |
1 | #ifndef __ASM_PPC_PROCESSOR_H |
2 | #define __ASM_PPC_PROCESSOR_H | |
3 | ||
4 | /* | |
5 | * Default implementation of macro that returns current | |
6 | * instruction pointer ("program counter"). | |
7 | */ | |
8 | #define current_text_addr() ({ __label__ _l; _l: &&_l;}) | |
9 | ||
10 | #include <linux/config.h> | |
11 | ||
12 | #include <asm/ptrace.h> | |
13 | #include <asm/types.h> | |
14 | ||
15 | /* Machine State Register (MSR) Fields */ | |
16 | ||
17 | #ifdef CONFIG_PPC64BRIDGE | |
18 | #define MSR_SF (1<<63) | |
19 | #define MSR_ISF (1<<61) | |
20 | #endif /* CONFIG_PPC64BRIDGE */ | |
1aeed8d7 | 21 | #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ |
42d1f039 | 22 | #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ |
1aeed8d7 | 23 | #define MSR_SPE (1<<25) /* Enable SPE(e500) */ |
935ecca1 WD |
24 | #define MSR_POW (1<<18) /* Enable Power Management */ |
25 | #define MSR_WE (1<<18) /* Wait State Enable */ | |
26 | #define MSR_TGPR (1<<17) /* TLB Update registers in use */ | |
27 | #define MSR_CE (1<<17) /* Critical Interrupt Enable */ | |
28 | #define MSR_ILE (1<<16) /* Interrupt Little Endian */ | |
29 | #define MSR_EE (1<<15) /* External Interrupt Enable */ | |
30 | #define MSR_PR (1<<14) /* Problem State / Privilege Level */ | |
31 | #define MSR_FP (1<<13) /* Floating Point enable */ | |
32 | #define MSR_ME (1<<12) /* Machine Check Enable */ | |
33 | #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ | |
34 | #define MSR_SE (1<<10) /* Single Step */ | |
1aeed8d7 WD |
35 | #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ |
36 | #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ | |
935ecca1 | 37 | #define MSR_BE (1<<9) /* Branch Trace */ |
1636d1c8 | 38 | #define MSR_DE (1<<9) /* Debug Exception Enable */ |
935ecca1 WD |
39 | #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ |
40 | #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ | |
1636d1c8 | 41 | #define MSR_IR (1<<5) /* Instruction Relocate */ |
1aeed8d7 | 42 | #define MSR_IS (1<<5) /* Book E Instruction space */ |
1636d1c8 | 43 | #define MSR_DR (1<<4) /* Data Relocate */ |
1aeed8d7 | 44 | #define MSR_DS (1<<4) /* Book E Data space */ |
935ecca1 WD |
45 | #define MSR_PE (1<<3) /* Protection Enable */ |
46 | #define MSR_PX (1<<2) /* Protection Exclusive Mode */ | |
1aeed8d7 | 47 | #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ |
935ecca1 | 48 | #define MSR_RI (1<<1) /* Recoverable Exception */ |
1636d1c8 | 49 | #define MSR_LE (1<<0) /* Little Endian */ |
935ecca1 WD |
50 | |
51 | #ifdef CONFIG_APUS_FAST_EXCEPT | |
52 | #define MSR_ MSR_ME|MSR_IP|MSR_RI | |
53 | #else | |
54 | #define MSR_ MSR_ME|MSR_RI | |
55 | #endif | |
42d1f039 | 56 | #ifndef CONFIG_E500 |
1aeed8d7 | 57 | #define MSR_KERNEL MSR_|MSR_IR|MSR_DR |
42d1f039 WD |
58 | #else |
59 | #define MSR_KERNEL MSR_ME | |
60 | #endif | |
935ecca1 WD |
61 | |
62 | /* Floating Point Status and Control Register (FPSCR) Fields */ | |
63 | ||
64 | #define FPSCR_FX 0x80000000 /* FPU exception summary */ | |
65 | #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ | |
66 | #define FPSCR_VX 0x20000000 /* Invalid operation summary */ | |
67 | #define FPSCR_OX 0x10000000 /* Overflow exception summary */ | |
68 | #define FPSCR_UX 0x08000000 /* Underflow exception summary */ | |
69 | #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ | |
70 | #define FPSCR_XX 0x02000000 /* Inexact exception summary */ | |
71 | #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ | |
72 | #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ | |
73 | #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ | |
74 | #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ | |
75 | #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ | |
76 | #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ | |
77 | #define FPSCR_FR 0x00040000 /* Fraction rounded */ | |
78 | #define FPSCR_FI 0x00020000 /* Fraction inexact */ | |
79 | #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ | |
80 | #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ | |
81 | #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ | |
82 | #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ | |
83 | #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ | |
84 | #define FPSCR_VE 0x00000080 /* Invalid op exception enable */ | |
85 | #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ | |
86 | #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ | |
87 | #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ | |
88 | #define FPSCR_XE 0x00000008 /* FP inexact exception enable */ | |
89 | #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ | |
90 | #define FPSCR_RN 0x00000003 /* FPU rounding control */ | |
91 | ||
92 | /* Special Purpose Registers (SPRNs)*/ | |
93 | ||
f6ba9b56 EB |
94 | /* PPC440 Architecture is BOOK-E */ |
95 | #ifdef CONFIG_440 | |
96 | #define CONFIG_BOOKE | |
97 | #endif | |
98 | ||
58ea142f MF |
99 | #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ |
100 | #ifdef CONFIG_BOOKE | |
101 | #define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ | |
102 | #endif | |
3c74e32a WD |
103 | #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ |
104 | #define SPRN_CTR 0x009 /* Count Register */ | |
105 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ | |
42d1f039 | 106 | #ifndef CONFIG_BOOKE |
3c74e32a WD |
107 | #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ |
108 | #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ | |
42d1f039 | 109 | #else |
1aeed8d7 WD |
110 | #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ |
111 | #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ | |
112 | #endif /* CONFIG_BOOKE */ | |
3c74e32a WD |
113 | #define SPRN_DAR 0x013 /* Data Address Register */ |
114 | #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ | |
115 | #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ | |
116 | #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ | |
117 | #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ | |
118 | #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ | |
119 | #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ | |
120 | #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ | |
121 | #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ | |
1aeed8d7 WD |
122 | #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ |
123 | #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ | |
124 | #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ | |
125 | #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ | |
126 | #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ | |
127 | #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ | |
128 | #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ | |
129 | #define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ | |
3c74e32a WD |
130 | #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ |
131 | #define DBCR_EDM 0x80000000 | |
132 | #define DBCR_IDM 0x40000000 | |
133 | #define DBCR_RST(x) (((x) & 0x3) << 28) | |
1636d1c8 WD |
134 | #define DBCR_RST_NONE 0 |
135 | #define DBCR_RST_CORE 1 | |
136 | #define DBCR_RST_CHIP 2 | |
3c74e32a WD |
137 | #define DBCR_RST_SYSTEM 3 |
138 | #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ | |
139 | #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ | |
140 | #define DBCR_EDE 0x02000000 /* Exception Debug Event */ | |
141 | #define DBCR_TDE 0x01000000 /* TRAP Debug Event */ | |
142 | #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ | |
143 | #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ | |
144 | #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ | |
145 | #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ | |
146 | #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ | |
147 | #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ | |
148 | #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ | |
149 | #define DAC_BYTE 0 | |
150 | #define DAC_HALF 1 | |
151 | #define DAC_WORD 2 | |
152 | #define DAC_QUAD 3 | |
153 | #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ | |
154 | #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ | |
155 | #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ | |
156 | #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ | |
157 | #define DBCR_SED 0x00000020 /* Second Exception Debug Event */ | |
158 | #define DBCR_STD 0x00000010 /* Second Trap Debug Event */ | |
159 | #define DBCR_SIA 0x00000008 /* Second IAC Enable */ | |
160 | #define DBCR_SDA 0x00000004 /* Second DAC Enable */ | |
161 | #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ | |
162 | #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ | |
42d1f039 | 163 | #ifndef CONFIG_BOOKE |
1aeed8d7 | 164 | #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ |
42d1f039 | 165 | #else |
1aeed8d7 | 166 | #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ |
42d1f039 WD |
167 | #endif /* CONFIG_BOOKE */ |
168 | #ifndef CONFIG_BOOKE | |
3c74e32a WD |
169 | #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ |
170 | #define SPRN_DBSR 0x3F0 /* Debug Status Register */ | |
42d1f039 | 171 | #else |
1aeed8d7 | 172 | #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ |
58ea142f MF |
173 | #ifdef CONFIG_BOOKE |
174 | #define SPRN_DBDR 0x3f3 /* Debug Data Register */ | |
175 | #endif | |
1aeed8d7 WD |
176 | #define SPRN_DBSR 0x130 /* Book E Debug Status Register */ |
177 | #define DBSR_IC 0x08000000 /* Book E Instruction Completion */ | |
178 | #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ | |
42d1f039 | 179 | #endif /* CONFIG_BOOKE */ |
3c74e32a WD |
180 | #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ |
181 | #define DCCR_NOCACHE 0 /* Noncacheable */ | |
182 | #define DCCR_CACHE 1 /* Cacheable */ | |
58ea142f MF |
183 | #ifndef CONFIG_BOOKE |
184 | #define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ | |
185 | #define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ | |
186 | #endif | |
3c74e32a WD |
187 | #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ |
188 | #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ | |
189 | #define DCWR_COPY 0 /* Copy-back */ | |
190 | #define DCWR_WRITE 1 /* Write-through */ | |
42d1f039 | 191 | #ifndef CONFIG_BOOKE |
3c74e32a | 192 | #define SPRN_DEAR 0x3D5 /* Data Error Address Register */ |
42d1f039 | 193 | #else |
1aeed8d7 | 194 | #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ |
42d1f039 | 195 | #endif /* CONFIG_BOOKE */ |
3c74e32a WD |
196 | #define SPRN_DEC 0x016 /* Decrement Register */ |
197 | #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ | |
58ea142f MF |
198 | #ifdef CONFIG_BOOKE |
199 | #define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ | |
200 | #define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ | |
201 | #define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ | |
202 | #define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ | |
203 | #endif | |
3c74e32a | 204 | #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ |
58ea142f MF |
205 | #ifdef CONFIG_BOOKE |
206 | #define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ | |
207 | #define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ | |
208 | #define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ | |
209 | #define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ | |
210 | #define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ | |
211 | #endif | |
3c74e32a | 212 | #define SPRN_EAR 0x11A /* External Address Register */ |
42d1f039 | 213 | #ifndef CONFIG_BOOKE |
3c74e32a | 214 | #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ |
42d1f039 | 215 | #else |
1aeed8d7 | 216 | #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ |
42d1f039 | 217 | #endif /* CONFIG_BOOKE */ |
3c74e32a WD |
218 | #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ |
219 | #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ | |
220 | #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ | |
221 | #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ | |
222 | #define ESR_PIL 0x08000000 /* Program Exception - Illegal */ | |
223 | #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ | |
224 | #define ESR_PTR 0x02000000 /* Program Exception - Trap */ | |
225 | #define ESR_DST 0x00800000 /* Storage Exception - Data miss */ | |
226 | #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ | |
227 | #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ | |
228 | #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ | |
229 | #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ | |
230 | #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ | |
f046ccd1 EL |
231 | |
232 | #define HID0_ICE_SHIFT 15 | |
233 | #define HID0_DCE_SHIFT 14 | |
234 | #define HID0_DLOCK_SHIFT 12 | |
235 | ||
3c74e32a WD |
236 | #define HID0_EMCP (1<<31) /* Enable Machine Check pin */ |
237 | #define HID0_EBA (1<<29) /* Enable Bus Address Parity */ | |
238 | #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ | |
239 | #define HID0_SBCLK (1<<27) | |
240 | #define HID0_EICE (1<<26) | |
241 | #define HID0_ECLK (1<<25) | |
242 | #define HID0_PAR (1<<24) | |
243 | #define HID0_DOZE (1<<23) | |
244 | #define HID0_NAP (1<<22) | |
245 | #define HID0_SLEEP (1<<21) | |
246 | #define HID0_DPM (1<<20) | |
f046ccd1 EL |
247 | #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ |
248 | #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ | |
61a21e98 | 249 | #define HID0_TBEN (1<<14) /* Time Base Enable */ |
3c74e32a | 250 | #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ |
f046ccd1 | 251 | #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ |
3c74e32a WD |
252 | #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ |
253 | #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ | |
254 | #define HID0_DCI HID0_DCFI | |
935ecca1 | 255 | #define HID0_SPD (1<<9) /* Speculative disable */ |
61a21e98 | 256 | #define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */ |
935ecca1 | 257 | #define HID0_SGE (1<<7) /* Store Gathering Enable */ |
3c74e32a | 258 | #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ |
935ecca1 WD |
259 | #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ |
260 | #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ | |
261 | #define HID0_ABE (1<<3) /* Address Broadcast Enable */ | |
3c74e32a WD |
262 | #define HID0_BHTE (1<<2) /* Branch History Table Enable */ |
263 | #define HID0_BTCD (1<<1) /* Branch target cache disable */ | |
264 | #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ | |
81f481ca AF |
265 | #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ |
266 | #define HID1_ASTME (1<<13) /* Address bus streaming mode */ | |
267 | #define HID1_ABE (1<<12) /* Address broadcast enable */ | |
3c74e32a | 268 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ |
42d1f039 | 269 | #ifndef CONFIG_BOOKE |
3c74e32a WD |
270 | #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ |
271 | #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ | |
42d1f039 | 272 | #else |
1aeed8d7 WD |
273 | #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ |
274 | #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ | |
42d1f039 | 275 | #endif /* CONFIG_BOOKE */ |
3c74e32a WD |
276 | #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ |
277 | #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ | |
278 | #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ | |
279 | #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ | |
280 | #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ | |
281 | #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ | |
282 | #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ | |
283 | #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ | |
1aeed8d7 WD |
284 | #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ |
285 | #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ | |
286 | #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ | |
287 | #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ | |
288 | #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ | |
289 | #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ | |
290 | #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ | |
291 | #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ | |
3c74e32a WD |
292 | #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ |
293 | #define ICCR_NOCACHE 0 /* Noncacheable */ | |
294 | #define ICCR_CACHE 1 /* Cacheable */ | |
295 | #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ | |
58ea142f MF |
296 | #ifdef CONFIG_BOOKE |
297 | #define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */ | |
298 | #define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */ | |
299 | #endif | |
3c74e32a WD |
300 | #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ |
301 | #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ | |
302 | #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ | |
1636d1c8 | 303 | #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ |
58ea142f MF |
304 | #ifdef CONFIG_BOOKE |
305 | #define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */ | |
306 | #define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */ | |
307 | #define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */ | |
308 | #define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */ | |
309 | #define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */ | |
310 | #define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */ | |
311 | #define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */ | |
312 | #define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */ | |
313 | #define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */ | |
314 | #endif | |
1aeed8d7 | 315 | #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ |
3c74e32a WD |
316 | #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ |
317 | #define SPRN_LR 0x008 /* Link Register */ | |
1aeed8d7 | 318 | #define SPRN_MBAR 0x137 /* System memory base address */ |
3c74e32a WD |
319 | #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ |
320 | #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ | |
58ea142f MF |
321 | #ifdef CONFIG_BOOKE |
322 | #define SPRN_MMUCR 0x3b2 /* MMU Control Register */ | |
323 | #endif | |
3c74e32a WD |
324 | #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ |
325 | #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ | |
326 | #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ | |
327 | #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ | |
42d1f039 | 328 | #ifndef CONFIG_BOOKE |
3c74e32a WD |
329 | #define SPRN_PID 0x3B1 /* Process ID */ |
330 | #define SPRN_PIR 0x3FF /* Processor Identification Register */ | |
42d1f039 | 331 | #else |
1aeed8d7 WD |
332 | #define SPRN_PID 0x030 /* Book E Process ID */ |
333 | #define SPRN_PIR 0x11E /* Book E Processor Identification Register */ | |
42d1f039 | 334 | #endif /* CONFIG_BOOKE */ |
3c74e32a WD |
335 | #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ |
336 | #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ | |
337 | #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ | |
338 | #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ | |
339 | #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ | |
340 | #define SPRN_PVR 0x11F /* Processor Version Register */ | |
341 | #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ | |
58ea142f MF |
342 | #ifdef CONFIG_BOOKE |
343 | #define SPRN_RSTCFG 0x39b /* Reset Configuration */ | |
344 | #endif | |
3c74e32a WD |
345 | #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ |
346 | #define SPRN_SDR1 0x019 /* MMU Hash Base Register */ | |
347 | #define SPRN_SGR 0x3B9 /* Storage Guarded Register */ | |
348 | #define SGR_NORMAL 0 | |
349 | #define SGR_GUARDED 1 | |
350 | #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ | |
351 | #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ | |
352 | #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ | |
353 | #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ | |
354 | #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ | |
e01bd218 SR |
355 | #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ |
356 | #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ | |
357 | #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ | |
358 | #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ | |
3c74e32a WD |
359 | #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ |
360 | #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ | |
361 | #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ | |
efa35cf1 | 362 | #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ |
58ea142f | 363 | |
0ac6f8b7 WD |
364 | #ifdef CONFIG_BOOKE |
365 | #define SPRN_SVR 0x3FF /* System Version Register */ | |
366 | #else | |
367 | #define SPRN_SVR 0x11E /* System Version Register */ | |
368 | #endif | |
3c74e32a WD |
369 | #define SPRN_TBHI 0x3DC /* Time Base High */ |
370 | #define SPRN_TBHU 0x3CC /* Time Base High User-mode */ | |
371 | #define SPRN_TBLO 0x3DD /* Time Base Low */ | |
372 | #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ | |
182e1069 SR |
373 | #define SPRN_TBRL 0x10C /* Time Base Read Lower Register */ |
374 | #define SPRN_TBRU 0x10D /* Time Base Read Upper Register */ | |
375 | #define SPRN_TBWL 0x11C /* Time Base Write Lower Register */ | |
376 | #define SPRN_TBWU 0x11D /* Time Base Write Upper Register */ | |
42d1f039 | 377 | #ifndef CONFIG_BOOKE |
3c74e32a | 378 | #define SPRN_TCR 0x3DA /* Timer Control Register */ |
42d1f039 | 379 | #else |
1aeed8d7 | 380 | #define SPRN_TCR 0x154 /* Book E Timer Control Register */ |
42d1f039 | 381 | #endif /* CONFIG_BOOKE */ |
3c74e32a WD |
382 | #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ |
383 | #define WP_2_17 0 /* 2^17 clocks */ | |
384 | #define WP_2_21 1 /* 2^21 clocks */ | |
385 | #define WP_2_25 2 /* 2^25 clocks */ | |
386 | #define WP_2_29 3 /* 2^29 clocks */ | |
387 | #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ | |
388 | #define WRC_NONE 0 /* No reset will occur */ | |
389 | #define WRC_CORE 1 /* Core reset will occur */ | |
390 | #define WRC_CHIP 2 /* Chip reset will occur */ | |
391 | #define WRC_SYSTEM 3 /* System reset will occur */ | |
392 | #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ | |
393 | #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ | |
394 | #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ | |
395 | #define FP_2_9 0 /* 2^9 clocks */ | |
396 | #define FP_2_13 1 /* 2^13 clocks */ | |
397 | #define FP_2_17 2 /* 2^17 clocks */ | |
398 | #define FP_2_21 3 /* 2^21 clocks */ | |
399 | #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ | |
400 | #define TCR_ARE 0x00400000 /* Auto Reload Enable */ | |
401 | #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ | |
402 | #define THRM1_TIN (1<<0) | |
403 | #define THRM1_TIV (1<<1) | |
404 | #define THRM1_THRES (0x7f<<2) | |
405 | #define THRM1_TID (1<<29) | |
406 | #define THRM1_TIE (1<<30) | |
407 | #define THRM1_V (1<<31) | |
408 | #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ | |
409 | #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ | |
410 | #define THRM3_E (1<<31) | |
1aeed8d7 | 411 | #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ |
42d1f039 | 412 | #ifndef CONFIG_BOOKE |
3c74e32a | 413 | #define SPRN_TSR 0x3D8 /* Timer Status Register */ |
42d1f039 | 414 | #else |
1aeed8d7 | 415 | #define SPRN_TSR 0x150 /* Book E Timer Status Register */ |
42d1f039 | 416 | #endif /* CONFIG_BOOKE */ |
3c74e32a WD |
417 | #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ |
418 | #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ | |
419 | #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ | |
420 | #define WRS_NONE 0 /* No WDT reset occurred */ | |
421 | #define WRS_CORE 1 /* WDT forced core reset */ | |
422 | #define WRS_CHIP 2 /* WDT forced chip reset */ | |
423 | #define WRS_SYSTEM 3 /* WDT forced system reset */ | |
424 | #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ | |
425 | #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ | |
426 | #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ | |
427 | #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ | |
428 | #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ | |
429 | #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ | |
430 | #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ | |
431 | #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ | |
432 | #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ | |
433 | #define SPRN_XER 0x001 /* Fixed Point Exception Register */ | |
434 | #define SPRN_ZPR 0x3B0 /* Zone Protection Register */ | |
935ecca1 | 435 | |
42d1f039 WD |
436 | /* Book E definitions */ |
437 | #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ | |
438 | #define SPRN_CSRR0 0x03A /* Critical SRR0 */ | |
439 | #define SPRN_CSRR1 0x03B /* Critical SRR0 */ | |
3c74e32a | 440 | #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ |
42d1f039 | 441 | #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ |
3c74e32a WD |
442 | #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ |
443 | #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ | |
444 | #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ | |
445 | #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ | |
446 | #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ | |
447 | #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ | |
448 | #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ | |
449 | #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ | |
42d1f039 | 450 | #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ |
3c74e32a WD |
451 | #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ |
452 | #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ | |
42d1f039 WD |
453 | #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ |
454 | #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ | |
455 | #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ | |
456 | #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ | |
457 | #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ | |
458 | #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ | |
459 | #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ | |
460 | #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ | |
461 | #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ | |
462 | #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ | |
463 | #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ | |
464 | #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ | |
465 | #define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ | |
466 | #define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ | |
467 | #define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ | |
468 | #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ | |
469 | #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ | |
470 | #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ | |
26f4cdba KG |
471 | #define SPRN_IVOR38 0x1b0 /* Interrupt Vector Offset Register 38 */ |
472 | #define SPRN_IVOR39 0x1b1 /* Interrupt Vector Offset Register 39 */ | |
473 | #define SPRN_IVOR40 0x1b2 /* Interrupt Vector Offset Register 40 */ | |
474 | #define SPRN_IVOR41 0x1b3 /* Interrupt Vector Offset Register 41 */ | |
475 | #define SPRN_GIVOR2 0x1b8 /* Guest Interrupt Vector Offset Register 2 */ | |
476 | #define SPRN_GIVOR3 0x1b9 /* Guest Interrupt Vector Offset Register 3 */ | |
477 | #define SPRN_GIVOR4 0x1ba /* Guest Interrupt Vector Offset Register 4 */ | |
478 | #define SPRN_GIVOR8 0x1bb /* Guest Interrupt Vector Offset Register 8 */ | |
479 | #define SPRN_GIVOR13 0x1bc /* Guest Interrupt Vector Offset Register 13 */ | |
480 | #define SPRN_GIVOR14 0x1bd /* Guest Interrupt Vector Offset Register 14 */ | |
42d1f039 WD |
481 | |
482 | /* e500 definitions */ | |
1aeed8d7 WD |
483 | #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ |
484 | #define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ | |
7f9f4347 | 485 | #define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ |
1aeed8d7 WD |
486 | #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ |
487 | #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ | |
33f57bd5 | 488 | #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */ |
1aeed8d7 WD |
489 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ |
490 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ | |
491 | #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ | |
492 | #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ | |
33f57bd5 | 493 | #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ |
1aeed8d7 WD |
494 | #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ |
495 | #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ | |
7f9f4347 KG |
496 | #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ |
497 | #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ | |
498 | #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ | |
499 | #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ | |
500 | #define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ | |
501 | #define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ | |
502 | #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ | |
503 | #define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ | |
504 | #define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ | |
505 | #define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ | |
506 | #define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ | |
507 | #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ | |
508 | #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ | |
509 | #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ | |
510 | #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ | |
42d1f039 | 511 | |
f8523cb0 KG |
512 | #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ |
513 | #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ | |
3c74e32a | 514 | #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ |
1aeed8d7 WD |
515 | #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ |
516 | #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ | |
517 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ | |
518 | #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ | |
519 | #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ | |
520 | #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ | |
521 | #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ | |
d9b94f28 | 522 | #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ |
dcc87dd5 | 523 | #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */ |
42d1f039 | 524 | |
1aeed8d7 WD |
525 | #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ |
526 | #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ | |
527 | #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ | |
528 | #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ | |
26f4cdba KG |
529 | #define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ |
530 | #define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ | |
1aeed8d7 | 531 | #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ |
42d1f039 | 532 | |
1aeed8d7 WD |
533 | #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ |
534 | #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ | |
42d1f039 | 535 | #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ |
1aeed8d7 WD |
536 | #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ |
537 | #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ | |
538 | #define SPRN_PID1 0x279 /* Process ID Register 1 */ | |
539 | #define SPRN_PID2 0x27a /* Process ID Register 2 */ | |
42d1f039 | 540 | #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ |
61a21e98 | 541 | #define SPRN_MCAR 0x23d /* Machine Check Address register */ |
efa35cf1 GB |
542 | #define MCSR_MCS 0x80000000 /* Machine Check Summary */ |
543 | #define MCSR_IB 0x40000000 /* Instruction PLB Error */ | |
c821b5f1 | 544 | #if defined(CONFIG_440) |
efa35cf1 GB |
545 | #define MCSR_DRB 0x20000000 /* Data Read PLB Error */ |
546 | #define MCSR_DWB 0x10000000 /* Data Write PLB Error */ | |
c821b5f1 GE |
547 | #else |
548 | #define MCSR_DB 0x20000000 /* Data PLB Error */ | |
549 | #endif /* defined(CONFIG_440) */ | |
efa35cf1 GB |
550 | #define MCSR_TLBP 0x08000000 /* TLB Parity Error */ |
551 | #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ | |
552 | #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ | |
553 | #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ | |
554 | #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ | |
1aeed8d7 | 555 | #define ESR_ST 0x00800000 /* Store Operation */ |
42d1f039 | 556 | |
debb7354 | 557 | #if defined(CONFIG_MPC86xx) |
cfc7a7f5 JL |
558 | #define SPRN_MSSCR0 0x3f6 |
559 | #define SPRN_MSSSR0 0x3f7 | |
debb7354 JL |
560 | #endif |
561 | ||
935ecca1 WD |
562 | /* Short-hand versions for a number of the above SPRNs */ |
563 | ||
3c74e32a WD |
564 | #define CTR SPRN_CTR /* Counter Register */ |
565 | #define DAR SPRN_DAR /* Data Address Register */ | |
566 | #define DABR SPRN_DABR /* Data Address Breakpoint Register */ | |
567 | #define DAC1 SPRN_DAC1 /* Data Address Register 1 */ | |
568 | #define DAC2 SPRN_DAC2 /* Data Address Register 2 */ | |
569 | #define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ | |
570 | #define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ | |
571 | #define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ | |
572 | #define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ | |
573 | #define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ | |
574 | #define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ | |
575 | #define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ | |
576 | #define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ | |
1aeed8d7 WD |
577 | #define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ |
578 | #define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ | |
579 | #define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ | |
580 | #define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ | |
581 | #define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ | |
582 | #define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ | |
583 | #define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ | |
584 | #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ | |
3c74e32a WD |
585 | #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ |
586 | #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ | |
587 | #define DBSR SPRN_DBSR /* Debug Status Register */ | |
1636d1c8 WD |
588 | #define DCMP SPRN_DCMP /* Data TLB Compare Register */ |
589 | #define DEC SPRN_DEC /* Decrement Register */ | |
590 | #define DMISS SPRN_DMISS /* Data TLB Miss Register */ | |
3c74e32a | 591 | #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ |
1636d1c8 | 592 | #define EAR SPRN_EAR /* External Address Register */ |
3c74e32a WD |
593 | #define ESR SPRN_ESR /* Exception Syndrome Register */ |
594 | #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ | |
595 | #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ | |
596 | #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ | |
597 | #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ | |
1636d1c8 | 598 | #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ |
3c74e32a WD |
599 | #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ |
600 | #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ | |
601 | #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ | |
602 | #define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ | |
603 | #define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ | |
604 | #define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ | |
605 | #define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ | |
606 | #define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ | |
607 | #define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ | |
608 | #define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ | |
609 | #define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ | |
610 | #define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ | |
611 | #define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ | |
612 | #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ | |
613 | #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ | |
614 | #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ | |
1636d1c8 | 615 | #define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ |
3c74e32a WD |
616 | #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ |
617 | #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ | |
618 | #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ | |
1636d1c8 | 619 | #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ |
1aeed8d7 | 620 | #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ |
1636d1c8 | 621 | #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ |
3c74e32a | 622 | #define LR SPRN_LR |
1aeed8d7 | 623 | #define MBAR SPRN_MBAR /* System memory base address */ |
debb7354 | 624 | #if defined(CONFIG_MPC86xx) |
2e4d94f1 | 625 | #define MSSCR0 SPRN_MSSCR0 |
debb7354 JL |
626 | #endif |
627 | #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) | |
42d1f039 WD |
628 | #define PIR SPRN_PIR |
629 | #endif | |
36c72877 | 630 | #define SVR SPRN_SVR /* System-On-Chip Version Register */ |
3c74e32a WD |
631 | #define PVR SPRN_PVR /* Processor Version */ |
632 | #define RPA SPRN_RPA /* Required Physical Address Register */ | |
1636d1c8 | 633 | #define SDR1 SPRN_SDR1 /* MMU hash base register */ |
3c74e32a WD |
634 | #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ |
635 | #define SPR1 SPRN_SPRG1 | |
636 | #define SPR2 SPRN_SPRG2 | |
637 | #define SPR3 SPRN_SPRG3 | |
1aeed8d7 WD |
638 | #define SPRG0 SPRN_SPRG0 |
639 | #define SPRG1 SPRN_SPRG1 | |
640 | #define SPRG2 SPRN_SPRG2 | |
641 | #define SPRG3 SPRN_SPRG3 | |
642 | #define SPRG4 SPRN_SPRG4 | |
643 | #define SPRG5 SPRN_SPRG5 | |
644 | #define SPRG6 SPRN_SPRG6 | |
645 | #define SPRG7 SPRN_SPRG7 | |
3c74e32a WD |
646 | #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ |
647 | #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ | |
efa35cf1 GB |
648 | #define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */ |
649 | #define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */ | |
0ac6f8b7 | 650 | #define SVR SPRN_SVR /* System Version Register */ |
3c74e32a WD |
651 | #define TBRL SPRN_TBRL /* Time Base Read Lower Register */ |
652 | #define TBRU SPRN_TBRU /* Time Base Read Upper Register */ | |
653 | #define TBWL SPRN_TBWL /* Time Base Write Lower Register */ | |
654 | #define TBWU SPRN_TBWU /* Time Base Write Upper Register */ | |
655 | #define TCR SPRN_TCR /* Timer Control Register */ | |
656 | #define TSR SPRN_TSR /* Timer Status Register */ | |
935ecca1 | 657 | #define ICTC 1019 |
3c74e32a WD |
658 | #define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ |
659 | #define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ | |
660 | #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ | |
661 | #define XER SPRN_XER | |
935ecca1 | 662 | |
3c74e32a WD |
663 | #define DECAR SPRN_DECAR |
664 | #define CSRR0 SPRN_CSRR0 | |
665 | #define CSRR1 SPRN_CSRR1 | |
666 | #define IVPR SPRN_IVPR | |
ae624168 | 667 | #define USPRG0 SPRN_USPRG |
3c74e32a WD |
668 | #define SPRG4R SPRN_SPRG4R |
669 | #define SPRG5R SPRN_SPRG5R | |
670 | #define SPRG6R SPRN_SPRG6R | |
671 | #define SPRG7R SPRN_SPRG7R | |
672 | #define SPRG4W SPRN_SPRG4W | |
673 | #define SPRG5W SPRN_SPRG5W | |
674 | #define SPRG6W SPRN_SPRG6W | |
675 | #define SPRG7W SPRN_SPRG7W | |
42d1f039 | 676 | #define DEAR SPRN_DEAR |
3c74e32a WD |
677 | #define DBCR2 SPRN_DBCR2 |
678 | #define IAC3 SPRN_IAC3 | |
679 | #define IAC4 SPRN_IAC4 | |
680 | #define DVC1 SPRN_DVC1 | |
681 | #define DVC2 SPRN_DVC2 | |
682 | #define IVOR0 SPRN_IVOR0 | |
683 | #define IVOR1 SPRN_IVOR1 | |
684 | #define IVOR2 SPRN_IVOR2 | |
685 | #define IVOR3 SPRN_IVOR3 | |
686 | #define IVOR4 SPRN_IVOR4 | |
687 | #define IVOR5 SPRN_IVOR5 | |
688 | #define IVOR6 SPRN_IVOR6 | |
689 | #define IVOR7 SPRN_IVOR7 | |
690 | #define IVOR8 SPRN_IVOR8 | |
691 | #define IVOR9 SPRN_IVOR9 | |
692 | #define IVOR10 SPRN_IVOR10 | |
693 | #define IVOR11 SPRN_IVOR11 | |
694 | #define IVOR12 SPRN_IVOR12 | |
695 | #define IVOR13 SPRN_IVOR13 | |
696 | #define IVOR14 SPRN_IVOR14 | |
697 | #define IVOR15 SPRN_IVOR15 | |
42d1f039 WD |
698 | #define IVOR32 SPRN_IVOR32 |
699 | #define IVOR33 SPRN_IVOR33 | |
700 | #define IVOR34 SPRN_IVOR34 | |
701 | #define IVOR35 SPRN_IVOR35 | |
702 | #define MCSRR0 SPRN_MCSRR0 | |
703 | #define MCSRR1 SPRN_MCSRR1 | |
1636d1c8 | 704 | #define L1CSR0 SPRN_L1CSR0 |
42d1f039 | 705 | #define L1CSR1 SPRN_L1CSR1 |
7f9f4347 | 706 | #define L1CSR2 SPRN_L1CSR2 |
b009f3ec KG |
707 | #define L1CFG0 SPRN_L1CFG0 |
708 | #define L1CFG1 SPRN_L1CFG1 | |
7f9f4347 KG |
709 | #define L2CFG0 SPRN_L2CFG0 |
710 | #define L2CSR0 SPRN_L2CSR0 | |
711 | #define L2CSR1 SPRN_L2CSR1 | |
42d1f039 WD |
712 | #define MCSR SPRN_MCSR |
713 | #define MMUCSR0 SPRN_MMUCSR0 | |
714 | #define BUCSR SPRN_BUCSR | |
715 | #define PID0 SPRN_PID | |
716 | #define PID1 SPRN_PID1 | |
717 | #define PID2 SPRN_PID2 | |
718 | #define MAS0 SPRN_MAS0 | |
1636d1c8 | 719 | #define MAS1 SPRN_MAS1 |
42d1f039 WD |
720 | #define MAS2 SPRN_MAS2 |
721 | #define MAS3 SPRN_MAS3 | |
722 | #define MAS4 SPRN_MAS4 | |
723 | #define MAS5 SPRN_MAS5 | |
724 | #define MAS6 SPRN_MAS6 | |
d9b94f28 | 725 | #define MAS7 SPRN_MAS7 |
dcc87dd5 | 726 | #define MAS8 SPRN_MAS8 |
935ecca1 | 727 | |
cc3023b9 RJ |
728 | #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) |
729 | #define DAR_DEAR DEAR | |
730 | #else | |
731 | #define DAR_DEAR DAR | |
732 | #endif | |
733 | ||
935ecca1 WD |
734 | /* Device Control Registers */ |
735 | ||
3c74e32a WD |
736 | #define DCRN_BEAR 0x090 /* Bus Error Address Register */ |
737 | #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ | |
1636d1c8 | 738 | #define BESR_DSES 0x80000000 /* Data-Side Error Status */ |
3c74e32a WD |
739 | #define BESR_DMES 0x40000000 /* DMA Error Status */ |
740 | #define BESR_RWS 0x20000000 /* Read/Write Status */ | |
741 | #define BESR_ETMASK 0x1C000000 /* Error Type */ | |
742 | #define ET_PROT 0 | |
743 | #define ET_PARITY 1 | |
744 | #define ET_NCFG 2 | |
745 | #define ET_BUSERR 4 | |
746 | #define ET_BUSTO 6 | |
747 | #define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ | |
748 | #define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ | |
749 | #define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ | |
1aeed8d7 WD |
750 | #define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ |
751 | #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ | |
752 | #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ | |
753 | #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ | |
754 | #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ | |
755 | #define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ | |
756 | #define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ | |
757 | #define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ | |
758 | #define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ | |
759 | #define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ | |
760 | #define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ | |
761 | #define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ | |
762 | #define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ | |
763 | #define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ | |
764 | #define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ | |
765 | #define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ | |
766 | #define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ | |
767 | #define DCRN_DMASR 0x0E0 /* DMA Status Register */ | |
768 | #define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ | |
3c74e32a WD |
769 | #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ |
770 | #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ | |
771 | #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ | |
772 | #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ | |
773 | #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ | |
774 | #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ | |
775 | #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ | |
776 | #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ | |
777 | #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ | |
778 | #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ | |
779 | #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ | |
780 | #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ | |
781 | #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ | |
782 | #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ | |
1aeed8d7 WD |
783 | #define DCRN_EXISR 0x040 /* External Interrupt Status Register */ |
784 | #define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ | |
3c74e32a WD |
785 | #define IOCR_E0TE 0x80000000 |
786 | #define IOCR_E0LP 0x40000000 | |
787 | #define IOCR_E1TE 0x20000000 | |
788 | #define IOCR_E1LP 0x10000000 | |
789 | #define IOCR_E2TE 0x08000000 | |
790 | #define IOCR_E2LP 0x04000000 | |
791 | #define IOCR_E3TE 0x02000000 | |
792 | #define IOCR_E3LP 0x01000000 | |
793 | #define IOCR_E4TE 0x00800000 | |
794 | #define IOCR_E4LP 0x00400000 | |
1636d1c8 WD |
795 | #define IOCR_EDT 0x00080000 |
796 | #define IOCR_SOR 0x00040000 | |
3c74e32a WD |
797 | #define IOCR_EDO 0x00008000 |
798 | #define IOCR_2XC 0x00004000 | |
799 | #define IOCR_ATC 0x00002000 | |
800 | #define IOCR_SPD 0x00001000 | |
801 | #define IOCR_BEM 0x00000800 | |
802 | #define IOCR_PTD 0x00000400 | |
803 | #define IOCR_ARE 0x00000080 | |
804 | #define IOCR_DRC 0x00000020 | |
805 | #define IOCR_RDM(x) (((x) & 0x3) << 3) | |
806 | #define IOCR_TCS 0x00000004 | |
807 | #define IOCR_SCS 0x00000002 | |
808 | #define IOCR_SPC 0x00000001 | |
935ecca1 | 809 | |
36c72877 WD |
810 | /* System-On-Chip Version Register */ |
811 | ||
812 | /* System-On-Chip Version Register (SVR) field extraction */ | |
813 | ||
814 | #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ | |
815 | #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ | |
816 | ||
1aeed8d7 WD |
817 | #define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ |
818 | #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ | |
819 | #define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ | |
820 | #define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ | |
821 | #define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ | |
822 | #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ | |
823 | #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ | |
935ecca1 WD |
824 | |
825 | /* Processor Version Register */ | |
826 | ||
827 | /* Processor Version Register (PVR) field extraction */ | |
828 | ||
3c74e32a WD |
829 | #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ |
830 | #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ | |
935ecca1 WD |
831 | |
832 | /* | |
0c8721a4 | 833 | * AMCC has further subdivided the standard PowerPC 16-bit version and |
935ecca1 WD |
834 | * revision subfields of the PVR for the PowerPC 403s into the following: |
835 | */ | |
836 | ||
3c74e32a WD |
837 | #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ |
838 | #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ | |
839 | #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ | |
840 | #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ | |
841 | #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ | |
842 | #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ | |
935ecca1 | 843 | |
a1c8a719 PT |
844 | /* e600 core PVR fields */ |
845 | ||
846 | #define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ | |
847 | #define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ | |
848 | #define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ | |
849 | #define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ | |
850 | ||
935ecca1 WD |
851 | /* Processor Version Numbers */ |
852 | ||
3c74e32a WD |
853 | #define PVR_403GA 0x00200000 |
854 | #define PVR_403GB 0x00200100 | |
855 | #define PVR_403GC 0x00200200 | |
856 | #define PVR_403GCX 0x00201400 | |
857 | #define PVR_405GP 0x40110000 | |
858 | #define PVR_405GP_RB 0x40110040 | |
859 | #define PVR_405GP_RC 0x40110082 | |
860 | #define PVR_405GP_RD 0x401100C4 | |
861 | #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ | |
862 | #define PVR_405CR_RA 0x40110041 | |
863 | #define PVR_405CR_RB 0x401100C5 | |
864 | #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ | |
865 | #define PVR_405EP_RA 0x51210950 | |
866 | #define PVR_405GPR_RB 0x50910951 | |
e01bd218 | 867 | #define PVR_405EZ_RA 0x41511460 |
70fab190 SR |
868 | #define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ |
869 | #define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ | |
70fab190 SR |
870 | #define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ |
871 | #define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ | |
872 | #define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ | |
873 | #define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ | |
56f14818 SR |
874 | #define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */ |
875 | #define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */ | |
876 | #define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */ | |
877 | #define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */ | |
3c74e32a WD |
878 | #define PVR_440GP_RB 0x40120440 |
879 | #define PVR_440GP_RC 0x40120481 | |
c157d8e2 | 880 | #define PVR_440EP_RA 0x42221850 |
9a8d82fd | 881 | #define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ |
512f8d5d | 882 | #define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ |
9a8d82fd | 883 | #define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ |
512f8d5d | 884 | #define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ |
1aeed8d7 WD |
885 | #define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ |
886 | #define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ | |
887 | #define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ | |
888 | #define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ | |
3c74e32a WD |
889 | #define PVR_440GX_RA 0x51B21850 |
890 | #define PVR_440GX_RB 0x51B21851 | |
0a7c5391 | 891 | #define PVR_440GX_RC 0x51B21892 |
57275b69 | 892 | #define PVR_440GX_RF 0x51B21894 |
3c74e32a | 893 | #define PVR_405EP_RB 0x51210950 |
95981778 SR |
894 | #define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ |
895 | #define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ | |
896 | #define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ | |
897 | #define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ | |
898 | #define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ | |
899 | #define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ | |
900 | #define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ | |
901 | #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ | |
1aeed8d7 | 902 | #define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ |
999ecd5a | 903 | #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ |
89bcc487 | 904 | #define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/ |
1aeed8d7 | 905 | #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ |
999ecd5a | 906 | #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ |
89bcc487 | 907 | #define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/ |
96e5fc0e FK |
908 | #define PVR_460SX_RA 0x13541800 /* 460SX rev A */ |
909 | #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ | |
910 | #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ | |
911 | #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ | |
3c74e32a WD |
912 | #define PVR_601 0x00010000 |
913 | #define PVR_602 0x00050000 | |
914 | #define PVR_603 0x00030000 | |
915 | #define PVR_603e 0x00060000 | |
916 | #define PVR_603ev 0x00070000 | |
917 | #define PVR_603r 0x00071000 | |
918 | #define PVR_604 0x00040000 | |
919 | #define PVR_604e 0x00090000 | |
920 | #define PVR_604r 0x000A0000 | |
921 | #define PVR_620 0x00140000 | |
922 | #define PVR_740 0x00080000 | |
923 | #define PVR_750 PVR_740 | |
924 | #define PVR_740P 0x10080000 | |
925 | #define PVR_750P PVR_740P | |
1aeed8d7 WD |
926 | #define PVR_7400 0x000C0000 |
927 | #define PVR_7410 0x800C0000 | |
928 | #define PVR_7450 0x80000000 | |
0ac6f8b7 WD |
929 | |
930 | #define PVR_85xx 0x80200000 | |
931 | #define PVR_85xx_REV1 (PVR_85xx | 0x0010) | |
932 | #define PVR_85xx_REV2 (PVR_85xx | 0x0020) | |
933 | ||
debb7354 | 934 | #define PVR_86xx 0x80040000 |
42d1f039 | 935 | |
d865fd09 RR |
936 | #define PVR_VIRTEX5 0x7ff21912 |
937 | ||
935ecca1 WD |
938 | /* |
939 | * For the 8xx processors, all of them report the same PVR family for | |
940 | * the PowerPC core. The various versions of these processors must be | |
941 | * differentiated by the version number in the Communication Processor | |
942 | * Module (CPM). | |
943 | */ | |
3c74e32a WD |
944 | #define PVR_821 0x00500000 |
945 | #define PVR_823 PVR_821 | |
946 | #define PVR_850 PVR_821 | |
947 | #define PVR_860 PVR_821 | |
1636d1c8 | 948 | #define PVR_7400 0x000C0000 |
3c74e32a | 949 | #define PVR_8240 0x00810100 |
935ecca1 | 950 | |
8564acf9 WD |
951 | /* |
952 | * PowerQUICC II family processors report different PVR values depending | |
953 | * on silicon process (HiP3, HiP4, HiP7, etc.) | |
954 | */ | |
1aeed8d7 WD |
955 | #define PVR_8260 PVR_8240 |
956 | #define PVR_8260_HIP3 0x00810101 | |
957 | #define PVR_8260_HIP4 0x80811014 | |
958 | #define PVR_8260_HIP7 0x80822011 | |
5779d8d9 | 959 | #define PVR_8260_HIP7R1 0x80822013 |
e1599e83 | 960 | #define PVR_8260_HIP7RA 0x80822014 |
935ecca1 | 961 | |
a9d87e27 GW |
962 | /* |
963 | * MPC 52xx | |
964 | */ | |
965 | #define PVR_5200 0x80822011 | |
966 | #define PVR_5200B 0x80822014 | |
967 | ||
0ac6f8b7 WD |
968 | /* |
969 | * System Version Register | |
970 | */ | |
971 | ||
972 | /* System Version Register (SVR) field extraction */ | |
973 | ||
974 | #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ | |
975 | #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ | |
976 | ||
d14ba6a7 JL |
977 | #define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ |
978 | ||
0ac6f8b7 WD |
979 | #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ |
980 | #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ | |
981 | ||
982 | #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ | |
983 | #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ | |
984 | ||
1ced1216 AF |
985 | /* Some parts define SVR[0:23] as the SOC version */ |
986 | #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ | |
987 | ||
6b70ffb9 KP |
988 | /* whether MPC8xxxE (i.e. has SEC) */ |
989 | #if defined(CONFIG_MPC85xx) | |
990 | #define IS_E_PROCESSOR(svr) (svr & 0x80000) | |
991 | #else | |
0f898604 | 992 | #if defined(CONFIG_MPC83xx) |
6b70ffb9 KP |
993 | #define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) |
994 | #endif | |
995 | #endif | |
996 | ||
effe4973 KG |
997 | #define IS_SVR_REV(svr, maj, min) \ |
998 | ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) | |
999 | ||
0ac6f8b7 | 1000 | /* |
1ced1216 | 1001 | * SVR_SOC_VER() Version Values |
0ac6f8b7 WD |
1002 | */ |
1003 | ||
1ced1216 AF |
1004 | #define SVR_8533 0x803400 |
1005 | #define SVR_8533_E 0x803C00 | |
71b358cc KG |
1006 | #define SVR_8535 0x803701 |
1007 | #define SVR_8535_E 0x803F01 | |
ef50d6c0 KG |
1008 | #define SVR_8536 0x803700 |
1009 | #define SVR_8536_E 0x803F00 | |
1ced1216 AF |
1010 | #define SVR_8540 0x803000 |
1011 | #define SVR_8541 0x807200 | |
1012 | #define SVR_8541_E 0x807A00 | |
1013 | #define SVR_8543 0x803200 | |
1014 | #define SVR_8543_E 0x803A00 | |
1015 | #define SVR_8544 0x803401 | |
1016 | #define SVR_8544_E 0x803C01 | |
1017 | #define SVR_8545 0x803102 | |
1018 | #define SVR_8545_E 0x803902 | |
1019 | #define SVR_8547_E 0x803901 | |
1020 | #define SVR_8548 0x803100 | |
1021 | #define SVR_8548_E 0x803900 | |
1022 | #define SVR_8555 0x807100 | |
1023 | #define SVR_8555_E 0x807900 | |
1024 | #define SVR_8560 0x807000 | |
1025 | #define SVR_8567 0x807600 | |
1026 | #define SVR_8567_E 0x807E00 | |
1027 | #define SVR_8568 0x807500 | |
1028 | #define SVR_8568_E 0x807D00 | |
22b6dbc1 HW |
1029 | #define SVR_8569 0x808000 |
1030 | #define SVR_8569_E 0x808800 | |
1ced1216 AF |
1031 | #define SVR_8572 0x80E000 |
1032 | #define SVR_8572_E 0x80E800 | |
a713ba92 PA |
1033 | #define SVR_P1011 0x80E500 |
1034 | #define SVR_P1011_E 0x80ED00 | |
87c7661b PA |
1035 | #define SVR_P1020 0x80E400 |
1036 | #define SVR_P1020_E 0x80EC00 | |
a713ba92 PA |
1037 | #define SVR_P2010 0x80E300 |
1038 | #define SVR_P2010_E 0x80EB00 | |
1039 | #define SVR_P2020 0x80E200 | |
1040 | #define SVR_P2020_E 0x80EA00 | |
7e4259bb KG |
1041 | #define SVR_P4040 0x820100 |
1042 | #define SVR_P4040_E 0x820900 | |
1043 | #define SVR_P4080 0x820000 | |
1044 | #define SVR_P4080_E 0x820800 | |
1ced1216 AF |
1045 | |
1046 | #define SVR_8610 0x80A000 | |
1047 | #define SVR_8641 0x809000 | |
1048 | #define SVR_8641D 0x809001 | |
1049 | ||
58442dc0 PA |
1050 | #define SVR_Unknown 0xFFFFFF |
1051 | ||
935ecca1 WD |
1052 | #define _GLOBAL(n)\ |
1053 | .globl n;\ | |
1054 | n: | |
1055 | ||
1056 | /* Macros for setting and retrieving special purpose registers */ | |
1057 | ||
1058 | #define stringify(s) tostring(s) | |
1059 | #define tostring(s) #s | |
1060 | ||
1061 | #define mfdcr(rn) ({unsigned int rval; \ | |
1062 | asm volatile("mfdcr %0," stringify(rn) \ | |
1063 | : "=r" (rval)); rval;}) | |
1064 | #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) | |
1065 | ||
1066 | #define mfmsr() ({unsigned int rval; \ | |
1067 | asm volatile("mfmsr %0" : "=r" (rval)); rval;}) | |
1068 | #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) | |
1069 | ||
1070 | #define mfspr(rn) ({unsigned int rval; \ | |
1071 | asm volatile("mfspr %0," stringify(rn) \ | |
1072 | : "=r" (rval)); rval;}) | |
1073 | #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) | |
1074 | ||
1075 | #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) | |
1076 | ||
1077 | /* Segment Registers */ | |
1078 | ||
1079 | #define SR0 0 | |
1080 | #define SR1 1 | |
1081 | #define SR2 2 | |
1082 | #define SR3 3 | |
1083 | #define SR4 4 | |
1084 | #define SR5 5 | |
1085 | #define SR6 6 | |
1086 | #define SR7 7 | |
1087 | #define SR8 8 | |
1088 | #define SR9 9 | |
1089 | #define SR10 10 | |
1090 | #define SR11 11 | |
1091 | #define SR12 12 | |
1092 | #define SR13 13 | |
1093 | #define SR14 14 | |
1094 | #define SR15 15 | |
1095 | ||
1096 | #ifndef __ASSEMBLY__ | |
4dbdb768 KG |
1097 | |
1098 | struct cpu_type { | |
1099 | char name[15]; | |
1100 | u32 soc_ver; | |
0e870980 | 1101 | u32 num_cores; |
4dbdb768 KG |
1102 | }; |
1103 | ||
96026d42 | 1104 | struct cpu_type *identify_cpu(u32 ver); |
4dbdb768 | 1105 | |
480f6179 | 1106 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
0e870980 PA |
1107 | #define CPU_TYPE_ENTRY(n, v, nc) \ |
1108 | { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), } | |
4890246a | 1109 | #else |
0f898604 | 1110 | #if defined(CONFIG_MPC83xx) |
4890246a KP |
1111 | #define CPU_TYPE_ENTRY(x) {#x, SPR_##x} |
1112 | #endif | |
1113 | #endif | |
1114 | ||
4dbdb768 | 1115 | |
935ecca1 WD |
1116 | #ifndef CONFIG_MACH_SPECIFIC |
1117 | extern int _machine; | |
1118 | extern int have_of; | |
1119 | #endif /* CONFIG_MACH_SPECIFIC */ | |
1120 | ||
1121 | /* what kind of prep workstation we are */ | |
1122 | extern int _prep_type; | |
1123 | /* | |
1124 | * This is used to identify the board type from a given PReP board | |
1125 | * vendor. Board revision is also made available. | |
1126 | */ | |
1127 | extern unsigned char ucSystemType; | |
1128 | extern unsigned char ucBoardRev; | |
1129 | extern unsigned char ucBoardRevMaj, ucBoardRevMin; | |
1130 | ||
1131 | struct task_struct; | |
1132 | void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp); | |
1133 | void release_thread(struct task_struct *); | |
1134 | ||
1135 | /* | |
1136 | * Create a new kernel thread. | |
1137 | */ | |
1138 | extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); | |
1139 | ||
1140 | /* | |
1141 | * Bus types | |
1142 | */ | |
1143 | #define EISA_bus 0 | |
1144 | #define EISA_bus__is_a_macro /* for versions in ksyms.c */ | |
1145 | #define MCA_bus 0 | |
1146 | #define MCA_bus__is_a_macro /* for versions in ksyms.c */ | |
1147 | ||
1148 | /* Lazy FPU handling on uni-processor */ | |
1149 | extern struct task_struct *last_task_used_math; | |
1150 | extern struct task_struct *last_task_used_altivec; | |
1151 | ||
1152 | /* | |
1153 | * this is the minimum allowable io space due to the location | |
1154 | * of the io areas on prep (first one at 0x80000000) but | |
1155 | * as soon as I get around to remapping the io areas with the BATs | |
1156 | * to match the mac we can raise this. -- Cort | |
1157 | */ | |
1158 | #define TASK_SIZE (0x80000000UL) | |
1159 | ||
1160 | /* This decides where the kernel will search for a free chunk of vm | |
1161 | * space during mmap's. | |
1162 | */ | |
1163 | #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) | |
1164 | ||
1165 | typedef struct { | |
1166 | unsigned long seg; | |
1167 | } mm_segment_t; | |
1168 | ||
1169 | struct thread_struct { | |
1170 | unsigned long ksp; /* Kernel stack pointer */ | |
1171 | unsigned long wchan; /* Event task is sleeping on */ | |
1172 | struct pt_regs *regs; /* Pointer to saved register state */ | |
1173 | mm_segment_t fs; /* for get_fs() validation */ | |
1174 | void *pgdir; /* root of page-table tree */ | |
1aeed8d7 | 1175 | signed long last_syscall; |
935ecca1 WD |
1176 | double fpr[32]; /* Complete floating point set */ |
1177 | unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ | |
1178 | unsigned long fpscr; /* Floating point status */ | |
1179 | #ifdef CONFIG_ALTIVEC | |
1180 | vector128 vr[32]; /* Complete AltiVec set */ | |
1181 | vector128 vscr; /* AltiVec status */ | |
1182 | unsigned long vrsave; | |
1183 | #endif /* CONFIG_ALTIVEC */ | |
1184 | }; | |
1185 | ||
1186 | #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) | |
1187 | ||
1188 | #define INIT_THREAD { \ | |
1189 | INIT_SP, /* ksp */ \ | |
1190 | 0, /* wchan */ \ | |
1191 | (struct pt_regs *)INIT_SP - 1, /* regs */ \ | |
1192 | KERNEL_DS, /*fs*/ \ | |
1193 | swapper_pg_dir, /* pgdir */ \ | |
1194 | 0, /* last_syscall */ \ | |
1195 | {0}, 0, 0 \ | |
1196 | } | |
1197 | ||
1198 | /* | |
1199 | * Note: the vm_start and vm_end fields here should *not* | |
1aeed8d7 | 1200 | * be in kernel space. (Could vm_end == vm_start perhaps?) |
935ecca1 WD |
1201 | */ |
1202 | #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ | |
1203 | PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ | |
1204 | 1, NULL, NULL } | |
1205 | ||
1206 | /* | |
1207 | * Return saved PC of a blocked thread. For now, this is the "user" PC | |
1208 | */ | |
1209 | static inline unsigned long thread_saved_pc(struct thread_struct *t) | |
1210 | { | |
1211 | return (t->regs) ? t->regs->nip : 0; | |
1212 | } | |
1213 | ||
1214 | #define copy_segments(tsk, mm) do { } while (0) | |
1215 | #define release_segments(mm) do { } while (0) | |
1216 | #define forget_segments() do { } while (0) | |
1217 | ||
1218 | unsigned long get_wchan(struct task_struct *p); | |
1219 | ||
1220 | #define KSTK_EIP(tsk) ((tsk)->thread.regs->nip) | |
1221 | #define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1]) | |
1222 | ||
1223 | /* | |
1224 | * NOTE! The task struct and the stack go together | |
1225 | */ | |
1226 | #define THREAD_SIZE (2*PAGE_SIZE) | |
1227 | #define alloc_task_struct() \ | |
1228 | ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) | |
1229 | #define free_task_struct(p) free_pages((unsigned long)(p),1) | |
1aeed8d7 | 1230 | #define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) |
935ecca1 WD |
1231 | |
1232 | /* in process.c - for early bootup debug -- Cort */ | |
1233 | int ll_printk(const char *, ...); | |
1234 | void ll_puts(const char *); | |
1235 | ||
1236 | #define init_task (init_task_union.task) | |
1237 | #define init_stack (init_task_union.stack) | |
1238 | ||
1239 | /* In misc.c */ | |
1240 | void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); | |
1241 | ||
1242 | #endif /* ndef ASSEMBLY*/ | |
1243 | ||
1244 | #ifdef CONFIG_MACH_SPECIFIC | |
1245 | #if defined(CONFIG_8xx) | |
1246 | #define _machine _MACH_8xx | |
1247 | #define have_of 0 | |
1248 | #elif defined(CONFIG_OAK) | |
1249 | #define _machine _MACH_oak | |
1250 | #define have_of 0 | |
1251 | #elif defined(CONFIG_WALNUT) | |
1252 | #define _machine _MACH_walnut | |
1253 | #define have_of 0 | |
1254 | #elif defined(CONFIG_APUS) | |
1255 | #define _machine _MACH_apus | |
1256 | #define have_of 0 | |
1257 | #elif defined(CONFIG_GEMINI) | |
1258 | #define _machine _MACH_gemini | |
1259 | #define have_of 0 | |
1260 | #elif defined(CONFIG_8260) | |
1261 | #define _machine _MACH_8260 | |
1262 | #define have_of 0 | |
1263 | #elif defined(CONFIG_SANDPOINT) | |
1264 | #define _machine _MACH_sandpoint | |
756f586a WD |
1265 | #elif defined(CONFIG_HIDDEN_DRAGON) |
1266 | #define _machine _MACH_hidden_dragon | |
935ecca1 WD |
1267 | #define have_of 0 |
1268 | #else | |
1269 | #error "Machine not defined correctly" | |
1270 | #endif | |
1271 | #endif /* CONFIG_MACH_SPECIFIC */ | |
1272 | ||
1273 | #endif /* __ASM_PPC_PROCESSOR_H */ |