[people/ms/u-boot.git] / include / configs / BC3450.h

/*
 * -- Version 1.1 --
 *
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2005
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * (C) Copyright 2005
 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
 *
 * History:
 *	1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU	    */
#define CONFIG_MPC5200		1	/* (more precisely a MPC5200 CPU)   */
#define CONFIG_TQM5200		1	/* ... on a TQM5200 module	    */

#define CONFIG_BC3450		1	/* ... on a BC3450 mainboard	    */
#define CONFIG_BC3450_PS2	1	/*  + a PS/2 converter onboard	    */
#define CONFIG_BC3450_IDE	1	/*  + IDE drives (Compact Flash)    */
#define CONFIG_BC3450_USB	1	/*  + USB support		    */
# define CONFIG_FAT		1	/*    + FAT support		    */
# define CONFIG_EXT2		1	/*    + EXT2 support		    */
#undef CONFIG_BC3450_BUZZER		/*  + Buzzer onboard		    */
#undef CONFIG_BC3450_CAN		/*  + CAN transceiver		    */
#undef CONFIG_BC3450_DS1340		/*  + a RTC DS1340 onboard	    */
#undef CONFIG_BC3450_DS3231		/*  + a RTC DS3231 onboard	tbd */
#undef CONFIG_BC3450_AC97		/*  + AC97 on PSC2,		tbd */
#define CONFIG_BC3450_FP	1	/*  + enable FP O/P		    */
#undef CONFIG_BC3450_CRT		/*  + enable CRT O/P (Debug only!)  */

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	    */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot		    */

#define CONFIG_HIGH_BATS	1	/* High BATs supported		    */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps		*/
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * AT-PS/2 Multiplexer
 */
#ifdef CONFIG_BC3450_PS2
# define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
# define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
# define CONFIG_PS2SERIAL	6		/* .. on PSC6		*/
# define CONFIG_PS2MULT_DELAY	(CFG_HZ/2)	/* Initial delay	*/
# define CONFIG_BOARD_EARLY_INIT_R
#endif /* CONFIG_BC3450_PS2 */

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
# define CONFIG_PCI		1
# define CONFIG_PCI_PNP		1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_NET_MULTI	1
/*#define CONFIG_EEPRO100	XXX - FIXME: conflicts when CONFIG_MII is enabled */
#define CFG_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
#define CONFIG_NS8382X		1

/*
 * Video console
 */
# define CONFIG_VIDEO
# define CONFIG_VIDEO_SM501
# define CONFIG_VIDEO_SM501_32BPP
# define CONFIG_CFB_CONSOLE
# define CONFIG_VIDEO_LOGO
# define CONFIG_VGA_AS_SINGLE_DEVICE
# define CONFIG_CONSOLE_EXTRA_INFO	/* display Board/Device-Infos */
# define CONFIG_VIDEO_SW_CURSOR
# define CONFIG_SPLASH_SCREEN
# define CFG_CONSOLE_IS_IN_ENV

/*
 * Partitions
 */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * USB
 */
#ifdef CONFIG_BC3450_USB
# define CONFIG_USB_OHCI
# define CONFIG_USB_STORAGE
#endif /* CONFIG_BC3450_USB */

/*
 * POST support
 */
#define CONFIG_POST		(CFG_POST_MEMORY   | \
				 CFG_POST_CPU	   | \
				 CFG_POST_I2C)

#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#endif /* CONFIG_POST */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_BSP

#ifdef CONFIG_VIDEO
    #define CONFIG_CMD_BMP
#endif

#ifdef CONFIG_BC3450_IDE
    #define CONFIG_CMD_IDE
#endif

#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
    #ifdef CONFIG_FAT
	#define CONFIG_CMD_FAT
    #endif

    #ifdef CONFIG_EXT2
	#define CONFIG_CMD_EXT2
    #endif
#endif

#ifdef CONFIG_BC3450_USB
    #define CONFIG_CMD_USB
#endif

#ifdef CONFIG_PCI
    #define CONFIG_CMD_PCI
#endif

#ifdef CONFIG_POST
    #define CONFIG_CMD_DIAG
#endif


#define CONFIG_TIMESTAMP		/* display image timestamps */

#if (TEXT_BASE == 0xFC000000)		/* Boot low */
#   define CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo;"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"ipaddr=192.168.1.10\0"						\
	"serverip=192.168.1.3\0"					\
	"netmask=255.255.255.0\0"					\
	"hostname=bc3450\0"						\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"kernel_addr=fc0a0000\0"					\
	"ramdisk_addr=fc1c0000\0"					\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ideargs=setenv bootargs root=/dev/hda2 ro\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"addcons=setenv bootargs $(bootargs) "				\
		"console=ttyS0,$(baudrate) console=tty0\0"		\
	"flash_self=run ramargs addip addcons;"				\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"	\
	"net_nfs=tftp 200000 $(bootfile); "				\
		"run nfsargs addip addcons; bootm\0"			\
	"ide_nfs=run nfsargs addip addcons; "				\
		"disk 200000 0:1; bootm\0"				\
	"ide_ide=run ideargs addip addcons; "				\
		"disk 200000 0:1; bootm\0"				\
	"usb_self=run usbload; run ramargs addip addcons; "		\
		"bootm 200000 400000\0"					\
	"usbload=usb reset; usb scan; usbboot 200000 0:1; "		\
		"usbboot 400000 0:2\0"					\
	"bootfile=uImage\0"						\
	"load=tftp 200000 $(u-boot)\0"					\
	"u-boot=u-boot.bin\0"						\
	"update=protect off FC000000 FC05FFFF;"				\
		"erase FC000000 FC05FFFF;"				\
		"cp.b 200000 FC000000 $(filesize);"			\
		"protect on FC000000 FC05FFFF\0"			\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 */
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
# define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CFG_I2C_MODULE		2	/* Select I2C module #2 */

/*
 * I2C clock frequency
 *
 * Please notice, that the resulting clock frequency could differ from the
 * configured value. This is because the I2C clock is derived from system
 * clock over a frequency divider with only a few divider values. U-boot
 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 * approximation allways lies below the configured value, never above.
 */
#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration for I²C EEPROM M24C32
 * M24C64 should work also. For other EEPROMs config should be verified.
 *
 * The TQM5200 module may hold an EEPROM at address 0x50.
 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x (TQM) */
#define CFG_I2C_EEPROM_ADDR_LEN		2
#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * RTC configuration
 */
#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
# define CONFIG_RTC_M41T11	1
# define CFG_I2C_RTC_ADDR	0x68
#else
# define CONFIG_RTC_MPC5200	1	/* use MPC5200 internal RTC */
# define CONFIG_BOARD_EARLY_INIT_R
#endif

/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */

/* use CFI flash driver if no module variant is spezified */
#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */

#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
#else	/* CFG_LOWBOOT */
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
#endif	/* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/* Dynamic MTD partition support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
						"1408k(kernel),"	\
						"2m(initrd),"		\
						"4m(small-fs),"		\
						"16m(big-fs),"		\
						"8m(misc)"

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x10000
#define CFG_ENV_SECT_SIZE	0x20000
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
# define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
# define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif /*CONFIG_POST*/

#define CFG_GBL_DATA_SIZE	128	/* Bytes reserved for initial data  */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE	TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(384 << 10) /* Reserve 384 kB for Monitor   */
#define CFG_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
#define CFG_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */

/*
 * Ethernet configuration
 *
 * Define CONFIG_FEC10MBIT to force FEC at 10MBIT
 */
#define CONFIG_MPC5xxx_FEC	1
#undef CONFIG_FEC_10MBIT
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration on BC3450
 *
 *  PSC1:   UART1 (Service-UART)	 [0x xxxxxxx4]
 *  PSC2:   UART2			 [0x xxxxxx4x]
 *    or:   AC/97 if CONFIG_BC3450_AC97	 [0x xxxxxx2x]
 *  PSC3:   USB2			 [0x xxxxx1xx]
 *  USB:    UART4(ext.)/UART5(int.)	 [0x xxxx2xxx]
 *	      (this has to match
 *	      CONFIG_USB_CONFIG which is
 *	      used by usb_ohci.c to set
 *	      the USB ports)
 *  Eth:    10/100Mbit Ethernet		 [0x xxx0xxxx]
 *	      (this is reset to '5'
 *	      in FEC driver: fec.c)
 *  PSC6:   UART6 (int. to PS/2 contr.)	 [0x xx5xxxxx]
 *  ATA/CS: ???				 [0x x1xxxxxx]
 *	    FIXME! UM Fig 2-10 suggests	 [0x x0xxxxxx]
 *  CS1:    Use Pin gpio_wkup_6 as second
 *	    SDRAM chip select (mem_cs1)
 *  Timer:  CAN2 / SPI
 *  I2C:    CAN1 / I²C2		  [0x bxxxxxxx]
 */
#ifdef CONFIG_BC3450_AC97
# define CFG_GPS_PORT_CONFIG	0xb1502124
#else /* PSC2=UART2 */
# define CFG_GPS_PORT_CONFIG	0xb1502144
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP				/* undef to save memory	    */
#define CFG_PROMPT		"=> "		/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024		/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256		/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size  */
#define CFG_MAXARGS		16		/* max no of command args   */
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Arg. Buffer Size    */

#define CFG_ALT_MEMTEST				/* Enable an alternative,   */
						/*  more extensive mem test */

#define CFG_MEMTEST_START	0x00100000	/* memtest works on	    */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	    */

#define CFG_LOAD_ADDR		0x100000	/* default load address	    */

#define CFG_HZ			1000		/* dec freq: 1ms ticks	    */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		    */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value    */
#endif

/*
 * Enable loopw command.
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
# define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
# define CFG_HID0_FINAL		HID0_ICE
#else
# define CFG_HID0_INIT		0
# define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
# define CFG_BOOTCS_CFG		0x0008DF30	/* for pci_clk	= 66 MHz */
#else
# define CFG_BOOTCS_CFG		0x0004DF30	/* for pci_clk = 33 MHz	 */
#endif
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

/* automatic configuration of chip selects */
#ifdef CONFIG_TQM5200
# define CONFIG_LAST_STAGE_INIT
#endif /* CONFIG_TQM5200 */

/*
 * SRAM - Do not map below 2 GB in address space, because this area is used
 * for SDRAM autosizing.
 */
#ifdef CONFIG_TQM5200
# define CFG_CS2_START		0xE5000000
# define CFG_CS2_SIZE		0x100000	/* 1 MByte */
# define CFG_CS2_CFG		0x0004D930
#endif /* CONFIG_TQM5200 */

/*
 * Grafic controller - Do not map below 2 GB in address space, because this
 * area is used for SDRAM autosizing.
 */
#ifdef CONFIG_TQM5200
# define SM501_FB_BASE		0xE0000000
# define CFG_CS1_START		(SM501_FB_BASE)
# define CFG_CS1_SIZE		0x4000000	/* 64 MByte */
# define CFG_CS1_CFG		0x8F48FF70
# define SM501_MMIO_BASE	CFG_CS1_START + 0x03E00000
#endif /* CONFIG_TQM5200 */

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for	*/
						/*  flash and SM501	*/

#define CFG_RESET_ADDRESS	0xff000000

/*
 * USB stuff
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00002000	/* we're using Port 2	*/

/*
 * IDE/ATA stuff Supports IDE harddisk
 */
#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	  not supported */
#undef	CONFIG_IDE_LED			/* LED for ide	  not supported */

#define CONFIG_IDE_RESET		/* reset for ide      supported */
#define CONFIG_IDE_PREINIT

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O */
#define CFG_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses */
#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)

/* Offset for alternate registers */
#define CFG_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers */
#define CFG_ATA_STRIDE		4

#endif /* __CONFIG_H */
Commit	Line	Data
6ca24c64	1	/*
	2	* -- Version 1.1 --
	3	*
	4	* (C) Copyright 2003-2005
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* (C) Copyright 2004-2005
	8	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	9	*
	10	* (C) Copyright 2005
	11	* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
	12	*
	13	* History:
	14	* 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
	15	*
	16	* See file CREDITS for list of people who contributed to this
	17	* project.
	18	*
	19	* This program is free software; you can redistribute it and/or
	20	* modify it under the terms of the GNU General Public License as
	21	* published by the Free Software Foundation; either version 2 of
	22	* the License, or (at your option) any later version.
	23	*
	24	* This program is distributed in the hope that it will be useful,
	25	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	26	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	27	* GNU General Public License for more details.
	28	*
	29	* You should have received a copy of the GNU General Public License
	30	* along with this program; if not, write to the Free Software
	31	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	32	* MA 02111-1307 USA
	33	*/
	34
	35	#ifndef __CONFIG_H
	36	#define __CONFIG_H
	37
	38	/*
	39	* High Level Configuration Options
	40	*/
	41	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	42	#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
	43	#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
	44
610cf367 WD	45	#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
	46	#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
	47	#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
6ca24c64	48	#define CONFIG_BC3450_USB 1 /* + USB support */
	49	# define CONFIG_FAT 1 /* + FAT support */
	50	# define CONFIG_EXT2 1 /* + EXT2 support */
	51	#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
	52	#undef CONFIG_BC3450_CAN /* + CAN transceiver */
	53	#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
610cf367 WD	54	#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
610cf367 WD	55	#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
6ca24c64	56	#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
	57	#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
	58
610cf367	59	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
6ca24c64	60
	61	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	62	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	63
31d82672 BB	64	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	65
6ca24c64	66	/*
	67	* Serial console configuration
	68	*/
	69	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	70	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	71	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	72
	73	/*
	74	* AT-PS/2 Multiplexer
	75	*/
	76	#ifdef CONFIG_BC3450_PS2
	77	# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
	78	# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
	79	# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
	80	# define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
	81	# define CONFIG_BOARD_EARLY_INIT_R
	82	#endif /* CONFIG_BC3450_PS2 */
	83
	84	/*
	85	* PCI Mapping:
	86	* 0x40000000 - 0x4fffffff - PCI Memory
	87	* 0x50000000 - 0x50ffffff - PCI IO Space
	88	*/
	89	# define CONFIG_PCI 1
	90	# define CONFIG_PCI_PNP 1
610cf367	91	/* #define CONFIG_PCI_SCAN_SHOW 1 */
f33fca22	92	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
6ca24c64	93
	94	#define CONFIG_PCI_MEM_BUS 0x40000000
	95	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	96	#define CONFIG_PCI_MEM_SIZE 0x10000000
	97
	98	#define CONFIG_PCI_IO_BUS 0x50000000
	99	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	100	#define CONFIG_PCI_IO_SIZE 0x01000000
	101
	102	#define CONFIG_NET_MULTI 1
	103	/#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled /
610cf367	104	#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
6ca24c64	105	#define CONFIG_NS8382X 1
6ca24c64	106
6ca24c64	107	/*
	108	* Video console
	109	*/
	110	# define CONFIG_VIDEO
	111	# define CONFIG_VIDEO_SM501
	112	# define CONFIG_VIDEO_SM501_32BPP
	113	# define CONFIG_CFB_CONSOLE
	114	# define CONFIG_VIDEO_LOGO
	115	# define CONFIG_VGA_AS_SINGLE_DEVICE
	116	# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
	117	# define CONFIG_VIDEO_SW_CURSOR
	118	# define CONFIG_SPLASH_SCREEN
	119	# define CFG_CONSOLE_IS_IN_ENV
	120
610cf367 WD	121	/*
610cf367 WD	122	* Partitions
6ca24c64	123	*/
	124	#define CONFIG_MAC_PARTITION
	125	#define CONFIG_DOS_PARTITION
	126	#define CONFIG_ISO_PARTITION
	127
610cf367 WD	128	/*
610cf367 WD	129	* USB
6ca24c64	130	*/
	131	#ifdef CONFIG_BC3450_USB
	132	# define CONFIG_USB_OHCI
6ca24c64	133	# define CONFIG_USB_STORAGE
6ca24c64	134	#endif /* CONFIG_BC3450_USB */
6ca24c64	135
610cf367 WD	136	/*
610cf367 WD	137	* POST support
6ca24c64	138	*/
	139	#define CONFIG_POST (CFG_POST_MEMORY \| \
	140	CFG_POST_CPU \| \
	141	CFG_POST_I2C)
	142
	143	#ifdef CONFIG_POST
6ca24c64	144	/* preserve space for the post_word at end of on-chip SRAM */
6ca24c64	145	# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
6ca24c64	146	#endif /* CONFIG_POST */
6ca24c64	147
de8b2a6e	148
11799434 JL	149	/*
	150	* BOOTP options
	151	*/
	152	#define CONFIG_BOOTP_BOOTFILESIZE
	153	#define CONFIG_BOOTP_BOOTPATH
	154	#define CONFIG_BOOTP_GATEWAY
	155	#define CONFIG_BOOTP_HOSTNAME
	156
	157
610cf367	158	/*
de8b2a6e	159	* Command line configuration.
6ca24c64	160	*/
de8b2a6e JL	161	#include <config_cmd_default.h>
	162
	163	#define CONFIG_CMD_ASKENV
	164	#define CONFIG_CMD_DATE
	165	#define CONFIG_CMD_DHCP
	166	#define CONFIG_CMD_ECHO
	167	#define CONFIG_CMD_EEPROM
	168	#define CONFIG_CMD_I2C
	169	#define CONFIG_CMD_JFFS2
	170	#define CONFIG_CMD_MII
	171	#define CONFIG_CMD_NFS
	172	#define CONFIG_CMD_PING
de8b2a6e JL	173	#define CONFIG_CMD_REGINFO
	174	#define CONFIG_CMD_SNTP
	175	#define CONFIG_CMD_BSP
	176
	177	#ifdef CONFIG_VIDEO
	178	#define CONFIG_CMD_BMP
	179	#endif
	180
6ca24c64	181	#ifdef CONFIG_BC3450_IDE
de8b2a6e JL	182	#define CONFIG_CMD_IDE
de8b2a6e JL	183	#endif
6ca24c64	184
de8b2a6e JL	185	#if defined(CONFIG_BC3450_IDE) \|\| defined(CONFIG_BC3450_USB)
	186	#ifdef CONFIG_FAT
	187	#define CONFIG_CMD_FAT
	188	#endif
6ca24c64	189
de8b2a6e JL	190	#ifdef CONFIG_EXT2
	191	#define CONFIG_CMD_EXT2
	192	#endif
	193	#endif
	194
	195	#ifdef CONFIG_BC3450_USB
	196	#define CONFIG_CMD_USB
	197	#endif
5728be38	198
de8b2a6e JL	199	#ifdef CONFIG_PCI
	200	#define CONFIG_CMD_PCI
	201	#endif
6ca24c64	202
af075ee9 JL	203	#ifdef CONFIG_POST
	204	#define CONFIG_CMD_DIAG
	205	#endif
	206
6ca24c64	207
610cf367	208	#define CONFIG_TIMESTAMP /* display image timestamps */
6ca24c64	209
	210	#if (TEXT_BASE == 0xFC000000) /* Boot low */
	211	# define CFG_LOWBOOT 1
	212	#endif
	213
	214	/*
	215	* Autobooting
	216	*/
	217	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	218	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	219
	220	#define CONFIG_PREBOOT "echo;" \
32bf3d14	221	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
6ca24c64	222	"echo;"
	223
	224	#undef CONFIG_BOOTARGS
	225
	226	#define CONFIG_EXTRA_ENV_SETTINGS \
	227	"netdev=eth0\0" \
	228	"ipaddr=192.168.1.10\0" \
	229	"serverip=192.168.1.3\0" \
	230	"netmask=255.255.255.0\0" \
610cf367	231	"hostname=bc3450\0" \
6ca24c64	232	"rootpath=/opt/eldk/ppc_6xx\0" \
610cf367 WD	233	"kernel_addr=fc0a0000\0" \
610cf367 WD	234	"ramdisk_addr=fc1c0000\0" \
6ca24c64	235	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	236	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	237	"nfsroot=$(serverip):$(rootpath)\0" \
610cf367	238	"ideargs=setenv bootargs root=/dev/hda2 ro\0" \
6ca24c64	239	"addip=setenv bootargs $(bootargs) " \
	240	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	241	":$(hostname):$(netdev):off panic=1\0" \
	242	"addcons=setenv bootargs $(bootargs) " \
	243	"console=ttyS0,$(baudrate) console=tty0\0" \
	244	"flash_self=run ramargs addip addcons;" \
	245	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	246	"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
	247	"net_nfs=tftp 200000 $(bootfile); " \
	248	"run nfsargs addip addcons; bootm\0" \
610cf367 WD	249	"ide_nfs=run nfsargs addip addcons; " \
	250	"disk 200000 0:1; bootm\0" \
	251	"ide_ide=run ideargs addip addcons; " \
	252	"disk 200000 0:1; bootm\0" \
6ca24c64	253	"usb_self=run usbload; run ramargs addip addcons; " \
	254	"bootm 200000 400000\0" \
	255	"usbload=usb reset; usb scan; usbboot 200000 0:1; " \
	256	"usbboot 400000 0:2\0" \
	257	"bootfile=uImage\0" \
	258	"load=tftp 200000 $(u-boot)\0" \
	259	"u-boot=u-boot.bin\0" \
	260	"update=protect off FC000000 FC05FFFF;" \
	261	"erase FC000000 FC05FFFF;" \
	262	"cp.b 200000 FC000000 $(filesize);" \
	263	"protect on FC000000 FC05FFFF\0" \
	264	""
	265
	266	#define CONFIG_BOOTCOMMAND "run flash_self"
	267
	268	/*
	269	* IPB Bus clocking configuration.
	270	*/
c99512d6	271	#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
6ca24c64	272
	273	/*
	274	* PCI Bus clocking configuration
	275	*
	276	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
c99512d6 BS	277	* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
c99512d6 BS	278	* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
6ca24c64	279	*/
c99512d6 BS	280	#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
c99512d6 BS	281	# define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
6ca24c64	282	#endif
	283
	284	/*
	285	* I2C configuration
	286	*/
	287	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	288	#define CFG_I2C_MODULE 2 /* Select I2C module #2 */
	289
	290	/*
	291	* I2C clock frequency
	292	*
	293	* Please notice, that the resulting clock frequency could differ from the
	294	* configured value. This is because the I2C clock is derived from system
	295	* clock over a frequency divider with only a few divider values. U-boot
	296	* calculates the best approximation for CFG_I2C_SPEED. However the calculated
	297	* approximation allways lies below the configured value, never above.
	298	*/
	299	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	300	#define CFG_I2C_SLAVE 0x7F
	301
	302	/*
610cf367	303	* EEPROM configuration for I²C EEPROM M24C32
6ca24c64	304	* M24C64 should work also. For other EEPROMs config should be verified.
610cf367	305	*
6ca24c64	306	* The TQM5200 module may hold an EEPROM at address 0x50.
	307	*/
	308	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
	309	#define CFG_I2C_EEPROM_ADDR_LEN 2
	310	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	311	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
	312
	313	/*
	314	* RTC configuration
	315	*/
	316	#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
	317	# define CONFIG_RTC_M41T11 1
	318	# define CFG_I2C_RTC_ADDR 0x68
	319	#else
	320	# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
	321	# define CONFIG_BOARD_EARLY_INIT_R
	322	#endif
	323
	324	/*
	325	* Flash configuration
	326	*/
	327	#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
	328
	329	/* use CFI flash driver if no module variant is spezified */
	330	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	331	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6ca24c64	332	#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
	333	#define CFG_FLASH_EMPTY_INFO
	334	#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
	335	#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
	336	#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
	337
	338	#if !defined(CFG_LOWBOOT)
	339	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
	340	#else /* CFG_LOWBOOT */
	341	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
	342	#endif /* CFG_LOWBOOT */
	343	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
	344	(= chip selects) */
	345	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	346	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	347
	348	/* Dynamic MTD partition support */
	349	#define CONFIG_JFFS2_CMDLINE
	350	#define MTDIDS_DEFAULT "nor0=TQM5200-0"
	351	#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
	352	"1408k(kernel)," \
	353	"2m(initrd)," \
	354	"4m(small-fs)," \
	355	"16m(big-fs)," \
	356	"8m(misc)"
	357
	358	/*
	359	* Environment settings
	360	*/
5a1aceb0	361	#define CONFIG_ENV_IS_IN_FLASH 1
6ca24c64	362	#define CFG_ENV_SIZE 0x10000
	363	#define CFG_ENV_SECT_SIZE 0x20000
	364	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
610cf367	365	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
6ca24c64	366
	367	/*
	368	* Memory map
	369	*/
	370	#define CFG_MBAR 0xF0000000
	371	#define CFG_SDRAM_BASE 0x00000000
	372	#define CFG_DEFAULT_MBAR 0x80000000
	373
	374	/* Use ON-Chip SRAM until RAM will be available */
	375	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	376	#ifdef CONFIG_POST
	377	/* preserve space for the post_word at end of on-chip SRAM */
	378	# define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
	379	#else
	380	# define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
	381	#endif /CONFIG_POST/
	382
	383	#define CFG_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
	384	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	385	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	386
	387	#define CFG_MONITOR_BASE TEXT_BASE
	388	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	389	# define CFG_RAMBOOT 1
	390	#endif
	391
	392	#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
	393	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	394	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	395
	396	/*
	397	* Ethernet configuration
	398	*
	399	* Define CONFIG_FEC10MBIT to force FEC at 10MBIT
	400	*/
	401	#define CONFIG_MPC5xxx_FEC 1
	402	#undef CONFIG_FEC_10MBIT
	403	#define CONFIG_PHY_ADDR 0x00
	404
	405	/*
	406	* GPIO configuration on BC3450
	407	*
610cf367 WD	408	* PSC1: UART1 (Service-UART) [0x xxxxxxx4]
	409	* PSC2: UART2 [0x xxxxxx4x]
	410	* or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
	411	* PSC3: USB2 [0x xxxxx1xx]
	412	* USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
	413	* (this has to match
	414	* CONFIG_USB_CONFIG which is
	415	* used by usb_ohci.c to set
	416	* the USB ports)
	417	* Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
	418	* (this is reset to '5'
	419	* in FEC driver: fec.c)
	420	* PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
	421	* ATA/CS: ??? [0x x1xxxxxx]
	422	* FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
6ca24c64	423	* CS1: Use Pin gpio_wkup_6 as second
610cf367	424	* SDRAM chip select (mem_cs1)
6ca24c64	425	* Timer: CAN2 / SPI
610cf367	426	* I2C: CAN1 / I²C2 [0x bxxxxxxx]
6ca24c64	427	*/
	428	#ifdef CONFIG_BC3450_AC97
	429	# define CFG_GPS_PORT_CONFIG 0xb1502124
	430	#else /* PSC2=UART2 */
	431	# define CFG_GPS_PORT_CONFIG 0xb1502144
	432	#endif
	433
	434	/*
	435	* Miscellaneous configurable options
	436	*/
	437	#define CFG_LONGHELP /* undef to save memory */
	438	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
de8b2a6e	439	#if defined(CONFIG_CMD_KGDB)
6ca24c64	440	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	441	#else
	442	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	443	#endif
	444	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	445	#define CFG_MAXARGS 16 /* max no of command args */
	446	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Arg. Buffer Size */
	447
	448	#define CFG_ALT_MEMTEST /* Enable an alternative, */
	449	/* more extensive mem test */
	450
	451	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	452	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	453
610cf367	454	#define CFG_LOAD_ADDR 0x100000 /* default load address */
6ca24c64	455
	456	#define CFG_HZ 1000 /* dec freq: 1ms ticks */
	457
de8b2a6e JL	458	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	459	#if defined(CONFIG_CMD_KGDB)
	460	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	461	#endif
	462
6ca24c64	463	/*
11799434	464	* Enable loopw command.
6ca24c64	465	*/
	466	#define CONFIG_LOOPW
	467
	468	/*
	469	* Various low-level settings
	470	*/
	471	#if defined(CONFIG_MPC5200)
	472	# define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	473	# define CFG_HID0_FINAL HID0_ICE
	474	#else
	475	# define CFG_HID0_INIT 0
	476	# define CFG_HID0_FINAL 0
	477	#endif
	478
	479	#define CFG_BOOTCS_START CFG_FLASH_BASE
	480	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
c99512d6	481	#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
610cf367	482	# define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
6ca24c64	483	#else
	484	# define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
	485	#endif
	486	#define CFG_CS0_START CFG_FLASH_BASE
	487	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	488
	489	/* automatic configuration of chip selects */
	490	#ifdef CONFIG_TQM5200
	491	# define CONFIG_LAST_STAGE_INIT
	492	#endif /* CONFIG_TQM5200 */
	493
	494	/*
	495	* SRAM - Do not map below 2 GB in address space, because this area is used
	496	* for SDRAM autosizing.
	497	*/
	498	#ifdef CONFIG_TQM5200
	499	# define CFG_CS2_START 0xE5000000
	500	# define CFG_CS2_SIZE 0x100000 /* 1 MByte */
	501	# define CFG_CS2_CFG 0x0004D930
	502	#endif /* CONFIG_TQM5200 */
	503
	504	/*
	505	* Grafic controller - Do not map below 2 GB in address space, because this
	506	* area is used for SDRAM autosizing.
	507	*/
	508	#ifdef CONFIG_TQM5200
	509	# define SM501_FB_BASE 0xE0000000
	510	# define CFG_CS1_START (SM501_FB_BASE)
	511	# define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
	512	# define CFG_CS1_CFG 0x8F48FF70
	513	# define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
	514	#endif /* CONFIG_TQM5200 */
	515
	516	#define CFG_CS_BURST 0x00000000
	517	#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
	518	/* flash and SM501 */
	519
	520	#define CFG_RESET_ADDRESS 0xff000000
	521
	522	/*
	523	* USB stuff
	524	*/
	525	#define CONFIG_USB_CLOCK 0x0001BBBB
610cf367	526	#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
6ca24c64	527
	528	/*
	529	* IDE/ATA stuff Supports IDE harddisk
	530	*/
	531	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	532
610cf367 WD	533	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
610cf367 WD	534	#undef CONFIG_IDE_LED /* LED for ide not supported */
6ca24c64	535
610cf367	536	#define CONFIG_IDE_RESET /* reset for ide supported */
6ca24c64	537	#define CONFIG_IDE_PREINIT
	538
	539	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	540	#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
	541
	542	#define CFG_ATA_IDE0_OFFSET 0x0000
	543
	544	#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
	545
	546	/* Offset for data I/O */
	547	#define CFG_ATA_DATA_OFFSET (0x0060)
	548
	549	/* Offset for normal register accesses */
	550	#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
	551
	552	/* Offset for alternate registers */
	553	#define CFG_ATA_ALT_OFFSET (0x005C)
	554
	555	/* Interval between registers */
	556	#define CFG_ATA_STRIDE 4
	557
	558	#endif /* __CONFIG_H */