[people/ms/u-boot.git] / include / configs / BC3450.h

/*
 * -- Version 1.1 --
 *
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2005
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * (C) Copyright 2005
 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
 *
 * History:
 *	1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_MPC5200		1	/* This is a MPC5200 CPU	    */
#define CONFIG_TQM5200		1	/* ... on a TQM5200 module	    */

#define CONFIG_BC3450		1	/* ... on a BC3450 mainboard	    */
#define CONFIG_BC3450_PS2	1	/*  + a PS/2 converter onboard	    */
#define CONFIG_BC3450_IDE	1	/*  + IDE drives (Compact Flash)    */
#define CONFIG_BC3450_USB	1	/*  + USB support		    */
# define CONFIG_FAT		1	/*    + FAT support		    */
# define CONFIG_EXT2		1	/*    + EXT2 support		    */
#undef CONFIG_BC3450_BUZZER		/*  + Buzzer onboard		    */
#undef CONFIG_BC3450_CAN		/*  + CAN transceiver		    */
#undef CONFIG_BC3450_DS1340		/*  + a RTC DS1340 onboard	    */
#undef CONFIG_BC3450_DS3231		/*  + a RTC DS3231 onboard	tbd */
#undef CONFIG_BC3450_AC97		/*  + AC97 on PSC2,		tbd */
#define CONFIG_BC3450_FP	1	/*  + enable FP O/P		    */
#undef CONFIG_BC3450_CRT		/*  + enable CRT O/P (Debug only!)  */

/*
 * Valid values for CONFIG_SYS_TEXT_BASE are:
 * 0xFC000000	boot low (standard configuration with room for
 *		max 64 MByte Flash ROM)
 * 0x00100000	boot from RAM (for testing only)
 */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFC000000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	    */

#define CONFIG_HIGH_BATS	1	/* High BATs supported		    */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1		*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps		*/
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * AT-PS/2 Multiplexer
 */
#ifdef CONFIG_BC3450_PS2
# define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
# define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
# define CONFIG_PS2SERIAL	6		/* .. on PSC6		*/
# define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
# define CONFIG_BOARD_EARLY_INIT_R
#endif /* CONFIG_BC3450_PS2 */

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
# define CONFIG_PCI		1
# define CONFIG_PCI_PNP		1
/* #define CONFIG_PCI_SCAN_SHOW 1 */
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

/*#define CONFIG_EEPRO100	XXX - FIXME: conflicts when CONFIG_MII is enabled */
#define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
#define CONFIG_NS8382X		1

/*
 * Video console
 */
# define CONFIG_VIDEO
# define CONFIG_VIDEO_SM501
# define CONFIG_VIDEO_SM501_32BPP
# define CONFIG_CFB_CONSOLE
# define CONFIG_VIDEO_LOGO
# define CONFIG_VGA_AS_SINGLE_DEVICE
# define CONFIG_CONSOLE_EXTRA_INFO	/* display Board/Device-Infos */
# define CONFIG_VIDEO_SW_CURSOR
# define CONFIG_SPLASH_SCREEN
# define CONFIG_SYS_CONSOLE_IS_IN_ENV

/*
 * Partitions
 */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/*
 * USB
 */
#ifdef CONFIG_BC3450_USB
# define CONFIG_USB_OHCI
# define CONFIG_USB_STORAGE
#endif /* CONFIG_BC3450_USB */

/*
 * POST support
 */
#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY   | \
				 CONFIG_SYS_POST_CPU	   | \
				 CONFIG_SYS_POST_I2C)

#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#endif /* CONFIG_POST */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_BSP

#ifdef CONFIG_VIDEO
    #define CONFIG_CMD_BMP
#endif

#ifdef CONFIG_BC3450_IDE
    #define CONFIG_CMD_IDE
#endif

#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
    #ifdef CONFIG_FAT
	#define CONFIG_CMD_FAT
    #endif

    #ifdef CONFIG_EXT2
	#define CONFIG_CMD_EXT2
    #endif
#endif

#ifdef CONFIG_BC3450_USB
    #define CONFIG_CMD_USB
#endif

#ifdef CONFIG_PCI
    #define CONFIG_CMD_PCI
#endif

#ifdef CONFIG_POST
    #define CONFIG_CMD_DIAG
#endif


#define CONFIG_TIMESTAMP		/* display image timestamps */

#if (CONFIG_SYS_TEXT_BASE == 0xFC000000)		/* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo;"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"ipaddr=192.168.1.10\0"						\
	"serverip=192.168.1.3\0"					\
	"netmask=255.255.255.0\0"					\
	"hostname=bc3450\0"						\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"kernel_addr=fc0a0000\0"					\
	"ramdisk_addr=fc1c0000\0"					\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$(serverip):$(rootpath)\0"			\
	"ideargs=setenv bootargs root=/dev/hda2 ro\0"			\
	"addip=setenv bootargs $(bootargs) "				\
		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
		":$(hostname):$(netdev):off panic=1\0"			\
	"addcons=setenv bootargs $(bootargs) "				\
		"console=ttyS0,$(baudrate) console=tty0\0"		\
	"flash_self=run ramargs addip addcons;"				\
		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
	"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"	\
	"net_nfs=tftp 200000 $(bootfile); "				\
		"run nfsargs addip addcons; bootm\0"			\
	"ide_nfs=run nfsargs addip addcons; "				\
		"disk 200000 0:1; bootm\0"				\
	"ide_ide=run ideargs addip addcons; "				\
		"disk 200000 0:1; bootm\0"				\
	"usb_self=run usbload; run ramargs addip addcons; "		\
		"bootm 200000 400000\0"					\
	"usbload=usb reset; usb scan; usbboot 200000 0:1; "		\
		"usbboot 400000 0:2\0"					\
	"bootfile=uImage\0"						\
	"load=tftp 200000 $(u-boot)\0"					\
	"u-boot=u-boot.bin\0"						\
	"update=protect off FC000000 FC05FFFF;"				\
		"erase FC000000 FC05FFFF;"				\
		"cp.b 200000 FC000000 $(filesize);"			\
		"protect on FC000000 FC05FFFF\0"			\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

/*
 * IPB Bus clocking configuration.
 */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 */
#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */

/*
 * I2C clock frequency
 *
 * Please notice, that the resulting clock frequency could differ from the
 * configured value. This is because the I2C clock is derived from system
 * clock over a frequency divider with only a few divider values. U-boot
 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 * approximation allways lies below the configured value, never above.
 */
#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration for I²C EEPROM M24C32
 * M24C64 should work also. For other EEPROMs config should be verified.
 *
 * The TQM5200 module may hold an EEPROM at address 0x50.
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x (TQM) */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * RTC configuration
 */
#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
# define CONFIG_RTC_M41T11	1
# define CONFIG_SYS_I2C_RTC_ADDR	0x68
#else
# define CONFIG_RTC_MPC5200	1	/* use MPC5200 internal RTC */
# define CONFIG_BOARD_EARLY_INIT_R
#endif

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE /* 0xFC000000 */

/* use CFI flash driver if no module variant is spezified */
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_BOOTCS_START }
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_SIZE		0x04000000 /* 64 MByte */
#define CONFIG_SYS_MAX_FLASH_SECT	512	/* max num of sects on one chip */
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */

#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
#else	/* CONFIG_SYS_LOWBOOT */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00060000)
#endif	/* CONFIG_SYS_LOWBOOT */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/* Dynamic MTD partition support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
						"1408k(kernel),"	\
						"2m(initrd),"		\
						"4m(small-fs),"		\
						"16m(big-fs),"		\
						"8m(misc)"

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
# define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
#else
# define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
#endif /*CONFIG_POST*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(384 << 10) /* Reserve 384 kB for Monitor   */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10) /* Reserve 128 kB for malloc()  */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)   /* Initial Memory map for Linux */

/*
 * Ethernet configuration
 *
 * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#undef CONFIG_MPC5xxx_MII10
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration on BC3450
 *
 *  PSC1:   UART1 (Service-UART)	 [0x xxxxxxx4]
 *  PSC2:   UART2			 [0x xxxxxx4x]
 *    or:   AC/97 if CONFIG_BC3450_AC97	 [0x xxxxxx2x]
 *  PSC3:   USB2			 [0x xxxxx1xx]
 *  USB:    UART4(ext.)/UART5(int.)	 [0x xxxx2xxx]
 *	      (this has to match
 *	      CONFIG_USB_CONFIG which is
 *	      used by usb_ohci.c to set
 *	      the USB ports)
 *  Eth:    10/100Mbit Ethernet		 [0x xxx0xxxx]
 *	      (this is reset to '5'
 *	      in FEC driver: fec.c)
 *  PSC6:   UART6 (int. to PS/2 contr.)	 [0x xx5xxxxx]
 *  ATA/CS: ???				 [0x x1xxxxxx]
 *	    FIXME! UM Fig 2-10 suggests	 [0x x0xxxxxx]
 *  CS1:    Use Pin gpio_wkup_6 as second
 *	    SDRAM chip select (mem_cs1)
 *  Timer:  CAN2 / SPI
 *  I2C:    CAN1 / I²C2		  [0x bxxxxxxx]
 */
#ifdef CONFIG_BC3450_AC97
# define CONFIG_SYS_GPS_PORT_CONFIG	0xb1502124
#else /* PSC2=UART2 */
# define CONFIG_SYS_GPS_PORT_CONFIG	0xb1502144
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory	    */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size  */
#define CONFIG_SYS_MAXARGS		16		/* max no of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Arg. Buffer Size    */

#define CONFIG_SYS_ALT_MEMTEST				/* Enable an alternative,   */
						/*  more extensive mem test */

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	    */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	    */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	    */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		    */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value    */
#endif

/*
 * Enable loopw command.
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
# define CONFIG_SYS_BOOTCS_CFG		0x0008DF30	/* for pci_clk	= 66 MHz */
#else
# define CONFIG_SYS_BOOTCS_CFG		0x0004DF30	/* for pci_clk = 33 MHz	 */
#endif
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* automatic configuration of chip selects */
#ifdef CONFIG_TQM5200
# define CONFIG_LAST_STAGE_INIT
#endif /* CONFIG_TQM5200 */

/*
 * SRAM - Do not map below 2 GB in address space, because this area is used
 * for SDRAM autosizing.
 */
#ifdef CONFIG_TQM5200
# define CONFIG_SYS_CS2_START		0xE5000000
# define CONFIG_SYS_CS2_SIZE		0x100000	/* 1 MByte */
# define CONFIG_SYS_CS2_CFG		0x0004D930
#endif /* CONFIG_TQM5200 */

/*
 * Grafic controller - Do not map below 2 GB in address space, because this
 * area is used for SDRAM autosizing.
 */
#ifdef CONFIG_TQM5200
# define SM501_FB_BASE		0xE0000000
# define CONFIG_SYS_CS1_START		(SM501_FB_BASE)
# define CONFIG_SYS_CS1_SIZE		0x4000000	/* 64 MByte */
# define CONFIG_SYS_CS1_CFG		0x8F48FF70
# define SM501_MMIO_BASE	CONFIG_SYS_CS1_START + 0x03E00000
#endif /* CONFIG_TQM5200 */

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for	*/
						/*  flash and SM501	*/

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*
 * USB stuff
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00002000	/* we're using Port 2	*/

/*
 * IDE/ATA stuff Supports IDE harddisk
 */
#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	  not supported */
#undef	CONFIG_IDE_LED			/* LED for ide	  not supported */

#define CONFIG_IDE_RESET		/* reset for ide      supported */
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers */
#define CONFIG_SYS_ATA_STRIDE		4

#endif /* __CONFIG_H */
Commit	Line	Data
6ca24c64	1	/*
	2	* -- Version 1.1 --
	3	*
	4	* (C) Copyright 2003-2005
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* (C) Copyright 2004-2005
	8	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	9	*
	10	* (C) Copyright 2005
	11	* Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
	12	*
	13	* History:
	14	* 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
	15	*
3765b3e7	16	* SPDX-License-Identifier: GPL-2.0+
6ca24c64	17	*/
	18
	19	#ifndef __CONFIG_H
	20	#define __CONFIG_H
	21
	22	/*
	23	* High Level Configuration Options
	24	*/
b2a6dfe4	25	#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
6ca24c64	26	#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
6ca24c64	27
610cf367 WD	28	#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
	29	#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
	30	#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
6ca24c64	31	#define CONFIG_BC3450_USB 1 /* + USB support */
	32	# define CONFIG_FAT 1 /* + FAT support */
	33	# define CONFIG_EXT2 1 /* + EXT2 support */
	34	#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
	35	#undef CONFIG_BC3450_CAN /* + CAN transceiver */
	36	#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
610cf367 WD	37	#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
610cf367 WD	38	#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
6ca24c64	39	#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
	40	#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
	41
2ae18241 WD	42	/*
	43	* Valid values for CONFIG_SYS_TEXT_BASE are:
	44	* 0xFC000000 boot low (standard configuration with room for
	45	* max 64 MByte Flash ROM)
	46	* 0x00100000 boot from RAM (for testing only)
	47	*/
	48	#ifndef CONFIG_SYS_TEXT_BASE
	49	#define CONFIG_SYS_TEXT_BASE 0xFC000000
	50	#endif
	51
6d0f6bcf	52	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
6ca24c64	53
31d82672 BB	54	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	55
6ca24c64	56	/*
	57	* Serial console configuration
	58	*/
	59	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	60	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	61	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
6ca24c64	62
	63	/*
	64	* AT-PS/2 Multiplexer
	65	*/
	66	#ifdef CONFIG_BC3450_PS2
	67	# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
	68	# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
	69	# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
6d0f6bcf	70	# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
6ca24c64	71	# define CONFIG_BOARD_EARLY_INIT_R
	72	#endif /* CONFIG_BC3450_PS2 */
	73
	74	/*
	75	* PCI Mapping:
	76	* 0x40000000 - 0x4fffffff - PCI Memory
	77	* 0x50000000 - 0x50ffffff - PCI IO Space
	78	*/
	79	# define CONFIG_PCI 1
	80	# define CONFIG_PCI_PNP 1
610cf367	81	/* #define CONFIG_PCI_SCAN_SHOW 1 */
f33fca22	82	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
6ca24c64	83
	84	#define CONFIG_PCI_MEM_BUS 0x40000000
	85	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	86	#define CONFIG_PCI_MEM_SIZE 0x10000000
	87
	88	#define CONFIG_PCI_IO_BUS 0x50000000
	89	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	90	#define CONFIG_PCI_IO_SIZE 0x01000000
	91
6ca24c64	92	/#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled /
6d0f6bcf	93	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
6ca24c64	94	#define CONFIG_NS8382X 1
6ca24c64	95
6ca24c64	96	/*
	97	* Video console
	98	*/
	99	# define CONFIG_VIDEO
	100	# define CONFIG_VIDEO_SM501
	101	# define CONFIG_VIDEO_SM501_32BPP
	102	# define CONFIG_CFB_CONSOLE
	103	# define CONFIG_VIDEO_LOGO
	104	# define CONFIG_VGA_AS_SINGLE_DEVICE
	105	# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
	106	# define CONFIG_VIDEO_SW_CURSOR
	107	# define CONFIG_SPLASH_SCREEN
6d0f6bcf	108	# define CONFIG_SYS_CONSOLE_IS_IN_ENV
6ca24c64	109
610cf367 WD	110	/*
610cf367 WD	111	* Partitions
6ca24c64	112	*/
	113	#define CONFIG_MAC_PARTITION
	114	#define CONFIG_DOS_PARTITION
	115	#define CONFIG_ISO_PARTITION
	116
610cf367 WD	117	/*
610cf367 WD	118	* USB
6ca24c64	119	*/
	120	#ifdef CONFIG_BC3450_USB
	121	# define CONFIG_USB_OHCI
6ca24c64	122	# define CONFIG_USB_STORAGE
6ca24c64	123	#endif /* CONFIG_BC3450_USB */
6ca24c64	124
610cf367 WD	125	/*
610cf367 WD	126	* POST support
6ca24c64	127	*/
6d0f6bcf JCPV	128	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| \
	129	CONFIG_SYS_POST_CPU \| \
	130	CONFIG_SYS_POST_I2C)
6ca24c64	131
6ca24c64	132	#ifdef CONFIG_POST
6ca24c64	133	/* preserve space for the post_word at end of on-chip SRAM */
6ca24c64	134	# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
6ca24c64	135	#endif /* CONFIG_POST */
6ca24c64	136
de8b2a6e	137
11799434 JL	138	/*
	139	* BOOTP options
	140	*/
	141	#define CONFIG_BOOTP_BOOTFILESIZE
	142	#define CONFIG_BOOTP_BOOTPATH
	143	#define CONFIG_BOOTP_GATEWAY
	144	#define CONFIG_BOOTP_HOSTNAME
	145
	146
610cf367	147	/*
de8b2a6e	148	* Command line configuration.
6ca24c64	149	*/
de8b2a6e JL	150	#include <config_cmd_default.h>
	151
	152	#define CONFIG_CMD_ASKENV
	153	#define CONFIG_CMD_DATE
	154	#define CONFIG_CMD_DHCP
	155	#define CONFIG_CMD_ECHO
	156	#define CONFIG_CMD_EEPROM
	157	#define CONFIG_CMD_I2C
	158	#define CONFIG_CMD_JFFS2
	159	#define CONFIG_CMD_MII
	160	#define CONFIG_CMD_NFS
	161	#define CONFIG_CMD_PING
de8b2a6e JL	162	#define CONFIG_CMD_REGINFO
	163	#define CONFIG_CMD_SNTP
	164	#define CONFIG_CMD_BSP
	165
	166	#ifdef CONFIG_VIDEO
	167	#define CONFIG_CMD_BMP
	168	#endif
	169
6ca24c64	170	#ifdef CONFIG_BC3450_IDE
de8b2a6e JL	171	#define CONFIG_CMD_IDE
de8b2a6e JL	172	#endif
6ca24c64	173
de8b2a6e JL	174	#if defined(CONFIG_BC3450_IDE) \|\| defined(CONFIG_BC3450_USB)
	175	#ifdef CONFIG_FAT
	176	#define CONFIG_CMD_FAT
	177	#endif
6ca24c64	178
de8b2a6e JL	179	#ifdef CONFIG_EXT2
	180	#define CONFIG_CMD_EXT2
	181	#endif
	182	#endif
	183
	184	#ifdef CONFIG_BC3450_USB
	185	#define CONFIG_CMD_USB
	186	#endif
5728be38	187
de8b2a6e JL	188	#ifdef CONFIG_PCI
	189	#define CONFIG_CMD_PCI
	190	#endif
6ca24c64	191
af075ee9 JL	192	#ifdef CONFIG_POST
	193	#define CONFIG_CMD_DIAG
	194	#endif
	195
6ca24c64	196
610cf367	197	#define CONFIG_TIMESTAMP /* display image timestamps */
6ca24c64	198
14d0a02a	199	#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
6d0f6bcf	200	# define CONFIG_SYS_LOWBOOT 1
6ca24c64	201	#endif
	202
	203	/*
	204	* Autobooting
	205	*/
	206	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	207	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	208
	209	#define CONFIG_PREBOOT "echo;" \
32bf3d14	210	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
6ca24c64	211	"echo;"
	212
	213	#undef CONFIG_BOOTARGS
	214
	215	#define CONFIG_EXTRA_ENV_SETTINGS \
	216	"netdev=eth0\0" \
	217	"ipaddr=192.168.1.10\0" \
	218	"serverip=192.168.1.3\0" \
	219	"netmask=255.255.255.0\0" \
610cf367	220	"hostname=bc3450\0" \
6ca24c64	221	"rootpath=/opt/eldk/ppc_6xx\0" \
610cf367 WD	222	"kernel_addr=fc0a0000\0" \
610cf367 WD	223	"ramdisk_addr=fc1c0000\0" \
6ca24c64	224	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	225	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	226	"nfsroot=$(serverip):$(rootpath)\0" \
610cf367	227	"ideargs=setenv bootargs root=/dev/hda2 ro\0" \
6ca24c64	228	"addip=setenv bootargs $(bootargs) " \
	229	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	230	":$(hostname):$(netdev):off panic=1\0" \
	231	"addcons=setenv bootargs $(bootargs) " \
	232	"console=ttyS0,$(baudrate) console=tty0\0" \
	233	"flash_self=run ramargs addip addcons;" \
	234	"bootm $(kernel_addr) $(ramdisk_addr)\0" \
	235	"flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
	236	"net_nfs=tftp 200000 $(bootfile); " \
	237	"run nfsargs addip addcons; bootm\0" \
610cf367 WD	238	"ide_nfs=run nfsargs addip addcons; " \
	239	"disk 200000 0:1; bootm\0" \
	240	"ide_ide=run ideargs addip addcons; " \
	241	"disk 200000 0:1; bootm\0" \
6ca24c64	242	"usb_self=run usbload; run ramargs addip addcons; " \
	243	"bootm 200000 400000\0" \
	244	"usbload=usb reset; usb scan; usbboot 200000 0:1; " \
	245	"usbboot 400000 0:2\0" \
	246	"bootfile=uImage\0" \
	247	"load=tftp 200000 $(u-boot)\0" \
	248	"u-boot=u-boot.bin\0" \
	249	"update=protect off FC000000 FC05FFFF;" \
	250	"erase FC000000 FC05FFFF;" \
	251	"cp.b 200000 FC000000 $(filesize);" \
	252	"protect on FC000000 FC05FFFF\0" \
	253	""
	254
	255	#define CONFIG_BOOTCOMMAND "run flash_self"
	256
	257	/*
	258	* IPB Bus clocking configuration.
	259	*/
6d0f6bcf	260	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
6ca24c64	261
	262	/*
	263	* PCI Bus clocking configuration
	264	*
	265	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
6d0f6bcf	266	* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
c99512d6	267	* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
6ca24c64	268	*/
6d0f6bcf JCPV	269	#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
6d0f6bcf JCPV	270	# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
6ca24c64	271	#endif
	272
	273	/*
	274	* I2C configuration
	275	*/
	276	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	277	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
6ca24c64	278
	279	/*
	280	* I2C clock frequency
	281	*
	282	* Please notice, that the resulting clock frequency could differ from the
	283	* configured value. This is because the I2C clock is derived from system
	284	* clock over a frequency divider with only a few divider values. U-boot
6d0f6bcf	285	* calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
6ca24c64	286	* approximation allways lies below the configured value, never above.
6ca24c64	287	*/
6d0f6bcf JCPV	288	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	289	#define CONFIG_SYS_I2C_SLAVE 0x7F
6ca24c64	290
6ca24c64	291	/*
610cf367	292	* EEPROM configuration for I²C EEPROM M24C32
6ca24c64	293	* M24C64 should work also. For other EEPROMs config should be verified.
610cf367	294	*
6ca24c64	295	* The TQM5200 module may hold an EEPROM at address 0x50.
6ca24c64	296	*/
6d0f6bcf JCPV	297	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
	298	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	299	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	300	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
6ca24c64	301
	302	/*
	303	* RTC configuration
	304	*/
	305	#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
	306	# define CONFIG_RTC_M41T11 1
6d0f6bcf	307	# define CONFIG_SYS_I2C_RTC_ADDR 0x68
6ca24c64	308	#else
	309	# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
	310	# define CONFIG_BOARD_EARLY_INIT_R
	311	#endif
	312
	313	/*
	314	* Flash configuration
	315	*/
14d0a02a	316	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
6ca24c64	317
6ca24c64	318	/* use CFI flash driver if no module variant is spezified */
6d0f6bcf	319	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	320	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
6d0f6bcf JCPV	321	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
	322	#define CONFIG_SYS_FLASH_EMPTY_INFO
	323	#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
	324	#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
	325	#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
	326
	327	#if !defined(CONFIG_SYS_LOWBOOT)
	328	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
	329	#else /* CONFIG_SYS_LOWBOOT */
	330	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
	331	#endif /* CONFIG_SYS_LOWBOOT */
	332	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
6ca24c64	333	(= chip selects) */
6d0f6bcf JCPV	334	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	335	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
6ca24c64	336
6ca24c64	337	/* Dynamic MTD partition support */
68d7d651	338	#define CONFIG_CMD_MTDPARTS
942556a9 SR	339	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	340	#define CONFIG_FLASH_CFI_MTD
6ca24c64	341	#define MTDIDS_DEFAULT "nor0=TQM5200-0"
	342	#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
	343	"1408k(kernel)," \
	344	"2m(initrd)," \
	345	"4m(small-fs)," \
	346	"16m(big-fs)," \
	347	"8m(misc)"
	348
	349	/*
	350	* Environment settings
	351	*/
5a1aceb0	352	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	353	#define CONFIG_ENV_SIZE 0x10000
	354	#define CONFIG_ENV_SECT_SIZE 0x20000
	355	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	356	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
6ca24c64	357
	358	/*
	359	* Memory map
	360	*/
6d0f6bcf JCPV	361	#define CONFIG_SYS_MBAR 0xF0000000
	362	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	363	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
6ca24c64	364
6ca24c64	365	/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf	366	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
6ca24c64	367	#ifdef CONFIG_POST
6ca24c64	368	/* preserve space for the post_word at end of on-chip SRAM */
553f0982	369	# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
6ca24c64	370	#else
553f0982	371	# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
6ca24c64	372	#endif /CONFIG_POST/
6ca24c64	373
25ddd1fb	374	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	375	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6ca24c64	376
14d0a02a	377	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	378	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	379	# define CONFIG_SYS_RAMBOOT 1
6ca24c64	380	#endif
6ca24c64	381
6d0f6bcf JCPV	382	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
	383	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	384	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
6ca24c64	385
	386	/*
	387	* Ethernet configuration
	388	*
86321fc1	389	* Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
6ca24c64	390	*/
6ca24c64	391	#define CONFIG_MPC5xxx_FEC 1
86321fc1 BW	392	#define CONFIG_MPC5xxx_FEC_MII100
86321fc1 BW	393	#undef CONFIG_MPC5xxx_MII10
6ca24c64	394	#define CONFIG_PHY_ADDR 0x00
	395
	396	/*
	397	* GPIO configuration on BC3450
	398	*
610cf367 WD	399	* PSC1: UART1 (Service-UART) [0x xxxxxxx4]
	400	* PSC2: UART2 [0x xxxxxx4x]
	401	* or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
	402	* PSC3: USB2 [0x xxxxx1xx]
	403	* USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
	404	* (this has to match
	405	* CONFIG_USB_CONFIG which is
	406	* used by usb_ohci.c to set
	407	* the USB ports)
	408	* Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
	409	* (this is reset to '5'
	410	* in FEC driver: fec.c)
	411	* PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
	412	* ATA/CS: ??? [0x x1xxxxxx]
	413	* FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
6ca24c64	414	* CS1: Use Pin gpio_wkup_6 as second
610cf367	415	* SDRAM chip select (mem_cs1)
6ca24c64	416	* Timer: CAN2 / SPI
610cf367	417	* I2C: CAN1 / I²C2 [0x bxxxxxxx]
6ca24c64	418	*/
6ca24c64	419	#ifdef CONFIG_BC3450_AC97
6d0f6bcf	420	# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
6ca24c64	421	#else /* PSC2=UART2 */
6d0f6bcf	422	# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
6ca24c64	423	#endif
	424
	425	/*
	426	* Miscellaneous configurable options
	427	*/
6d0f6bcf	428	#define CONFIG_SYS_LONGHELP /* undef to save memory */
de8b2a6e	429	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	430	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
6ca24c64	431	#else
6d0f6bcf	432	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6ca24c64	433	#endif
6d0f6bcf JCPV	434	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	435	#define CONFIG_SYS_MAXARGS 16 /* max no of command args */
	436	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
6ca24c64	437
6d0f6bcf	438	#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
6ca24c64	439	/* more extensive mem test */
6ca24c64	440
6d0f6bcf JCPV	441	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	442	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
6ca24c64	443
6d0f6bcf	444	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6ca24c64	445
6d0f6bcf	446	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
de8b2a6e	447	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	448	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
de8b2a6e JL	449	#endif
de8b2a6e JL	450
6ca24c64	451	/*
11799434	452	* Enable loopw command.
6ca24c64	453	*/
	454	#define CONFIG_LOOPW
	455
	456	/*
	457	* Various low-level settings
	458	*/
fd428c05 DZ	459	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
fd428c05 DZ	460	#define CONFIG_SYS_HID0_FINAL HID0_ICE
6ca24c64	461
6d0f6bcf JCPV	462	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	463	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	464	#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
	465	# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
6ca24c64	466	#else
6d0f6bcf	467	# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
6ca24c64	468	#endif
6d0f6bcf JCPV	469	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	470	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
6ca24c64	471
	472	/* automatic configuration of chip selects */
	473	#ifdef CONFIG_TQM5200
	474	# define CONFIG_LAST_STAGE_INIT
	475	#endif /* CONFIG_TQM5200 */
	476
	477	/*
	478	* SRAM - Do not map below 2 GB in address space, because this area is used
	479	* for SDRAM autosizing.
	480	*/
	481	#ifdef CONFIG_TQM5200
6d0f6bcf JCPV	482	# define CONFIG_SYS_CS2_START 0xE5000000
	483	# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
	484	# define CONFIG_SYS_CS2_CFG 0x0004D930
6ca24c64	485	#endif /* CONFIG_TQM5200 */
	486
	487	/*
	488	* Grafic controller - Do not map below 2 GB in address space, because this
	489	* area is used for SDRAM autosizing.
	490	*/
	491	#ifdef CONFIG_TQM5200
	492	# define SM501_FB_BASE 0xE0000000
6d0f6bcf JCPV	493	# define CONFIG_SYS_CS1_START (SM501_FB_BASE)
	494	# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
	495	# define CONFIG_SYS_CS1_CFG 0x8F48FF70
	496	# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
6ca24c64	497	#endif /* CONFIG_TQM5200 */
6ca24c64	498
6d0f6bcf JCPV	499	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	500	#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
6ca24c64	501	/* flash and SM501 */
6ca24c64	502
6d0f6bcf	503	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
6ca24c64	504
	505	/*
	506	* USB stuff
	507	*/
	508	#define CONFIG_USB_CLOCK 0x0001BBBB
610cf367	509	#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
6ca24c64	510
	511	/*
	512	* IDE/ATA stuff Supports IDE harddisk
	513	*/
	514	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	515
610cf367 WD	516	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
610cf367 WD	517	#undef CONFIG_IDE_LED /* LED for ide not supported */
6ca24c64	518
610cf367	519	#define CONFIG_IDE_RESET /* reset for ide supported */
6ca24c64	520	#define CONFIG_IDE_PREINIT
6ca24c64	521
6d0f6bcf JCPV	522	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	523	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
6ca24c64	524
6d0f6bcf	525	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
6ca24c64	526
6d0f6bcf	527	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
6ca24c64	528
6ca24c64	529	/* Offset for data I/O */
6d0f6bcf	530	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
6ca24c64	531
6ca24c64	532	/* Offset for normal register accesses */
6d0f6bcf	533	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
6ca24c64	534
6ca24c64	535	/* Offset for alternate registers */
6d0f6bcf	536	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
6ca24c64	537
6ca24c64	538	/* Interval between registers */
6d0f6bcf	539	#define CONFIG_SYS_ATA_STRIDE 4
6ca24c64	540
6ca24c64	541	#endif /* __CONFIG_H */