[people/ms/u-boot.git] / include / configs / BSC9131RDB.h

/*
 * Copyright 2011-2012 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * BSC9131 RDB board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_NAND_FSL_IFC

#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE		0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS	0x110bfffc
#endif

#ifdef CONFIG_NAND
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"

#define CONFIG_SYS_TEXT_BASE		0x00201000
#define CONFIG_SPL_TEXT_BASE		0xFFFFE000
#define CONFIG_SPL_MAX_SIZE		8192
#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
#define CONFIG_SPL_RELOC_STACK		0x00100000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
#define CONFIG_SYS_LDSCRIPT	"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
#endif

/* High Level Configuration Options */

#define CONFIG_TSEC_ENET
#define CONFIG_ENV_OVERWRITE

#define CONFIG_DDR_CLK_FREQ	66666666 /* DDRCLK on 9131 RDB */
#if defined(CONFIG_SYS_CLK_100)
#define CONFIG_SYS_CLK_FREQ    100000000 /* SYSCLK for 9131 RDB */
#else
#define CONFIG_SYS_CLK_FREQ	66666666 /* SYSCLK for 9131 RDB */
#endif

#define CONFIG_HWCONFIG
/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* enable branch predition */

#define CONFIG_SYS_MEMTEST_START	0x01000000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x01ffffff

/* DDR Setup */
#undef CONFIG_SYS_DDR_RAW_TIMING
#undef CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM		0
#define SPD_EEPROM_ADDRESS		0x52 /* I2C access */

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#ifndef __ASSEMBLY__
extern unsigned long get_sdram_size(void);
#endif
#define CONFIG_SYS_SDRAM_SIZE		get_sdram_size() /* DDR size */
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	1

#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003f
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014302
#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000

#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
#define CONFIG_SYS_DDR_INIT_ADDR	0x00000000
#define CONFIG_SYS_DDR_INIT_EXT_ADDR	0x00000000
#define CONFIG_SYS_DDR_MODE_CONTROL	0x00000000

#define CONFIG_SYS_DDR_ZQ_CONTROL	0x89080600
#define CONFIG_SYS_DDR_SR_CNTR		0x00000000
#define CONFIG_SYS_DDR_RCW_1		0x00000000
#define CONFIG_SYS_DDR_RCW_2		0x00000000
#define CONFIG_SYS_DDR_CONTROL		0xC70C0000	/* Type = DDR3	*/
#define CONFIG_SYS_DDR_CONTROL_2	0x24401000
#define CONFIG_SYS_DDR_TIMING_4		0x00000001
#define CONFIG_SYS_DDR_TIMING_5		0x02401400

#define CONFIG_SYS_DDR_TIMING_3_800		0x00030000
#define CONFIG_SYS_DDR_TIMING_0_800		0x00110104
#define CONFIG_SYS_DDR_TIMING_1_800		0x6f6b8644
#define CONFIG_SYS_DDR_TIMING_2_800		0x0fa888cf
#define CONFIG_SYS_DDR_CLK_CTRL_800		0x03000000
#define CONFIG_SYS_DDR_MODE_1_800		0x00441420
#define CONFIG_SYS_DDR_MODE_2_800		0x8000c000
#define CONFIG_SYS_DDR_INTERVAL_800		0x0c300100
#define CONFIG_SYS_DDR_WRLVL_CONTROL_800	0x8675f608

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
/* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR	CONFIG_SYS_CCSRBAR_DEFAULT
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR_DEFAULT

#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses */
							/* CONFIG_SYS_IMMR */
/* DSP CCSRBAR */
#define CONFIG_SYS_FSL_DSP_CCSRBAR	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS	CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT

/*
 * Memory map
 *
 * 0x0000_0000	0x3FFF_FFFF	DDR			1G cacheable
 * 0x8800_0000	0x8810_0000	IFC internal SRAM		1M
 * 0xB000_0000	0xB0FF_FFFF	DSP core M2 memory	16M
 * 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
 * 0xC1F0_0000	0xC1F3_FFFF	PA L2 SRAM Region 0	256K
 * 0xC1F8_0000	0xC1F9_FFFF	PA L2 SRAM Region 1	128K
 * 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
 * 0xFF60_0000	0xFF6F_FFFF	DSP CCSR		1M
 * 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
 * 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND flash buffer	8M
 *
 */

/*
 * IFC Definitions
 */

/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE		0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8	/* Port Size = 8 bit*/ \
				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)

#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
				| CSOR_NAND_RAL_2	/* RAL = 2Byes */ \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

/* NAND Flash Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x03)  \
					| FTIM0_NAND_TWP(0x05)   \
					| FTIM0_NAND_TWCHT(0x02) \
					| FTIM0_NAND_TWH(0x04))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x1C) \
					| FTIM1_NAND_TWBE(0x1E) \
					| FTIM1_NAND_TRR(0x07)  \
					| FTIM1_NAND_TRP(0x05))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x08)  \
					| FTIM2_NAND_TREH(0x04) \
					| FTIM2_NAND_TWHRE(0x11))
#define CONFIG_SYS_NAND_FTIM3		FTIM3_NAND_TWW(0x04)

#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)

#define CONFIG_SYS_NAND_DDR_LAW		11

/* Set up IFC registers for boot location NAND */
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* stack in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000/* End of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
						- GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc*/

/* Serial Port */
#define CONFIG_CONS_INDEX	1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000

/* I2C EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5

/* eSPI - Enhanced SPI */
#ifdef CONFIG_FSL_ESPI
#define CONFIG_SF_DEFAULT_SPEED		10000000
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
#endif

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII			/* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"eTSEC2"

#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		3

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX		0

#define TSEC2_PHYIDX		0

#define CONFIG_ETHPRIME		"eTSEC1"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_SPI_BUS	0
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MAX_HZ	10000000
#define CONFIG_ENV_SPI_MODE	0
#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_SIZE		0x2000
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET	((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO		/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate change */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

#ifdef CONFIG_USB_EHCI_HCD
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_HAS_FSL_DR_USB
#endif

/*
 * Dynamic MTD Partition support with mtdparts
 */
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
			"8m(kernel),512k(dtb),-(fs)"

/*
 * Environment Configuration
 */

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#endif

#define CONFIG_HOSTNAME		BSC9131rdb
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"uboot=" CONFIG_UBOOTPATH "\0"				\
	"loadaddr=1000000\0"			\
	"bootfile=uImage\0"	\
	"consoledev=ttyS0\0"				\
	"ramdiskaddr=2000000\0"			\
	"ramdiskfile=rootfs.ext2.gz.uboot\0"		\
	"fdtaddr=1e00000\0"				\
	"fdtfile=bsc9131rdb.dtb\0"		\
	"bdev=sda1\0"	\
	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"	\
	"bootm_size=0x37000000\0"	\
	"othbootargs=ramdisk_size=600000 " \
	"default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
	"usbext2boot=setenv bootargs root=/dev/ram rw "	\
	"console=$consoledev,$baudrate $othbootargs; "	\
	"usb start;"			\
	"ext2load usb 0:4 $loadaddr $bootfile;"		\
	"ext2load usb 0:4 $fdtaddr $fdtfile;"	\
	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"	\
	"bootm $loadaddr $ramdiskaddr $fdtaddr\0"	\

#define CONFIG_RAMBOOTCOMMAND		\
	"setenv bootargs root=/dev/ram rw "	\
	"console=$consoledev,$baudrate $othbootargs; "	\
	"tftp $ramdiskaddr $ramdiskfile;"	\
	"tftp $loadaddr $bootfile;"		\
	"tftp $fdtaddr $fdtfile;"		\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
7530d341 PK	1	/*
	2	* Copyright 2011-2012 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
7530d341 PK	5	*/
	6
	7	/*
	8	* BSC9131 RDB board configuration file
	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
7530d341	14	#define CONFIG_NAND_FSL_IFC
7530d341 PK	15
	16	#ifdef CONFIG_SPIFLASH
	17	#define CONFIG_RAMBOOT_SPIFLASH
	18	#define CONFIG_SYS_RAMBOOT
	19	#define CONFIG_SYS_EXTRA_ENV_RELOC
	20	#define CONFIG_SYS_TEXT_BASE 0x11000000
e222b1f3	21	#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
7530d341 PK	22	#endif
7530d341 PK	23
f1593269	24	#ifdef CONFIG_NAND
f1593269	25	#define CONFIG_SPL_INIT_MINIMAL
fbe76ae4	26	#define CONFIG_SPL_NAND_BOOT
f1593269 PK	27	#define CONFIG_SPL_FLUSH_IMAGE
	28	#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	29
	30	#define CONFIG_SYS_TEXT_BASE 0x00201000
	31	#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
	32	#define CONFIG_SPL_MAX_SIZE 8192
	33	#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
	34	#define CONFIG_SPL_RELOC_STACK 0x00100000
e222b1f3	35	#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
f1593269 PK	36	#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
	37	#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
	38	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
	39	#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
7530d341 PK	40	#endif
7530d341 PK	41
f1593269 PK	42	#ifdef CONFIG_SPL_BUILD
	43	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	44	#else
	45	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	46	#endif
	47
7530d341	48	/* High Level Configuration Options */
7530d341	49
7530d341 PK	50	#define CONFIG_TSEC_ENET
	51	#define CONFIG_ENV_OVERWRITE
	52
	53	#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
087cf44f PJ	54	#if defined(CONFIG_SYS_CLK_100)
	55	#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
	56	#else
7530d341	57	#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
087cf44f	58	#endif
7530d341 PK	59
	60	#define CONFIG_HWCONFIG
	61	/*
	62	* These can be toggled for performance analysis, otherwise use default.
	63	*/
	64	#define CONFIG_L2_CACHE /* toggle L2 cache */
	65	#define CONFIG_BTB /* enable branch predition */
	66
	67	#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
	68	#define CONFIG_SYS_MEMTEST_END 0x01ffffff
	69
	70	/* DDR Setup */
7530d341 PK	71	#undef CONFIG_SYS_DDR_RAW_TIMING
	72	#undef CONFIG_DDR_SPD
	73	#define CONFIG_SYS_SPD_BUS_NUM 0
	74	#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
	75
	76	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	77
	78	#ifndef __ASSEMBLY__
	79	extern unsigned long get_sdram_size(void);
	80	#endif
	81	#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
	82	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	83	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	84
7530d341 PK	85	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	86	#define CONFIG_CHIP_SELECTS_PER_CTRL 1
	87
	88	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
	89	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
	90	#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
	91
	92	#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
	93	#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
	94	#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
	95	#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
	96
	97	#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
	98	#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
	99	#define CONFIG_SYS_DDR_RCW_1 0x00000000
	100	#define CONFIG_SYS_DDR_RCW_2 0x00000000
	101	#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
	102	#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
	103	#define CONFIG_SYS_DDR_TIMING_4 0x00000001
	104	#define CONFIG_SYS_DDR_TIMING_5 0x02401400
	105
	106	#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
	107	#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
	108	#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
	109	#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
	110	#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
	111	#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
	112	#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
	113	#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
	114	#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
	115
	116	/*
	117	* Base addresses -- Note these are effective addresses where the
	118	* actual resources get mapped (not physical addresses)
	119	*/
	120	/* relocated CCSRBAR */
	121	#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
	122	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
	123
	124	#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
	125	/* CONFIG_SYS_IMMR */
765b0bdb PJ	126	/* DSP CCSRBAR */
	127	#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
	128	#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
7530d341 PK	129
	130	/*
	131	* Memory map
	132	*
	133	* 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
	134	* 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
765b0bdb	135	* 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
7530d341 PK	136	* 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
	137	* 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
	138	* 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
	139	* 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
765b0bdb	140	* 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
7530d341 PK	141	* 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
	142	* 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
	143	*
	144	*/
	145
	146	/*
	147	* IFC Definitions
	148	*/
7530d341 PK	149
	150	/* NAND Flash on IFC */
	151	#define CONFIG_SYS_NAND_BASE 0xff800000
	152	#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
	153
	154	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	155	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
	156	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	157	\| CSPR_V)
	158	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	159
	160	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	161	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	162	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	163	\| CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
	164	\| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
	165	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
	166	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	167
	168	/* NAND Flash Timing Params */
4544fd29 PK	169	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
	170	\| FTIM0_NAND_TWP(0x05) \
	171	\| FTIM0_NAND_TWCHT(0x02) \
7530d341	172	\| FTIM0_NAND_TWH(0x04))
4544fd29 PK	173	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
	174	\| FTIM1_NAND_TWBE(0x1E) \
	175	\| FTIM1_NAND_TRR(0x07) \
7530d341 PK	176	\| FTIM1_NAND_TRP(0x05))
	177	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
	178	\| FTIM2_NAND_TREH(0x04) \
4544fd29 PK	179	\| FTIM2_NAND_TWHRE(0x11))
4544fd29 PK	180	#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
7530d341 PK	181
	182	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	183	#define CONFIG_SYS_MAX_NAND_DEVICE 1
7530d341 PK	184	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	185
	186	#define CONFIG_SYS_NAND_DDR_LAW 11
	187
	188	/* Set up IFC registers for boot location NAND */
	189	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	190	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	191	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	192	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	193	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	194	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	195	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
	196
7530d341 PK	197	#define CONFIG_SYS_INIT_RAM_LOCK
7530d341 PK	198	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
b39d1213	199	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
7530d341	200
b39d1213	201	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
7530d341 PK	202	- GENERATED_GBL_DATA_SIZE)
	203	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	204
9307cbab	205	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
7530d341 PK	206	#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
	207
	208	/* Serial Port */
	209	#define CONFIG_CONS_INDEX 1
	210	#undef CONFIG_SERIAL_SOFTWARE_FIFO
7530d341 PK	211	#define CONFIG_SYS_NS16550_SERIAL
	212	#define CONFIG_SYS_NS16550_REG_SIZE 1
	213	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
f1593269 PK	214	#ifdef CONFIG_SPL_BUILD
	215	#define CONFIG_NS16550_MIN_FUNCTIONS
	216	#endif
7530d341	217
7530d341 PK	218	#define CONFIG_SYS_BAUDRATE_TABLE \
	219	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	220
	221	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	222
00f792e0 HS	223	#define CONFIG_SYS_I2C
	224	#define CONFIG_SYS_I2C_FSL
	225	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	226	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	227	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
7530d341 PK	228
7530d341 PK	229	/* I2C EEPROM */
7530d341 PK	230	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	231	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	232	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
	233
7530d341 PK	234	/* eSPI - Enhanced SPI */
7530d341 PK	235	#ifdef CONFIG_FSL_ESPI
7530d341 PK	236	#define CONFIG_SF_DEFAULT_SPEED 10000000
	237	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	238	#endif
	239
	240	#if defined(CONFIG_TSEC_ENET)
	241
	242	#define CONFIG_MII /* MII PHY management */
	243	#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
	244	#define CONFIG_TSEC1 1
	245	#define CONFIG_TSEC1_NAME "eTSEC1"
	246	#define CONFIG_TSEC2 1
	247	#define CONFIG_TSEC2_NAME "eTSEC2"
	248
	249	#define TSEC1_PHY_ADDR 0
	250	#define TSEC2_PHY_ADDR 3
	251
	252	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	253	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	254
	255	#define TSEC1_PHYIDX 0
	256
	257	#define TSEC2_PHYIDX 0
	258
	259	#define CONFIG_ETHPRIME "eTSEC1"
	260
7530d341 PK	261	#endif /* CONFIG_TSEC_ENET */
	262
	263	/*
	264	* Environment
	265	*/
7530d341	266	#if defined(CONFIG_RAMBOOT_SPIFLASH)
7530d341 PK	267	#define CONFIG_ENV_SPI_BUS 0
	268	#define CONFIG_ENV_SPI_CS 0
	269	#define CONFIG_ENV_SPI_MAX_HZ 10000000
	270	#define CONFIG_ENV_SPI_MODE 0
	271	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
	272	#define CONFIG_ENV_SECT_SIZE 0x10000
	273	#define CONFIG_ENV_SIZE 0x2000
f1593269	274	#elif defined(CONFIG_NAND)
f1593269 PK	275	#define CONFIG_SYS_EXTRA_ENV_RELOC
f1593269 PK	276	#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
e222b1f3	277	#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
f1593269 PK	278	#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
f1593269 PK	279	#elif defined(CONFIG_SYS_RAMBOOT)
7530d341	280	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
f1593269	281	#define CONFIG_ENV_SIZE 0x2000
7530d341 PK	282	#endif
	283
	284	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	285	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
	286
7530d341 PK	287	/*
	288	* Miscellaneous configurable options
	289	*/
	290	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	291	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
	292	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
	293	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
7530d341 PK	294
	295	#if defined(CONFIG_CMD_KGDB)
	296	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	297	#else
	298	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	299	#endif
7530d341	300	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
7530d341 PK	301
	302	/*
	303	* For booting Linux, the board info and command line data
	304	* have to be in the first 64 MB of memory, since this is
	305	* the maximum mapped by the Linux kernel during initialization.
	306	*/
	307	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
	308	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	309
	310	#if defined(CONFIG_CMD_KGDB)
	311	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
7530d341 PK	312	#endif
7530d341 PK	313
8850c5d5	314	#ifdef CONFIG_USB_EHCI_HCD
7530d341 PK	315	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
7530d341 PK	316	#define CONFIG_USB_EHCI_FSL
7530d341 PK	317	#define CONFIG_HAS_FSL_DR_USB
	318	#endif
	319
7ac1a24a AK	320	/*
	321	* Dynamic MTD Partition support with mtdparts
	322	*/
	323	#define CONFIG_MTD_DEVICE
	324	#define CONFIG_MTD_PARTITIONS
7ac1a24a AK	325	#define MTDIDS_DEFAULT "nand0=ff800000.flash,"
	326	#define MTDPARTS_DEFAULT "mtdparts=ff800000.flash:1m(uboot)," \
	327	"8m(kernel),512k(dtb),-(fs)"
7ac1a24a	328
7530d341 PK	329	/*
	330	* Environment Configuration
	331	*/
	332
	333	#if defined(CONFIG_TSEC_ENET)
	334	#define CONFIG_HAS_ETH0
	335	#endif
	336
	337	#define CONFIG_HOSTNAME BSC9131rdb
	338	#define CONFIG_ROOTPATH "/opt/nfsroot"
	339	#define CONFIG_BOOTFILE "uImage"
	340	#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
	341
7530d341 PK	342	#define CONFIG_EXTRA_ENV_SETTINGS \
	343	"netdev=eth0\0" \
	344	"uboot=" CONFIG_UBOOTPATH "\0" \
	345	"loadaddr=1000000\0" \
	346	"bootfile=uImage\0" \
	347	"consoledev=ttyS0\0" \
	348	"ramdiskaddr=2000000\0" \
	349	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
b24a4f62	350	"fdtaddr=1e00000\0" \
7530d341 PK	351	"fdtfile=bsc9131rdb.dtb\0" \
	352	"bdev=sda1\0" \
	353	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
1d2949ae PJ	354	"bootm_size=0x37000000\0" \
	355	"othbootargs=ramdisk_size=600000 " \
	356	"default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
7530d341 PK	357	"usbext2boot=setenv bootargs root=/dev/ram rw " \
	358	"console=$consoledev,$baudrate $othbootargs; " \
	359	"usb start;" \
	360	"ext2load usb 0:4 $loadaddr $bootfile;" \
	361	"ext2load usb 0:4 $fdtaddr $fdtfile;" \
	362	"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
	363	"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
	364
	365	#define CONFIG_RAMBOOTCOMMAND \
	366	"setenv bootargs root=/dev/ram rw " \
	367	"console=$consoledev,$baudrate $othbootargs; " \
	368	"tftp $ramdiskaddr $ramdiskfile;" \
	369	"tftp $loadaddr $bootfile;" \
	370	"tftp $fdtaddr $fdtfile;" \
	371	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	372
	373	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	374
	375	#endif /* __CONFIG_H */