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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / include / configs / CMS700.h
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1/*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * CMS700.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_VOM405 1 /* ...on a VOM405 board */
39
40#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
42
43#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
44
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
47
48#undef CONFIG_BOOTARGS
49#undef CONFIG_BOOTCOMMAND
50
51#define CONFIG_PREBOOT /* enable preboot variable */
52
6d0f6bcf 53#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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54
55#define CONFIG_NET_MULTI 1
56#undef CONFIG_HAS_ETH1
57
58#define CONFIG_MII 1 /* MII PHY management */
59#define CONFIG_PHY_ADDR 0 /* PHY address */
60#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
61#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
62
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63/*
64 * BOOTP options
65 */
66#define CONFIG_BOOTP_SUBNETMASK
67#define CONFIG_BOOTP_GATEWAY
68#define CONFIG_BOOTP_HOSTNAME
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_DNS
71#define CONFIG_BOOTP_DNS2
72#define CONFIG_BOOTP_SEND_HOSTNAME
73
feaedfcf 74
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75/*
76 * Command line configuration.
77 */
78#include <config_cmd_default.h>
79
80#define CONFIG_CMD_DHCP
81#define CONFIG_CMD_BSP
82#define CONFIG_CMD_PCI
83#define CONFIG_CMD_IRQ
84#define CONFIG_CMD_ELF
85#define CONFIG_CMD_NAND
86#define CONFIG_CMD_I2C
87#define CONFIG_CMD_DATE
88#define CONFIG_CMD_MII
89#define CONFIG_CMD_PING
90#define CONFIG_CMD_EEPROM
91
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92
93#undef CONFIG_WATCHDOG /* watchdog disabled */
94
95#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
96
97#undef CONFIG_PRAM /* no "protected RAM" */
98
99/*
100 * Miscellaneous configurable options
101 */
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102#define CONFIG_SYS_LONGHELP /* undef to save memory */
103#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
feaedfcf 104
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105#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
106#ifdef CONFIG_SYS_HUSH_PARSER
107#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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108#endif
109
49cf7e8e 110#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 111#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
feaedfcf 112#else
6d0f6bcf 113#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
feaedfcf 114#endif
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115#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
116#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
117#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
feaedfcf 118
6d0f6bcf 119#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
feaedfcf 120
6d0f6bcf 121#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
feaedfcf 122
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123#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
124#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
feaedfcf 125
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126#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
127#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
128#define CONFIG_SYS_BASE_BAUD 691200
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129#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
130
131/* The following table includes the supported baudrates */
6d0f6bcf 132#define CONFIG_SYS_BAUDRATE_TABLE \
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133 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
134 57600, 115200, 230400, 460800, 921600 }
135
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136#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
137#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
feaedfcf 138
6d0f6bcf 139#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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140
141#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
142
143#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
144
6d0f6bcf 145#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
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146
147/*-----------------------------------------------------------------------
148 * RTC stuff
149 *-----------------------------------------------------------------------
150 */
151#define CONFIG_RTC_DS1337
6d0f6bcf 152#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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153
154/*-----------------------------------------------------------------------
155 * NAND-FLASH stuff
156 *-----------------------------------------------------------------------
157 */
6d0f6bcf 158#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
bd84ee4c 159#define NAND_MAX_CHIPS 1
6d0f6bcf 160#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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161#define NAND_BIG_DELAY_US 25
162
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163#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
164#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
165#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
166#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
feaedfcf 167
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168#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
169#define CONFIG_SYS_NAND_QUIET 1
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170
171/*-----------------------------------------------------------------------
172 * PCI stuff
173 *-----------------------------------------------------------------------
174 */
175#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
176#define PCI_HOST_FORCE 1 /* configure as pci host */
177#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
178
179#define CONFIG_PCI /* include pci support */
180#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
181#undef CONFIG_PCI_PNP /* do pci plug-and-play */
182 /* resource configuration */
183
184#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
185
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186#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
187#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
188#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
189#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
190#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
191#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
192#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
193#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
194#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
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195
196/*
197 * For booting Linux, the board info and command line data
198 * have to be in the first 8 MB of memory, since this is
199 * the maximum mapped by the Linux kernel during initialization.
200 */
6d0f6bcf 201#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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202/*-----------------------------------------------------------------------
203 * FLASH organization
204 */
205#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
206
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207#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
208#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
feaedfcf 209
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210#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
211#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
feaedfcf 212
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213#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
214#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
215#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
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216/*
217 * The following defines are added for buggy IOP480 byte interface.
218 * All other boards should use the standard values (CPCI405 etc.)
219 */
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220#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
221#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
222#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
feaedfcf 223
6d0f6bcf 224#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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225
226#if 0 /* test-only */
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227#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
228#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
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229#endif
230
231/*-----------------------------------------------------------------------
232 * Start addresses for the final memory configuration
233 * (Set up by the startup code)
6d0f6bcf 234 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
feaedfcf 235 */
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236#define CONFIG_SYS_SDRAM_BASE 0x00000000
237#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
238#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
239#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
240#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
241
242#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
243# define CONFIG_SYS_RAMBOOT 1
feaedfcf 244#else
6d0f6bcf 245# undef CONFIG_SYS_RAMBOOT
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246#endif
247
248/*-----------------------------------------------------------------------
249 * Environment Variable setup
250 */
bb1f8b4f 251#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
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252#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
253#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
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254 /* total size of a CAT24WC16 is 2048 bytes */
255
256/*-----------------------------------------------------------------------
257 * I2C EEPROM (CAT24WC16) for environment
258 */
259#define CONFIG_HARD_I2C /* I2c with hardware support */
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260#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
261#define CONFIG_SYS_I2C_SLAVE 0x7F
feaedfcf 262
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263#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
264#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
feaedfcf 265/* mask of address bits that overflow into the "EEPROM chip address" */
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266#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
267#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
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268 /* 16 byte page write mode using*/
269 /* last 4 bits of the address */
6d0f6bcf 270#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
feaedfcf 271
6d0f6bcf 272#define CONFIG_SYS_EEPROM_WREN 1
feaedfcf 273
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274/*-----------------------------------------------------------------------
275 * External Bus Controller (EBC) Setup
276 */
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277#define CONFIG_SYS_PLD_BASE 0xf0000000
278#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
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279
280/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
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281#define CONFIG_SYS_EBC_PB0AP 0x92015480
282#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
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283
284/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
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285#define CONFIG_SYS_EBC_PB1AP 0x92015480
286#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
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287
288/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
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289#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
290#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
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291
292/*-----------------------------------------------------------------------
293 * FPGA stuff
294 */
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295#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
296#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
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297
298/* FPGA program pin configuration */
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299#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
300#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
301#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
302#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
303#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
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304
305/*-----------------------------------------------------------------------
306 * Definitions for initial stack pointer and data area (in data cache)
307 */
308/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
6d0f6bcf 309#define CONFIG_SYS_TEMP_STACK_OCM 1
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310
311/* On Chip Memory location */
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312#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
313#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
314#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
315#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
feaedfcf 316
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317#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
318#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
319#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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320
321/*-----------------------------------------------------------------------
322 * Definitions for GPIO setup (PPC405EP specific)
323 *
324 * GPIO0[0] - External Bus Controller BLAST output
325 * GPIO0[1-9] - Instruction trace outputs -> GPIO
326 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
327 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
328 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
329 * GPIO0[24-27] - UART0 control signal inputs/outputs
330 * GPIO0[28-29] - UART1 data signal input/output
331 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
332 */
333/* GPIO Input: OSR=00, ISR=00, TSR=00, TCR=0 */
334/* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */
335/* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
336/* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
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337#define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */
338#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */
339#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */
340#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */
341#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */
342#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */
343#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */
344
345#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
346#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */
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347
348/*
349 * Internal Definitions
350 *
351 * Boot Flags
352 */
353#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
354#define BOOTFLAG_WARM 0x02 /* Software reboot */
355
356/*
357 * Default speed selection (cpu_plb_opb_ebc) in mhz.
358 * This value will be set if iic boot eprom is disabled.
359 */
360#if 0
361#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
362#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
363#endif
364#if 0
365#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
366#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
367#endif
368#if 1
369#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
370#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
371#endif
372
373#endif /* __CONFIG_H */