[people/ms/u-boot.git] / include / configs / CPCI405AB.h

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_CPCI405		1	/* ...on a CPCI405 board	*/
#define CONFIG_CPCI405_VER2	1	/* ...version 2			*/
#define CONFIG_CPCI405AB	1	/* ...and special AB version	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	 1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#undef	CONFIG_BOOTCOMMAND

#define CONFIG_PREBOOT                  /* enable preboot variable      */

#undef	CONFIG_LOADS_ECHO		/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */

#undef  CONFIG_HAS_ETH1

#define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_IDE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_SUPPORT_VFAT

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_CMDLINE_EDITING		/* add command line history	*/

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

#define CONFIG_AUTOBOOT_KEYED	1
#define CONFIG_AUTOBOOT_PROMPT	\
	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#undef CONFIG_AUTOBOOT_DELAY_STR
#define CONFIG_AUTOBOOT_STOP_STR " "

#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/

#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A	*/
#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */

#define CONFIG_PCI_4xx_PTM_OVERWRITE	1 /* overwrite PTMx settings by env */

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#undef	CONFIG_IDE_8xx_DIRECT		    /* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported	*/
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1		/* max. 1 IDE busses	*/
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CONFIG_SYS_ATA_BASE_ADDR	0xF0100000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

#define CONFIG_PRAM		0	/* use pram variable to overwrite */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC32) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC32		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x01
#define CONFIG_SYS_I2C_MULTI_EEPROMS   1       /* more than one eeprom used!   */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* The Catalyst CAT24WC32 has	*/
					/* 32 byte page write mode using*/
					/* last 5 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

/* Use EEPROM for environment variables */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars*/
				   /* total size of a CAT24WC32 is 4096 bytes */

#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
#define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization					*/
#define CONFIG_SYS_EBC_PB1AP		0x92015480
#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (CAN0, 1) initialization					*/
#define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
#define CONFIG_SYS_LED_ADDR		0xF0000380

/* Memory Bank 3 (CompactFlash IDE) initialization				*/
#define CONFIG_SYS_EBC_PB3AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB3CR		0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */

/* Memory Bank 4 (NVRAM/RTC) initialization					*/
/*#define CONFIG_SYS_EBC_PB4AP		  0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1	   */
#define CONFIG_SYS_EBC_PB4AP		0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1	*/
#define CONFIG_SYS_EBC_PB4CR		0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 5 (optional Quart) initialization				*/
#define CONFIG_SYS_EBC_PB5AP		0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
#define CONFIG_SYS_EBC_PB5CR		0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 6 (FPGA internal) initialization					*/
#define CONFIG_SYS_EBC_PB6AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CONFIG_SYS_EBC_PB6CR		0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_FPGA_BASE_ADDR	0xF0400000

/*-----------------------------------------------------------------------
 * FPGA stuff
 */
/* FPGA internal regs */
#define CONFIG_SYS_FPGA_MODE		0x00
#define CONFIG_SYS_FPGA_STATUS		0x02
#define CONFIG_SYS_FPGA_TS		0x04
#define CONFIG_SYS_FPGA_TS_LOW		0x06
#define CONFIG_SYS_FPGA_TS_CAP0	0x10
#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
#define CONFIG_SYS_FPGA_TS_CAP1	0x14
#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
#define CONFIG_SYS_FPGA_TS_CAP2	0x18
#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e

/* FPGA Mode Reg */
#define CONFIG_SYS_FPGA_MODE_CF_RESET	    0x0001
#define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
#define CONFIG_SYS_FPGA_MODE_1WIRE_DIR     0x0100     /* dir=1 -> output */
#define CONFIG_SYS_FPGA_MODE_SIM_OK_DIR    0x0200
#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
#define CONFIG_SYS_FPGA_MODE_1WIRE         0x1000
#define CONFIG_SYS_FPGA_MODE_SIM_OK        0x2000     /* wired-or net from all devices */
#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL  0x4000

/* FPGA Status Reg */
#define CONFIG_SYS_FPGA_STATUS_DIP0    0x0001
#define CONFIG_SYS_FPGA_STATUS_DIP1    0x0002
#define CONFIG_SYS_FPGA_STATUS_DIP2    0x0004
#define CONFIG_SYS_FPGA_STATUS_FLASH   0x0008
#define CONFIG_SYS_FPGA_STATUS_1WIRE   0x1000
#define CONFIG_SYS_FPGA_STATUS_SIM_OK  0x2000

#define CONFIG_SYS_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S30 */

/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
#define CONFIG_SYS_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
#define CONFIG_SYS_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
#define CONFIG_SYS_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
#define CONFIG_SYS_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */

#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#endif	/* __CONFIG_H */
Commit	Line	Data
d4629c8c SR	1	/*
	2	* (C) Copyright 2001-2003
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
d4629c8c SR	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1	21	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
d4629c8c	22	#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
c837dcb1 WD	23	#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
c837dcb1 WD	24	#define CONFIG_CPCI405AB 1 /* ...and special AB version */
d4629c8c	25
2ae18241 WD	26	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	27
c837dcb1	28	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
3a8f28d0	29	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
d4629c8c	30
a20b27a3	31	#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
d4629c8c SR	32
	33	#define CONFIG_BAUDRATE 9600
	34	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	35
d4629c8c	36	#undef CONFIG_BOOTARGS
a20b27a3 SR	37	#undef CONFIG_BOOTCOMMAND
	38
	39	#define CONFIG_PREBOOT /* enable preboot variable */
d4629c8c	40
c837dcb1	41	#undef CONFIG_LOADS_ECHO /* echo on for serial download */
6d0f6bcf	42	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
d4629c8c	43
96e21f86	44	#define CONFIG_PPC4xx_EMAC
d4629c8c	45	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	46	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	47	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
6f35c531 MF	48	#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
6f35c531 MF	49
6f35c531	50	#undef CONFIG_HAS_ETH1
d4629c8c SR	51
	52	#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
	53
5d2ebe1b JL	54	/*
	55	* BOOTP options
	56	*/
	57	#define CONFIG_BOOTP_SUBNETMASK
	58	#define CONFIG_BOOTP_GATEWAY
	59	#define CONFIG_BOOTP_HOSTNAME
	60	#define CONFIG_BOOTP_BOOTPATH
	61	#define CONFIG_BOOTP_DNS
	62	#define CONFIG_BOOTP_DNS2
	63	#define CONFIG_BOOTP_SEND_HOSTNAME
	64
d4629c8c	65
49cf7e8e JL	66	/*
	67	* Command line configuration.
	68	*/
	69	#include <config_cmd_default.h>
	70
	71	#define CONFIG_CMD_DHCP
	72	#define CONFIG_CMD_PCI
	73	#define CONFIG_CMD_IRQ
	74	#define CONFIG_CMD_IDE
	75	#define CONFIG_CMD_FAT
	76	#define CONFIG_CMD_ELF
	77	#define CONFIG_CMD_DATE
49cf7e8e JL	78	#define CONFIG_CMD_I2C
	79	#define CONFIG_CMD_MII
	80	#define CONFIG_CMD_PING
3ba605d4	81	#define CONFIG_CMD_BSP
49cf7e8e JL	82	#define CONFIG_CMD_EEPROM
49cf7e8e JL	83
d4629c8c SR	84
	85	#define CONFIG_MAC_PARTITION
	86	#define CONFIG_DOS_PARTITION
	87
a20b27a3 SR	88	#define CONFIG_SUPPORT_VFAT
a20b27a3 SR	89
c837dcb1	90	#undef CONFIG_WATCHDOG /* watchdog disabled */
d4629c8c	91
c837dcb1	92	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
d4629c8c SR	93
	94	/*
	95	* Miscellaneous configurable options
	96	*/
6d0f6bcf JCPV	97	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	98	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
d4629c8c	99
6d0f6bcf	100	#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
d4629c8c	101
49cf7e8e	102	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	103	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
d4629c8c	104	#else
6d0f6bcf	105	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
d4629c8c	106	#endif
6d0f6bcf JCPV	107	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	108	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	109	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
d4629c8c	110
6d0f6bcf	111	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
d4629c8c	112
6d0f6bcf	113	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
d4629c8c	114
6d0f6bcf JCPV	115	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	116	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
d4629c8c	117
550650dd SR	118	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	119	#define CONFIG_SYS_NS16550
	120	#define CONFIG_SYS_NS16550_SERIAL
	121	#define CONFIG_SYS_NS16550_REG_SIZE 1
	122	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	123
6d0f6bcf	124	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf	125	#define CONFIG_SYS_BASE_BAUD 691200
d4629c8c SR	126
d4629c8c SR	127	/* The following table includes the supported baudrates */
6d0f6bcf	128	#define CONFIG_SYS_BAUDRATE_TABLE \
8bde7f77 WD	129	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	130	57600, 115200, 230400, 460800, 921600 }
d4629c8c	131
6d0f6bcf JCPV	132	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	133	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
d4629c8c	134
6d0f6bcf	135	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
d4629c8c	136
ac53ee83 MF	137	#define CONFIG_CMDLINE_EDITING /* add command line history */
ac53ee83 MF	138
d4629c8c SR	139	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
d4629c8c SR	140
c837dcb1	141	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
d4629c8c	142
75511b47 MF	143	#define CONFIG_AUTOBOOT_KEYED 1
	144	#define CONFIG_AUTOBOOT_PROMPT \
	145	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
	146	#undef CONFIG_AUTOBOOT_DELAY_STR
	147	#define CONFIG_AUTOBOOT_STOP_STR " "
	148
6d0f6bcf	149	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
53cf9435	150
d4629c8c SR	151	/*-----------------------------------------------------------------------
	152	* PCI stuff
	153	*-----------------------------------------------------------------------
	154	*/
c837dcb1 WD	155	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	156	#define PCI_HOST_FORCE 1 /* configure as pci host */
	157	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	158
	159	#define CONFIG_PCI /* include pci support */
842033e6	160	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c837dcb1 WD	161	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	162	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	163	/* resource configuration */
	164
	165	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	166
a20b27a3 SR	167	#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
a20b27a3 SR	168
c837dcb1 WD	169	#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
c837dcb1 WD	170
6d0f6bcf JCPV	171	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	172	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
	173	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
	174	#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	175	#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
	176	#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) \| 1) /* memsize, enable hard-wired to 1 */
	177	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	178	#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
	179	#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
468ebf19	180	#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
d4629c8c	181
82379b55 MF	182	#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
82379b55 MF	183
d4629c8c SR	184	/*-----------------------------------------------------------------------
	185	* IDE/ATA stuff
	186	*-----------------------------------------------------------------------
	187	*/
c837dcb1 WD	188	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
c837dcb1 WD	189	#undef CONFIG_IDE_LED /* no led for ide supported */
d4629c8c SR	190	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
d4629c8c SR	191
6d0f6bcf JCPV	192	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
6d0f6bcf JCPV	193	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS1) / max. 1 drives per IDE bus */
d4629c8c	194
6d0f6bcf JCPV	195	#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
6d0f6bcf JCPV	196	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
d4629c8c	197
6d0f6bcf JCPV	198	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	199	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
	200	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
d4629c8c SR	201
	202	/*-----------------------------------------------------------------------
	203	* Start addresses for the final memory configuration
	204	* (Set up by the startup code)
6d0f6bcf	205	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
d4629c8c	206	*/
6d0f6bcf JCPV	207	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	208	#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
	209	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	210	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	211	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
d4629c8c	212
3ba605d4 MF	213	#define CONFIG_PRAM 0 /* use pram variable to overwrite */
3ba605d4 MF	214
d4629c8c SR	215	/*
	216	* For booting Linux, the board info and command line data
	217	* have to be in the first 8 MB of memory, since this is
	218	* the maximum mapped by the Linux kernel during initialization.
	219	*/
6d0f6bcf	220	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
ac53ee83 MF	221
	222	#define CONFIG_OF_LIBFDT
	223	#define CONFIG_OF_BOARD_SETUP
	224
d4629c8c SR	225	/*-----------------------------------------------------------------------
	226	* FLASH organization
	227	*/
6d0f6bcf JCPV	228	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	229	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
d4629c8c	230
6d0f6bcf JCPV	231	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	232	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
d4629c8c	233
6d0f6bcf JCPV	234	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	235	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	236	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
d4629c8c SR	237	/*
	238	* The following defines are added for buggy IOP480 byte interface.
	239	* All other boards should use the standard values (CPCI405 etc.)
	240	*/
6d0f6bcf JCPV	241	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	242	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	243	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
d4629c8c	244
6d0f6bcf	245	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
d4629c8c	246
d4629c8c	247	/*-----------------------------------------------------------------------
2853d29b	248	* I2C EEPROM (CAT24WC32) for environment
d4629c8c	249	*/
2853d29b	250	#define CONFIG_HARD_I2C /* I2c with hardware support */
d0b0dcaa	251	#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
6d0f6bcf JCPV	252	#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
6d0f6bcf JCPV	253	#define CONFIG_SYS_I2C_SLAVE 0x7F
d4629c8c	254
6d0f6bcf JCPV	255	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
6d0f6bcf JCPV	256	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
c837dcb1	257	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	258	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
	259	#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom used! */
	260	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
2853d29b	261	/* 32 byte page write mode using*/
c837dcb1	262	/* last 5 bits of the address */
6d0f6bcf	263	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
2853d29b SR	264
2853d29b SR	265	/* Use EEPROM for environment variables */
d4629c8c	266
bb1f8b4f	267	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	268	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	269	#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
2853d29b	270	/* total size of a CAT24WC32 is 4096 bytes */
d4629c8c	271
6d0f6bcf JCPV	272	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
	273	#define CONFIG_SYS_NVRAM_SIZE (321024) / NVRAM size */
	274	#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
d4629c8c	275
d4629c8c SR	276	/*
	277	* Init Memory Controller:
	278	*
	279	* BR0/1 and OR0/1 (FLASH)
	280	*/
	281
	282	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	283	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	284
	285	/*-----------------------------------------------------------------------
	286	* External Bus Controller (EBC) Setup
	287	*/
	288
c837dcb1	289	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	290	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	291	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
d4629c8c	292
c837dcb1	293	/* Memory Bank 1 (Flash Bank 1) initialization */
6d0f6bcf JCPV	294	#define CONFIG_SYS_EBC_PB1AP 0x92015480
6d0f6bcf JCPV	295	#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
d4629c8c	296
c837dcb1	297	/* Memory Bank 2 (CAN0, 1) initialization */
6d0f6bcf JCPV	298	#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	299	#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	300	#define CONFIG_SYS_LED_ADDR 0xF0000380
d4629c8c	301
c837dcb1	302	/* Memory Bank 3 (CompactFlash IDE) initialization */
6d0f6bcf JCPV	303	#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
6d0f6bcf JCPV	304	#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
d4629c8c	305
c837dcb1	306	/* Memory Bank 4 (NVRAM/RTC) initialization */
6d0f6bcf JCPV	307	/#define CONFIG_SYS_EBC_PB4AP 0x01805280 / TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
	308	#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
	309	#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
d4629c8c	310
c837dcb1	311	/* Memory Bank 5 (optional Quart) initialization */
6d0f6bcf JCPV	312	#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
6d0f6bcf JCPV	313	#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
d4629c8c	314
c837dcb1	315	/* Memory Bank 6 (FPGA internal) initialization */
6d0f6bcf JCPV	316	#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	317	#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
	318	#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
d4629c8c SR	319
	320	/*-----------------------------------------------------------------------
	321	* FPGA stuff
	322	*/
	323	/* FPGA internal regs */
6d0f6bcf JCPV	324	#define CONFIG_SYS_FPGA_MODE 0x00
	325	#define CONFIG_SYS_FPGA_STATUS 0x02
	326	#define CONFIG_SYS_FPGA_TS 0x04
	327	#define CONFIG_SYS_FPGA_TS_LOW 0x06
	328	#define CONFIG_SYS_FPGA_TS_CAP0 0x10
	329	#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
	330	#define CONFIG_SYS_FPGA_TS_CAP1 0x14
	331	#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
	332	#define CONFIG_SYS_FPGA_TS_CAP2 0x18
	333	#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
	334	#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
	335	#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
d4629c8c SR	336
d4629c8c SR	337	/* FPGA Mode Reg */
6d0f6bcf JCPV	338	#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
	339	#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
	340	#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
	341	#define CONFIG_SYS_FPGA_MODE_1WIRE_DIR 0x0100 /* dir=1 -> output */
	342	#define CONFIG_SYS_FPGA_MODE_SIM_OK_DIR 0x0200
	343	#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
	344	#define CONFIG_SYS_FPGA_MODE_1WIRE 0x1000
	345	#define CONFIG_SYS_FPGA_MODE_SIM_OK 0x2000 /* wired-or net from all devices */
	346	#define CONFIG_SYS_FPGA_MODE_TESTRIG_FAIL 0x4000
d4629c8c SR	347
d4629c8c SR	348	/* FPGA Status Reg */
6d0f6bcf JCPV	349	#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
	350	#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
	351	#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
	352	#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
	353	#define CONFIG_SYS_FPGA_STATUS_1WIRE 0x1000
	354	#define CONFIG_SYS_FPGA_STATUS_SIM_OK 0x2000
d4629c8c	355
6d0f6bcf JCPV	356	#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
6d0f6bcf JCPV	357	#define CONFIG_SYS_FPGA_MAX_SIZE 1281024 / 128kByte is enough for XC2S30 */
d4629c8c SR	358
d4629c8c SR	359	/* FPGA program pin configuration */
6d0f6bcf JCPV	360	#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
	361	#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
	362	#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
	363	#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
	364	#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
d4629c8c SR	365
	366	/*-----------------------------------------------------------------------
	367	* Definitions for initial stack pointer and data area (in data cache)
	368	*/
6d0f6bcf	369	#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
d4629c8c	370
6d0f6bcf	371	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
553f0982	372	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
25ddd1fb	373	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	374	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
d4629c8c	375
d4629c8c	376	#endif /* __CONFIG_H */