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a20b27a3 SR |
1 | /* |
2 | * (C) Copyright 2001-2004 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ | |
38 | #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ | |
39 | #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ | |
40 | ||
41 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ | |
42 | ||
43 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ | |
44 | ||
45 | #define CONFIG_BAUDRATE 9600 | |
46 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
47 | ||
48 | #undef CONFIG_BOOTARGS | |
49 | #undef CONFIG_BOOTCOMMAND | |
50 | ||
51 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
52 | ||
53 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 54 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
a20b27a3 SR |
55 | |
56 | #define CONFIG_MII 1 /* MII PHY management */ | |
57 | #define CONFIG_PHY_ADDR 0 /* PHY address */ | |
58 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ | |
6f35c531 MF |
59 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
60 | ||
61 | #define CONFIG_NET_MULTI 1 | |
62 | #undef CONFIG_HAS_ETH1 | |
a20b27a3 SR |
63 | |
64 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
65 | ||
5d2ebe1b JL |
66 | /* |
67 | * BOOTP options | |
68 | */ | |
69 | #define CONFIG_BOOTP_SUBNETMASK | |
70 | #define CONFIG_BOOTP_GATEWAY | |
71 | #define CONFIG_BOOTP_HOSTNAME | |
72 | #define CONFIG_BOOTP_BOOTPATH | |
73 | #define CONFIG_BOOTP_DNS | |
74 | #define CONFIG_BOOTP_DNS2 | |
75 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
76 | ||
a20b27a3 | 77 | |
49cf7e8e JL |
78 | /* |
79 | * Command line configuration. | |
80 | */ | |
81 | #include <config_cmd_default.h> | |
82 | ||
83 | #define CONFIG_CMD_DHCP | |
84 | #define CONFIG_CMD_PCI | |
85 | #define CONFIG_CMD_IRQ | |
86 | #define CONFIG_CMD_IDE | |
87 | #define CONFIG_CMD_FAT | |
88 | #define CONFIG_CMD_ELF | |
89 | #define CONFIG_CMD_DATE | |
49cf7e8e JL |
90 | #define CONFIG_CMD_I2C |
91 | #define CONFIG_CMD_MII | |
92 | #define CONFIG_CMD_PING | |
93 | #define CONFIG_CMD_BSP | |
94 | #define CONFIG_CMD_EEPROM | |
95 | ||
a20b27a3 SR |
96 | #define CONFIG_MAC_PARTITION |
97 | #define CONFIG_DOS_PARTITION | |
98 | ||
99 | #define CONFIG_SUPPORT_VFAT | |
100 | ||
101 | #undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ | |
102 | ||
a20b27a3 SR |
103 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
104 | ||
105 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ | |
106 | ||
107 | /* | |
108 | * Miscellaneous configurable options | |
109 | */ | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
111 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
a20b27a3 | 112 | |
6d0f6bcf JCPV |
113 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
114 | #ifdef CONFIG_SYS_HUSH_PARSER | |
115 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
a20b27a3 SR |
116 | #endif |
117 | ||
49cf7e8e | 118 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 119 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
a20b27a3 | 120 | #else |
6d0f6bcf | 121 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
a20b27a3 | 122 | #endif |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
124 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
125 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
a20b27a3 | 126 | |
6d0f6bcf | 127 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
a20b27a3 | 128 | |
6d0f6bcf | 129 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
a20b27a3 SR |
130 | |
131 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ | |
132 | ||
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
134 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
a20b27a3 | 135 | |
6d0f6bcf JCPV |
136 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
137 | #define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ | |
138 | #define CONFIG_SYS_BASE_BAUD 691200 | |
a20b27a3 SR |
139 | |
140 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 141 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
a20b27a3 SR |
142 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
143 | 57600, 115200, 230400, 460800, 921600 } | |
144 | ||
6d0f6bcf JCPV |
145 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
146 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
a20b27a3 | 147 | |
6d0f6bcf | 148 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
a20b27a3 SR |
149 | |
150 | #define CONFIG_LOOPW 1 /* enable loopw command */ | |
151 | ||
152 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
153 | ||
154 | /* Only interrupt boot if special string is typed */ | |
f2302d44 SR |
155 | #define CONFIG_AUTOBOOT_KEYED 1 |
156 | #define CONFIG_AUTOBOOT_PROMPT \ | |
157 | "Autobooting in %d seconds\n", bootdelay | |
a20b27a3 SR |
158 | #undef CONFIG_AUTOBOOT_DELAY_STR |
159 | #undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */ | |
160 | #define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/ | |
161 | ||
162 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ | |
163 | ||
6d0f6bcf | 164 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
a20b27a3 SR |
165 | |
166 | /*----------------------------------------------------------------------- | |
167 | * PCI stuff | |
168 | *----------------------------------------------------------------------- | |
169 | */ | |
170 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
171 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
172 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
173 | ||
174 | #define CONFIG_PCI /* include pci support */ | |
175 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ | |
176 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
177 | /* resource configuration */ | |
178 | ||
179 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
180 | ||
181 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
182 | ||
183 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ | |
184 | ||
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
186 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
187 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ | |
188 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
189 | #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ | |
190 | #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ | |
191 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
192 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
193 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
194 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
a20b27a3 SR |
195 | |
196 | /*----------------------------------------------------------------------- | |
197 | * IDE/ATA stuff | |
198 | *----------------------------------------------------------------------- | |
199 | */ | |
200 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
201 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
202 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ | |
203 | ||
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
205 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ | |
a20b27a3 | 206 | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
208 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
a20b27a3 | 209 | |
6d0f6bcf JCPV |
210 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
211 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
212 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
a20b27a3 SR |
213 | |
214 | /*----------------------------------------------------------------------- | |
215 | * Start addresses for the final memory configuration | |
216 | * (Set up by the startup code) | |
6d0f6bcf | 217 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a20b27a3 | 218 | */ |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
220 | #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 | |
221 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
222 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
223 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
a20b27a3 SR |
224 | |
225 | /* | |
226 | * For booting Linux, the board info and command line data | |
227 | * have to be in the first 8 MB of memory, since this is | |
228 | * the maximum mapped by the Linux kernel during initialization. | |
229 | */ | |
6d0f6bcf | 230 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
a20b27a3 SR |
231 | /*----------------------------------------------------------------------- |
232 | * FLASH organization | |
233 | */ | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
235 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
a20b27a3 | 236 | |
6d0f6bcf JCPV |
237 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
238 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
a20b27a3 | 239 | |
6d0f6bcf JCPV |
240 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
241 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
242 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
a20b27a3 SR |
243 | /* |
244 | * The following defines are added for buggy IOP480 byte interface. | |
245 | * All other boards should use the standard values (CPCI405 etc.) | |
246 | */ | |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
248 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
249 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
a20b27a3 | 250 | |
6d0f6bcf | 251 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
a20b27a3 | 252 | |
a20b27a3 SR |
253 | #if 0 /* Use NVRAM for environment variables */ |
254 | /*----------------------------------------------------------------------- | |
255 | * NVRAM organization | |
256 | */ | |
9314cee6 | 257 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
0e8d1586 JCPV |
258 | #define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ |
259 | #define CONFIG_ENV_ADDR \ | |
6d0f6bcf | 260 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */ |
a20b27a3 SR |
261 | |
262 | #else /* Use EEPROM for environment variables */ | |
263 | ||
bb1f8b4f | 264 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
265 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
266 | #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ | |
a20b27a3 SR |
267 | /* total size of a CAT24WC16 is 2048 bytes */ |
268 | #endif | |
269 | ||
6d0f6bcf JCPV |
270 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
271 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
272 | #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ | |
a20b27a3 SR |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * I2C EEPROM (CAT24WC16) for environment | |
276 | */ | |
277 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
6d0f6bcf JCPV |
278 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
279 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
a20b27a3 | 280 | |
6d0f6bcf JCPV |
281 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
282 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
a20b27a3 | 283 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
285 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
a20b27a3 SR |
286 | /* 16 byte page write mode using*/ |
287 | /* last 4 bits of the address */ | |
6d0f6bcf | 288 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
a20b27a3 | 289 | |
a20b27a3 SR |
290 | /* |
291 | * Init Memory Controller: | |
292 | * | |
293 | * BR0/1 and OR0/1 (FLASH) | |
294 | */ | |
295 | ||
296 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ | |
297 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ | |
298 | ||
299 | /*----------------------------------------------------------------------- | |
300 | * External Bus Controller (EBC) Setup | |
301 | */ | |
302 | ||
303 | /* Memory Bank 0 (Flash Bank 0) initialization */ | |
6d0f6bcf JCPV |
304 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
305 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
306 | |
307 | /* Memory Bank 1 (Flash Bank 1) initialization */ | |
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
309 | #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
310 | |
311 | /* Memory Bank 2 (CAN0, 1) initialization */ | |
6d0f6bcf JCPV |
312 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
313 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
314 | #define CONFIG_SYS_LED_ADDR 0xF0000380 | |
a20b27a3 SR |
315 | |
316 | /* Memory Bank 3 (CompactFlash IDE) initialization */ | |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
318 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
a20b27a3 SR |
319 | |
320 | /* Memory Bank 4 (NVRAM/RTC) initialization */ | |
6d0f6bcf JCPV |
321 | /*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ |
322 | #define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ | |
323 | #define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ | |
a20b27a3 SR |
324 | |
325 | /* Memory Bank 5 (optional Quart) initialization */ | |
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ |
327 | #define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ | |
a20b27a3 SR |
328 | |
329 | /* Memory Bank 6 (FPGA internal) initialization */ | |
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
331 | #define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
332 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 | |
a20b27a3 SR |
333 | |
334 | /*----------------------------------------------------------------------- | |
335 | * FPGA stuff | |
336 | */ | |
337 | /* FPGA internal regs */ | |
6d0f6bcf JCPV |
338 | #define CONFIG_SYS_FPGA_MODE 0x00 |
339 | #define CONFIG_SYS_FPGA_STATUS 0x02 | |
340 | #define CONFIG_SYS_FPGA_TS 0x04 | |
341 | #define CONFIG_SYS_FPGA_TS_LOW 0x06 | |
342 | #define CONFIG_SYS_FPGA_TS_CAP0 0x10 | |
343 | #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 | |
344 | #define CONFIG_SYS_FPGA_TS_CAP1 0x14 | |
345 | #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 | |
346 | #define CONFIG_SYS_FPGA_TS_CAP2 0x18 | |
347 | #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a | |
348 | #define CONFIG_SYS_FPGA_TS_CAP3 0x1c | |
349 | #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e | |
a20b27a3 SR |
350 | |
351 | /* FPGA Mode Reg */ | |
6d0f6bcf JCPV |
352 | #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 |
353 | #define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 | |
354 | #define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ | |
355 | #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 | |
356 | #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 | |
357 | #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 | |
a20b27a3 SR |
358 | |
359 | /* FPGA Status Reg */ | |
6d0f6bcf JCPV |
360 | #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 |
361 | #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 | |
362 | #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 | |
363 | #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 | |
364 | #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 | |
a20b27a3 | 365 | |
6d0f6bcf JCPV |
366 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
367 | #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ | |
a20b27a3 SR |
368 | |
369 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
370 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
371 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
372 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
373 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
374 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
a20b27a3 SR |
375 | |
376 | /*----------------------------------------------------------------------- | |
377 | * Definitions for initial stack pointer and data area (in data cache) | |
378 | */ | |
6d0f6bcf | 379 | #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ |
a20b27a3 | 380 | |
6d0f6bcf JCPV |
381 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
382 | #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ | |
383 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
384 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
385 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
a20b27a3 | 386 | |
a20b27a3 SR |
387 | /* |
388 | * Internal Definitions | |
389 | * | |
390 | * Boot Flags | |
391 | */ | |
392 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
393 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
394 | ||
395 | #endif /* __CONFIG_H */ |