projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| a20b27a3 SR |
1 | /* |
| 2 | * (C) Copyright 2001 | |
| 3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| bfc81252 | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| a20b27a3 SR |
16 | * GNU General Public License for more details. |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | /* | |
| 25 | * board/config.h - configuration options, board specific | |
| 26 | */ | |
| 27 | ||
| 28 | /************************************************************************* | |
| 29 | * (c) 2004 esd gmbh Hannover | |
| 30 | * | |
| 31 | * | |
| 32 | * from db64360.h file | |
| 33 | * by Reinhard Arlt reinhard.arlt@esd-electronics.com | |
| 34 | * | |
| 35 | ************************************************************************/ | |
| 36 | ||
| 37 | ||
| 38 | #ifndef __CONFIG_H | |
| 39 | #define __CONFIG_H | |
| 40 | ||
| a20b27a3 SR |
41 | /* This define must be before the core.h include */ |
| 42 | #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ | |
| 43 | ||
| 44 | #ifndef __ASSEMBLY__ | |
| 45 | #include <../board/Marvell/include/core.h> | |
| 46 | #endif | |
| 47 | /*-----------------------------------------------------*/ | |
| 48 | ||
| 49 | #include "../board/esd/cpci750/local.h" | |
| 50 | ||
| 51 | /* | |
| 52 | * High Level Configuration Options | |
| 53 | * (easy to change) | |
| 54 | */ | |
| 55 | ||
| 56 | #define CONFIG_750FX /* we have a 750FX (override local.h) */ | |
| 57 | ||
| 58 | #define CONFIG_CPCI750 1 /* this is an CPCI750 board */ | |
| 59 | ||
| 2ae18241 WD |
60 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
| 61 | ||
| bfc81252 | 62 | #define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */ |
| a20b27a3 | 63 | |
| 0738e24e | 64 | #define CONFIG_MV64360_ECC /* enable ECC support */ |
| a20b27a3 | 65 | |
| 31d82672 BB |
66 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 67 | ||
| a20b27a3 SR |
68 | /* which initialization functions to call for this board */ |
| 69 | #define CONFIG_MISC_INIT_R | |
| 70 | #define CONFIG_BOARD_PRE_INIT | |
| 71 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
| 72 | ||
| 6d0f6bcf | 73 | #define CONFIG_SYS_BOARD_NAME "CPCI750" |
| a20b27a3 SR |
74 | #define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX" |
| 75 | ||
| 6d0f6bcf JCPV |
76 | /*#define CONFIG_SYS_HUSH_PARSER*/ |
| 77 | #define CONFIG_SYS_HUSH_PARSER | |
| a20b27a3 | 78 | |
| 6d0f6bcf | 79 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| a20b27a3 | 80 | |
| 0a14d6b8 SR |
81 | #define CONFIG_CMDLINE_EDITING /* add command line history */ |
| 82 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
| a7b9fb91 | 83 | |
| a20b27a3 | 84 | /* Define which ETH port will be used for connecting the network */ |
| 6d0f6bcf | 85 | #define CONFIG_SYS_ETH_PORT ETH_0 |
| a20b27a3 SR |
86 | |
| 87 | /* | |
| 88 | * The following defines let you select what serial you want to use | |
| 89 | * for your console driver. | |
| 90 | * | |
| 91 | * what to do: | |
| bfc81252 | 92 | * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial |
| 6d0f6bcf | 93 | * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 |
| a20b27a3 SR |
94 | * to 0 below. |
| 95 | * | |
| 96 | * to use the MPSC, #define CONFIG_MPSC. If you have wired up another | |
| 97 | * mpsc channel, change CONFIG_MPSC_PORT to the desired value. | |
| 98 | */ | |
| bfc81252 | 99 | #define CONFIG_MPSC |
| a20b27a3 SR |
100 | #define CONFIG_MPSC_PORT 0 |
| 101 | ||
| 102 | /* to change the default ethernet port, use this define (options: 0, 1, 2) */ | |
| 103 | #define CONFIG_NET_MULTI | |
| bfc81252 | 104 | #define MV_ETH_DEVS 1 |
| a20b27a3 SR |
105 | #define CONFIG_ETHER_PORT 0 |
| 106 | ||
| 107 | #undef CONFIG_ETHER_PORT_MII /* use RMII */ | |
| 108 | ||
| 109 | #define CONFIG_BOOTDELAY 5 /* autoboot disabled */ | |
| 110 | ||
| 111 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
| 112 | ||
| 113 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
| 114 | ||
| 115 | ||
| 116 | #undef CONFIG_BOOTARGS | |
| 117 | ||
| 118 | /* ----------------------------------------------------------------------------- | |
| 119 | * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus | |
| 120 | */ | |
| 121 | ||
| 122 | #define CONFIG_IPADDR "192.168.0.185" | |
| 123 | ||
| 124 | #define CONFIG_SERIAL "AA000001" | |
| 125 | #define CONFIG_SERVERIP "10.0.0.79" | |
| bfc81252 | 126 | #define CONFIG_ROOTPATH "/export/nfs_cpci750/%s" |
| a20b27a3 SR |
127 | |
| 128 | #define CONFIG_TESTDRAMDATA y | |
| bfc81252 | 129 | #define CONFIG_TESTDRAMADDRESS n |
| a20b27a3 SR |
130 | #define CONFIG_TESETDRAMWALK n |
| 131 | ||
| 132 | /* ----------------------------------------------------------------------------- */ | |
| 133 | ||
| 134 | ||
| bfc81252 | 135 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
| 6d0f6bcf | 136 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ |
| a20b27a3 SR |
137 | |
| 138 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| bfc81252 | 139 | #undef CONFIG_ALTIVEC /* undef to disable */ |
| a20b27a3 | 140 | |
| 5d2ebe1b JL |
141 | /* |
| 142 | * BOOTP options | |
| 143 | */ | |
| 144 | #define CONFIG_BOOTP_SUBNETMASK | |
| 145 | #define CONFIG_BOOTP_GATEWAY | |
| 146 | #define CONFIG_BOOTP_HOSTNAME | |
| 147 | #define CONFIG_BOOTP_BOOTPATH | |
| 148 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| a20b27a3 SR |
149 | |
| 150 | ||
| 49cf7e8e JL |
151 | /* |
| 152 | * Command line configuration. | |
| 153 | */ | |
| 154 | #include <config_cmd_default.h> | |
| 155 | ||
| 5728be38 WD |
156 | #define CONFIG_CMD_ASKENV |
| 157 | #define CONFIG_CMD_I2C | |
| 158 | #define CONFIG_CMD_CACHE | |
| 159 | #define CONFIG_CMD_EEPROM | |
| 160 | #define CONFIG_CMD_PCI | |
| 161 | #define CONFIG_CMD_ELF | |
| 162 | #define CONFIG_CMD_DATE | |
| 163 | #define CONFIG_CMD_NET | |
| 164 | #define CONFIG_CMD_PING | |
| 165 | #define CONFIG_CMD_IDE | |
| 166 | #define CONFIG_CMD_FAT | |
| 167 | #define CONFIG_CMD_EXT2 | |
| a20b27a3 | 168 | |
| a20b27a3 | 169 | |
| 49cf7e8e | 170 | #define CONFIG_DOS_PARTITION |
| a20b27a3 | 171 | |
| a7b9fb91 SR |
172 | #define CONFIG_USE_CPCIDVI |
| 173 | ||
| bfc81252 | 174 | #ifdef CONFIG_USE_CPCIDVI |
| a7b9fb91 SR |
175 | #define CONFIG_VIDEO |
| 176 | #define CONFIG_VIDEO_CT69000 | |
| 177 | #define CONFIG_CFB_CONSOLE | |
| 178 | #define CONFIG_VIDEO_SW_CURSOR | |
| 179 | #define CONFIG_VIDEO_LOGO | |
| 180 | #define CONFIG_I8042_KBD | |
| 6d0f6bcf | 181 | #define CONFIG_SYS_ISA_IO 0 |
| a7b9fb91 SR |
182 | #endif |
| 183 | ||
| a20b27a3 SR |
184 | /* |
| 185 | * Miscellaneous configurable options | |
| 186 | */ | |
| 6d0f6bcf JCPV |
187 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
| 188 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
| 189 | #define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed default */ | |
| a20b27a3 | 190 | |
| 6d0f6bcf JCPV |
191 | #define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ |
| 192 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 193 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 49cf7e8e | 194 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 195 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| a20b27a3 | 196 | #else |
| 6d0f6bcf | 197 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| a20b27a3 | 198 | #endif |
| 6d0f6bcf JCPV |
199 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 200 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 201 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| a20b27a3 | 202 | |
| 6d0f6bcf JCPV |
203 | /*#define CONFIG_SYS_MEMTEST_START 0x00400000*/ /* memtest works on */ |
| 204 | /*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ | |
| 205 | /*#define CONFIG_SYS_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */ | |
| a20b27a3 SR |
206 | |
| 207 | /* | |
| 6d0f6bcf | 208 | #define CONFIG_SYS_DRAM_TEST |
| a20b27a3 | 209 | * DRAM tests |
| 6d0f6bcf | 210 | * CONFIG_SYS_DRAM_TEST - enables the following tests. |
| a20b27a3 | 211 | * |
| 6d0f6bcf | 212 | * CONFIG_SYS_DRAM_TEST_DATA - Enables test for shorted or open data lines |
| bfc81252 WD |
213 | * Environment variable 'test_dram_data' must be |
| 214 | * set to 'y'. | |
| 6d0f6bcf | 215 | * CONFIG_SYS_DRAM_TEST_DATA - Enables test to verify that each word is uniquely |
| bfc81252 WD |
216 | * addressable. Environment variable |
| 217 | * 'test_dram_address' must be set to 'y'. | |
| 6d0f6bcf | 218 | * CONFIG_SYS_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test. |
| bfc81252 WD |
219 | * This test takes about 6 minutes to test 64 MB. |
| 220 | * Environment variable 'test_dram_walk' must be | |
| 221 | * set to 'y'. | |
| a20b27a3 | 222 | */ |
| 6d0f6bcf JCPV |
223 | #define CONFIG_SYS_DRAM_TEST |
| 224 | #if defined(CONFIG_SYS_DRAM_TEST) | |
| 225 | #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ | |
| 226 | /*#define CONFIG_SYS_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */ | |
| 227 | #define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */ | |
| 228 | #define CONFIG_SYS_DRAM_TEST_DATA | |
| 229 | #define CONFIG_SYS_DRAM_TEST_ADDRESS | |
| 230 | #define CONFIG_SYS_DRAM_TEST_WALK | |
| 231 | #endif /* CONFIG_SYS_DRAM_TEST */ | |
| a20b27a3 SR |
232 | |
| 233 | #define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */ | |
| 6d0f6bcf | 234 | #undef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */ |
| a20b27a3 | 235 | |
| 6d0f6bcf | 236 | #define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ |
| a20b27a3 | 237 | |
| 6d0f6bcf | 238 | #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ |
| ee80fa7b | 239 | #define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */ |
| a20b27a3 | 240 | |
| 6d0f6bcf | 241 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
| a20b27a3 | 242 | |
| 6d0f6bcf | 243 | #define CONFIG_SYS_TCLK 133000000 |
| a20b27a3 | 244 | |
| 6d0f6bcf JCPV |
245 | /*#define CONFIG_SYS_750FX_HID0 0x8000c084*/ |
| 246 | #define CONFIG_SYS_750FX_HID0 0x80008484 | |
| 247 | #define CONFIG_SYS_750FX_HID1 0x54800000 | |
| 248 | #define CONFIG_SYS_750FX_HID2 0x00000000 | |
| a20b27a3 SR |
249 | |
| 250 | /* | |
| 251 | * Low Level Configuration Settings | |
| 252 | * (address mappings, register initial values, etc.) | |
| 253 | * You should know what you are doing if you make changes here. | |
| 254 | */ | |
| 255 | ||
| 256 | /*----------------------------------------------------------------------- | |
| 257 | * Definitions for initial stack pointer and data area | |
| 258 | */ | |
| 259 | ||
| 260 | /* | |
| 6d0f6bcf | 261 | * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS |
| a20b27a3 SR |
262 | * To an unused memory region. The stack will remain in cache until RAM |
| 263 | * is initialized | |
| 264 | */ | |
| 6d0f6bcf JCPV |
265 | #undef CONFIG_SYS_INIT_RAM_LOCK |
| 266 | /* #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */ | |
| 267 | /* #define CONFIG_SYS_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */ | |
| 268 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf1080000 /* unused memory region */ | |
| 553f0982 | 269 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
| 25ddd1fb | 270 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| a20b27a3 SR |
271 | |
| 272 | #define RELOCATE_INTERNAL_RAM_ADDR | |
| 273 | #ifdef RELOCATE_INTERNAL_RAM_ADDR | |
| 6d0f6bcf JCPV |
274 | /*#define CONFIG_SYS_INTERNAL_RAM_ADDR 0xfba00000*/ |
| 275 | #define CONFIG_SYS_INTERNAL_RAM_ADDR 0xf1080000 | |
| a20b27a3 SR |
276 | #endif |
| 277 | ||
| 278 | /*----------------------------------------------------------------------- | |
| 279 | * Start addresses for the final memory configuration | |
| 280 | * (Set up by the startup code) | |
| 6d0f6bcf | 281 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| a20b27a3 | 282 | */ |
| 6d0f6bcf | 283 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| a20b27a3 | 284 | /* Dummies for BAT 4-7 */ |
| 6d0f6bcf JCPV |
285 | #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ |
| 286 | #define CONFIG_SYS_SDRAM2_BASE 0x20000000 | |
| 287 | #define CONFIG_SYS_SDRAM3_BASE 0x30000000 | |
| 288 | #define CONFIG_SYS_SDRAM4_BASE 0x40000000 | |
| 289 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 | |
| 290 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 291 | #define CONFIG_SYS_MONITOR_BASE 0xfff00000 | |
| 292 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */ | |
| a20b27a3 SR |
293 | |
| 294 | /*----------------------------------------------------------------------- | |
| 295 | * FLASH related | |
| 296 | *----------------------------------------------------------------------*/ | |
| 297 | ||
| 00b1883a | 298 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
299 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
| 300 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */ | |
| 301 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ | |
| 302 | #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of flash banks */ | |
| 303 | #define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */ | |
| 304 | #define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* size of flash bank */ | |
| 305 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
| 306 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ | |
| 307 | CONFIG_SYS_FLASH_BASE + 1*CONFIG_SYS_FLASH_INCREMENT, \ | |
| 308 | CONFIG_SYS_FLASH_BASE + 2*CONFIG_SYS_FLASH_INCREMENT, \ | |
| 309 | CONFIG_SYS_FLASH_BASE + 3*CONFIG_SYS_FLASH_INCREMENT } | |
| 310 | #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */ | |
| a20b27a3 SR |
311 | |
| 312 | /* areas to map different things with the GT in physical space */ | |
| 6d0f6bcf | 313 | #define CONFIG_SYS_DRAM_BANKS 4 |
| a20b27a3 SR |
314 | |
| 315 | /* What to put in the bats. */ | |
| 6d0f6bcf | 316 | #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 |
| a20b27a3 SR |
317 | |
| 318 | /* Peripheral Device section */ | |
| 319 | ||
| 320 | /*******************************************************/ | |
| bfc81252 WD |
321 | /* We have on the cpci750 Board : */ |
| 322 | /* GT-Chipset Register Area */ | |
| 323 | /* GT-Chipset internal SRAM 256k */ | |
| 324 | /* SRAM on external device module */ | |
| 325 | /* Real time clock on external device module */ | |
| 326 | /* dobble UART on external device module */ | |
| 327 | /* Data flash on external device module */ | |
| 328 | /* Boot flash on external device module */ | |
| a20b27a3 | 329 | /*******************************************************/ |
| 6d0f6bcf JCPV |
330 | #define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ |
| 331 | #define CONFIG_SYS_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */ | |
| a20b27a3 | 332 | |
| bfc81252 WD |
333 | #undef MARVEL_STANDARD_CFG |
| 334 | #ifndef MARVEL_STANDARD_CFG | |
| a20b27a3 | 335 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ |
| 6d0f6bcf JCPV |
336 | #define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers will be mapped here */ |
| 337 | /*#define CONFIG_SYS_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */ | |
| 338 | #define CONFIG_SYS_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */ | |
| 339 | ||
| 340 | #define CONFIG_SYS_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */ | |
| 341 | #define CONFIG_SYS_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */ | |
| 342 | #define CONFIG_SYS_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */ | |
| 343 | #define CONFIG_SYS_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */ | |
| 344 | #define CONFIG_SYS_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */ | |
| 345 | ||
| 346 | #define CONFIG_SYS_BOOT_SIZE _16M /* cpci750 flash 0 */ | |
| 347 | #define CONFIG_SYS_DEV0_SIZE _16M /* cpci750 flash 1 */ | |
| 348 | #define CONFIG_SYS_DEV1_SIZE _16M /* cpci750 flash 2 */ | |
| 349 | #define CONFIG_SYS_DEV2_SIZE _16M /* cpci750 flash 3 */ | |
| 350 | #define CONFIG_SYS_DEV3_SIZE _16M /* cpci750 nvram/can */ | |
| a20b27a3 SR |
351 | |
| 352 | /*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ | |
| 353 | #endif | |
| 354 | ||
| 355 | /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */ | |
| 6d0f6bcf JCPV |
356 | #define CONFIG_SYS_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */ |
| 357 | #define CONFIG_SYS_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */ | |
| 358 | #define CONFIG_SYS_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */ | |
| 359 | #define CONFIG_SYS_DEV3_PAR 0x8FCFFFFF /* nvram/can */ | |
| 360 | #define CONFIG_SYS_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */ | |
| a20b27a3 | 361 | |
| bfc81252 WD |
362 | /* c 4 a 8 2 4 1 c */ |
| 363 | /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ | |
| efe2a4d5 WD |
364 | /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ |
| 365 | /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */ | |
| 366 | /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */ | |
| a20b27a3 SR |
367 | |
| 368 | ||
| 369 | /* MPP Control MV64360 Appendix P P. 632*/ | |
| 6d0f6bcf JCPV |
370 | #define CONFIG_SYS_MPP_CONTROL_0 0x00002222 /* */ |
| 371 | #define CONFIG_SYS_MPP_CONTROL_1 0x11110000 /* */ | |
| 372 | #define CONFIG_SYS_MPP_CONTROL_2 0x11111111 /* */ | |
| 373 | #define CONFIG_SYS_MPP_CONTROL_3 0x00001111 /* */ | |
| 374 | /* #define CONFIG_SYS_SERIAL_PORT_MUX 0x00000102*/ /* */ | |
| a20b27a3 SR |
375 | |
| 376 | ||
| 6d0f6bcf | 377 | #define CONFIG_SYS_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/ |
| a20b27a3 SR |
378 | |
| 379 | /* setup new config_value for MV64360 DDR-RAM To_do !! */ | |
| 6d0f6bcf JCPV |
380 | /*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */ |
| 381 | /*# define CONFIG_SYS_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */ | |
| a20b27a3 SR |
382 | /* GB has high prio. |
| 383 | idma has low prio | |
| 384 | MPSC has low prio | |
| 385 | pci has low prio 1 and 2 | |
| 386 | cpu has high prio | |
| 387 | Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices | |
| 388 | ECC disable | |
| 389 | non registered DRAM */ | |
| 390 | /* 31:26 25:22 21:20 19 18 17 16 */ | |
| bfc81252 | 391 | /* 100001 0000 010 0 0 0 0 */ |
| a20b27a3 SR |
392 | /* refresh_count=0x400 |
| 393 | phisical interleaving disable | |
| 394 | virtual interleaving enable */ | |
| 395 | /* 15 14 13:0 */ | |
| bfc81252 | 396 | /* 0 1 0x400 */ |
| 6d0f6bcf | 397 | # define CONFIG_SYS_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/ |
| a20b27a3 SR |
398 | |
| 399 | ||
| 400 | /*----------------------------------------------------------------------- | |
| 401 | * PCI stuff | |
| 402 | *----------------------------------------------------------------------- | |
| 403 | */ | |
| 404 | ||
| bfc81252 WD |
405 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
| 406 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
| 407 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
| a20b27a3 | 408 | |
| bfc81252 WD |
409 | #define CONFIG_PCI /* include pci support */ |
| 410 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
| 411 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 412 | #define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ | |
| a20b27a3 SR |
413 | |
| 414 | /* PCI MEMORY MAP section */ | |
| 6d0f6bcf JCPV |
415 | #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 |
| 416 | #define CONFIG_SYS_PCI0_MEM_SIZE _128M | |
| 417 | #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 | |
| 418 | #define CONFIG_SYS_PCI1_MEM_SIZE _128M | |
| a20b27a3 | 419 | |
| 6d0f6bcf JCPV |
420 | #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) |
| 421 | #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) | |
| a20b27a3 | 422 | |
| a20b27a3 | 423 | /* PCI I/O MAP section */ |
| 6d0f6bcf JCPV |
424 | #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 |
| 425 | #define CONFIG_SYS_PCI0_IO_SIZE _16M | |
| 426 | #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 | |
| 427 | #define CONFIG_SYS_PCI1_IO_SIZE _16M | |
| a20b27a3 | 428 | |
| 6d0f6bcf JCPV |
429 | #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) |
| 430 | #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 | |
| 431 | #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) | |
| 432 | #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 | |
| a20b27a3 | 433 | |
| 6d0f6bcf | 434 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) |
| a7b9fb91 | 435 | |
| a20b27a3 | 436 | #if defined (CONFIG_750CX) |
| 6d0f6bcf | 437 | #define CONFIG_SYS_PCI_IDSEL 0x0 |
| a20b27a3 | 438 | #else |
| 6d0f6bcf | 439 | #define CONFIG_SYS_PCI_IDSEL 0x30 |
| a20b27a3 SR |
440 | #endif |
| 441 | ||
| 442 | /*----------------------------------------------------------------------- | |
| 443 | * IDE/ATA stuff | |
| 444 | *----------------------------------------------------------------------- | |
| 445 | */ | |
| bfc81252 WD |
446 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
| 447 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
| 448 | #define CONFIG_IDE_RESET /* no reset for ide supported */ | |
| 449 | #define CONFIG_IDE_PREINIT /* check for units */ | |
| a20b27a3 | 450 | |
| 6d0f6bcf JCPV |
451 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 1 IDE busses */ |
| 452 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */ | |
| a20b27a3 | 453 | |
| 6d0f6bcf JCPV |
454 | #define CONFIG_SYS_ATA_BASE_ADDR 0 |
| 455 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0 | |
| 456 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0 | |
| a20b27a3 | 457 | |
| 6d0f6bcf JCPV |
458 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
| 459 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
| 460 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
| a20b27a3 SR |
461 | |
| 462 | ||
| 463 | /*---------------------------------------------------------------------- | |
| 464 | * Initial BAT mappings | |
| 465 | */ | |
| 466 | ||
| 467 | /* NOTES: | |
| 468 | * 1) GUARDED and WRITE_THRU not allowed in IBATS | |
| 469 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT | |
| 470 | */ | |
| 471 | ||
| 472 | /* SDRAM */ | |
| 6d0f6bcf JCPV |
473 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 474 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 475 | #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 476 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| a20b27a3 SR |
477 | |
| 478 | /* init ram */ | |
| 6d0f6bcf JCPV |
479 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 480 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) | |
| 481 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 482 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| a20b27a3 SR |
483 | |
| 484 | /* PCI0, PCI1 in one BAT */ | |
| 6d0f6bcf JCPV |
485 | #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS |
| 486 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
| 487 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
| 488 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| a20b27a3 SR |
489 | |
| 490 | /* GT regs, bootrom, all the devices, PCI I/O */ | |
| 6d0f6bcf JCPV |
491 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) |
| 492 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) | |
| 493 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) | |
| 494 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| a20b27a3 SR |
495 | |
| 496 | /* | |
| 497 | * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7) | |
| 498 | * IBAT4 and DBAT4 | |
| 499 | * FIXME: ingo disable BATs for Linux Kernel | |
| 500 | */ | |
| 501 | #undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */ | |
| 502 | /*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */ | |
| 503 | ||
| 504 | #ifdef SETUP_HIGH_BATS_FX750 | |
| 6d0f6bcf JCPV |
505 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 506 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 507 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 508 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| a20b27a3 SR |
509 | |
| 510 | /* IBAT5 and DBAT5 */ | |
| 6d0f6bcf JCPV |
511 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 512 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 513 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 514 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| a20b27a3 SR |
515 | |
| 516 | /* IBAT6 and DBAT6 */ | |
| 6d0f6bcf JCPV |
517 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 518 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 519 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 520 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| a20b27a3 SR |
521 | |
| 522 | /* IBAT7 and DBAT7 */ | |
| 6d0f6bcf JCPV |
523 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 524 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 525 | #define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 526 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| a20b27a3 SR |
527 | |
| 528 | #else /* set em out of range for Linux !!!!!!!!!!! */ | |
| 6d0f6bcf JCPV |
529 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 530 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 531 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 532 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| a20b27a3 SR |
533 | |
| 534 | /* IBAT5 and DBAT5 */ | |
| 6d0f6bcf JCPV |
535 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 536 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 537 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 538 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT4U | |
| a20b27a3 SR |
539 | |
| 540 | /* IBAT6 and DBAT6 */ | |
| 6d0f6bcf JCPV |
541 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 542 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 543 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 544 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT4U | |
| a20b27a3 SR |
545 | |
| 546 | /* IBAT7 and DBAT7 */ | |
| 6d0f6bcf JCPV |
547 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 548 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 549 | #define CONFIG_SYS_DBAT7L (CONFIG_SYS_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 550 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT4U | |
| a20b27a3 SR |
551 | |
| 552 | #endif | |
| 553 | /* FIXME: ingo end: disable BATs for Linux Kernel */ | |
| 554 | ||
| 555 | /* I2C addresses for the two DIMM SPD chips */ | |
| 556 | #define DIMM0_I2C_ADDR 0x51 | |
| 557 | #define DIMM1_I2C_ADDR 0x52 | |
| 558 | ||
| 559 | /* | |
| 560 | * For booting Linux, the board info and command line data | |
| 561 | * have to be in the first 8 MB of memory, since this is | |
| 562 | * the maximum mapped by the Linux kernel during initialization. | |
| 563 | */ | |
| 6d0f6bcf | 564 | #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ |
| a20b27a3 SR |
565 | |
| 566 | /*----------------------------------------------------------------------- | |
| 567 | * FLASH organization | |
| 568 | */ | |
| 6d0f6bcf | 569 | #define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ |
| a20b27a3 | 570 | |
| 6d0f6bcf JCPV |
571 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 572 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
| 573 | #define CONFIG_SYS_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */ | |
| a20b27a3 SR |
574 | |
| 575 | #if 0 | |
| 5a1aceb0 | 576 | #define CONFIG_ENV_IS_IN_FLASH |
| 0e8d1586 JCPV |
577 | #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ |
| 578 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 579 | #define CONFIG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */ | |
| 6d0f6bcf | 580 | /* #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) */ |
| a20b27a3 SR |
581 | #endif |
| 582 | ||
| bb1f8b4f | 583 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
| 6d0f6bcf JCPV |
584 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 |
| 585 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
| 586 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x050 | |
| 0e8d1586 JCPV |
587 | #define CONFIG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */ |
| 588 | #define CONFIG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/ | |
| a20b27a3 | 589 | |
| 6d0f6bcf JCPV |
590 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */ |
| 591 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
| 592 | #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-0x40) | |
| a20b27a3 SR |
593 | |
| 594 | /*----------------------------------------------------------------------- | |
| 595 | * Cache Configuration | |
| 596 | */ | |
| 6d0f6bcf | 597 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
| 49cf7e8e | 598 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 599 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| a20b27a3 SR |
600 | #endif |
| 601 | ||
| 602 | /*----------------------------------------------------------------------- | |
| 603 | * L2CR setup -- make sure this is right for your board! | |
| 604 | * look in include/mpc74xx.h for the defines used here | |
| 605 | */ | |
| 606 | ||
| 6d0f6bcf JCPV |
607 | /*#define CONFIG_SYS_L2*/ |
| 608 | #undef CONFIG_SYS_L2 | |
| a20b27a3 SR |
609 | |
| 610 | /* #ifdef CONFIG_750CX*/ | |
| 611 | #if defined (CONFIG_750CX) || defined (CONFIG_750FX) | |
| 612 | #define L2_INIT 0 | |
| 613 | #else | |
| bfc81252 | 614 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
| a20b27a3 SR |
615 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
| 616 | #endif | |
| 617 | ||
| 618 | #define L2_ENABLE (L2_INIT | L2CR_L2E) | |
| 619 | ||
| 6d0f6bcf | 620 | #define CONFIG_SYS_BOARD_ASM_INIT 1 |
| a20b27a3 | 621 | |
| 58f10460 | 622 | #define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) |
| 0738e24e RA |
623 | #define CPCI750_ECC_TEST (((in8(0xf0300000) & 0x02) == 0) ? 1 : 0) |
| 624 | #define CONFIG_SYS_PLD_VER 0xf0e00000 | |
| 58f10460 | 625 | |
| a20b27a3 | 626 | #endif /* __CONFIG_H */ |