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Add common (with Linux) MTD partition scheme and "mtdparts" command
[people/ms/u-boot.git] / include / configs / CPCI750.h
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a20b27a3
SR		 1/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28/*************************************************************************
29 * (c) 2004 esd gmbh Hannover
30 *
31 *
32 * from db64360.h file
33 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
34 *
35 ************************************************************************/
36
37
38#ifndef __CONFIG_H
39#define __CONFIG_H
40
a20b27a3
SR		 41/* This define must be before the core.h include */
42#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
43
44#ifndef __ASSEMBLY__
45#include <../board/Marvell/include/core.h>
46#endif
47/*-----------------------------------------------------*/
48
49#include "../board/esd/cpci750/local.h"
50
51/*
52 * High Level Configuration Options
53 * (easy to change)
54 */
55
56#define CONFIG_750FX /* we have a 750FX (override local.h) */
57
58#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
59
60#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
61
62#undef CONFIG_ECC /* enable ECC support */
63
64/* which initialization functions to call for this board */
65#define CONFIG_MISC_INIT_R
66#define CONFIG_BOARD_PRE_INIT
67#define CONFIG_BOARD_EARLY_INIT_F 1
68
69#define CFG_BOARD_NAME "CPCI750"
70#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX"
71
72/*#define CFG_HUSH_PARSER*/
73#undef CFG_HUSH_PARSER
74
75#define CFG_PROMPT_HUSH_PS2 "> "
76
77/* Define which ETH port will be used for connecting the network */
78#define CFG_ETH_PORT ETH_0
79
80/*
81 * The following defines let you select what serial you want to use
82 * for your console driver.
83 *
84 * what to do:
85 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
86 * cable onto the second DUART channel, change the CFG_DUART port from 1
87 * to 0 below.
88 *
89 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
90 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
91 */
92#define CONFIG_MPSC
93#define CONFIG_MPSC_PORT 0
94
95/* to change the default ethernet port, use this define (options: 0, 1, 2) */
96#define CONFIG_NET_MULTI
97#define MV_ETH_DEVS 1
98#define CONFIG_ETHER_PORT 0
99
100#undef CONFIG_ETHER_PORT_MII /* use RMII */
101
102#define CONFIG_BOOTDELAY 5 /* autoboot disabled */
103
104#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
105
106#define CONFIG_ZERO_BOOTDELAY_CHECK
107
108
109#undef CONFIG_BOOTARGS
110
111/* -----------------------------------------------------------------------------
112 * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
113 */
114
115#define CONFIG_IPADDR "192.168.0.185"
116
117#define CONFIG_SERIAL "AA000001"
118#define CONFIG_SERVERIP "10.0.0.79"
119#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s"
120
121#define CONFIG_TESTDRAMDATA y
122#define CONFIG_TESTDRAMADDRESS n
123#define CONFIG_TESETDRAMWALK n
124
125/* ----------------------------------------------------------------------------- */
126
127
128#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
129#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
130
131#undef CONFIG_WATCHDOG /* watchdog disabled */
132#undef CONFIG_ALTIVEC /* undef to disable */
133
134#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
135 CONFIG_BOOTP_BOOTFILESIZE)
136
137
138#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
139 | CFG_CMD_ASKENV \
140 | CFG_CMD_I2C \
141 | CFG_CMD_CACHE \
142 | CFG_CMD_EEPROM \
143 | CFG_CMD_PCI \
144 | CFG_CMD_ELF \
145 | CFG_CMD_DATE \
efe2a4d5
WD		 146 | CFG_CMD_NET \
147 | CFG_CMD_PING \
148 | CFG_CMD_IDE \
149 | CFG_CMD_FAT \
150 | CFG_CMD_EXT2 \
a20b27a3
SR		 151 )
152
153#define CONFIG_DOS_PARTITION
154
155/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
156#include <cmd_confdefs.h>
157
158/*
159 * Miscellaneous configurable options
160 */
161#define CFG_I2C_EEPROM_ADDR_LEN 2
162#define CFG_I2C_MULTI_EEPROMS
163#define CFG_I2C_SPEED 80000 /* I2C speed default */
164
165#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */
166#define CFG_LONGHELP /* undef to save memory */
167#define CFG_PROMPT "=> " /* Monitor Command Prompt */
168#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
169#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
170#else
171#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
172#endif
173#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
174#define CFG_MAXARGS 16 /* max number of command args */
175#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
176
177/*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */
178/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
179/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */
180
181/*
182#define CFG_DRAM_TEST
183 * DRAM tests
184 * CFG_DRAM_TEST - enables the following tests.
185 *
186 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
187 * Environment variable 'test_dram_data' must be
188 * set to 'y'.
189 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
190 * addressable. Environment variable
191 * 'test_dram_address' must be set to 'y'.
192 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
193 * This test takes about 6 minutes to test 64 MB.
194 * Environment variable 'test_dram_walk' must be
195 * set to 'y'.
196 */
197#define CFG_DRAM_TEST
198#if defined(CFG_DRAM_TEST)
199#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
200/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
201#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
202#define CFG_DRAM_TEST_DATA
203#define CFG_DRAM_TEST_ADDRESS
204#define CFG_DRAM_TEST_WALK
205#endif /* CFG_DRAM_TEST */
206
207#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
208#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
209
210#define CFG_LOAD_ADDR 0x00300000 /* default load address */
211
212#define CFG_HZ 1000 /* decr freq: 1ms ticks */
213#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
214#define CFG_BUS_CLK CFG_BUS_HZ
215
216#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
217
218#define CFG_TCLK 133000000
219
220/*#define CFG_750FX_HID0 0x8000c084*/
221#define CFG_750FX_HID0 0x80008484
222#define CFG_750FX_HID1 0x54800000
223#define CFG_750FX_HID2 0x00000000
224
225/*
226 * Low Level Configuration Settings
227 * (address mappings, register initial values, etc.)
228 * You should know what you are doing if you make changes here.
229 */
230
231/*-----------------------------------------------------------------------
232 * Definitions for initial stack pointer and data area
233 */
234
235 /*
236 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
237 * To an unused memory region. The stack will remain in cache until RAM
238 * is initialized
239*/
240#undef CFG_INIT_RAM_LOCK
241/* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */
242/* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */
243#define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */
244#define CFG_INIT_RAM_END 0x1000
245#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
246#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
247
248#define RELOCATE_INTERNAL_RAM_ADDR
249#ifdef RELOCATE_INTERNAL_RAM_ADDR
250/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/
251#define CFG_INTERNAL_RAM_ADDR 0xf1080000
252#endif
253
254/*-----------------------------------------------------------------------
255 * Start addresses for the final memory configuration
256 * (Set up by the startup code)
257 * Please note that CFG_SDRAM_BASE _must_ start at 0
258 */
259#define CFG_SDRAM_BASE 0x00000000
260/* Dummies for BAT 4-7 */
261#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
262#define CFG_SDRAM2_BASE 0x20000000
263#define CFG_SDRAM3_BASE 0x30000000
264#define CFG_SDRAM4_BASE 0x40000000
265#define CFG_RESET_ADDRESS 0xfff00100
266#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
267#define CFG_MONITOR_BASE 0xfff00000
268#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */
269
270/*-----------------------------------------------------------------------
271 * FLASH related
272 *----------------------------------------------------------------------*/
273
274#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
275#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
276#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
277#define CFG_FLASH_INCREMENT 0x01000000 /* there is only one bank */
278#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
279#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
280#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */
281
282/* areas to map different things with the GT in physical space */
283#define CFG_DRAM_BANKS 4
284
285/* What to put in the bats. */
286#define CFG_MISC_REGION_BASE 0xf0000000
287
288/* Peripheral Device section */
289
290/*******************************************************/
291/* We have on the cpci750 Board : */
292/* GT-Chipset Register Area */
293/* GT-Chipset internal SRAM 256k */
294/* SRAM on external device module */
295/* Real time clock on external device module */
296/* dobble UART on external device module */
297/* Data flash on external device module */
298/* Boot flash on external device module */
299/*******************************************************/
300#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
301#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */
302
303#undef MARVEL_STANDARD_CFG
304#ifndef MARVEL_STANDARD_CFG
305/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
306#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
307/*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */
308#define CFG_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */
309
310#define CFG_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */
311#define CFG_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */
312#define CFG_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */
313#define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */
314#define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */
315
316#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */
317#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */
318#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */
319#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */
320#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */
321
322/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
323#endif
324
325/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
326#define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */
327#define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */
328#define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */
329#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */
330#define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */
331
efe2a4d5
WD		 332 /* c 4 a 8 2 4 1 c */
333 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
334 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
335 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
336 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
a20b27a3
SR		 337
338
339/* MPP Control MV64360 Appendix P P. 632*/
340#define CFG_MPP_CONTROL_0 0x00002222 /* */
341#define CFG_MPP_CONTROL_1 0x11110000 /* */
342#define CFG_MPP_CONTROL_2 0x11111111 /* */
343#define CFG_MPP_CONTROL_3 0x00001111 /* */
344/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */
345
346
347#define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/
348
349/* setup new config_value for MV64360 DDR-RAM To_do !! */
350/*# define CFG_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */
351/*# define CFG_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */
352 /* GB has high prio.
353 idma has low prio
354 MPSC has low prio
355 pci has low prio 1 and 2
356 cpu has high prio
357 Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
358 ECC disable
359 non registered DRAM */
360 /* 31:26 25:22 21:20 19 18 17 16 */
361 /* 100001 0000 010 0 0 0 0 */
362 /* refresh_count=0x400
363 phisical interleaving disable
364 virtual interleaving enable */
365 /* 15 14 13:0 */
366 /* 0 1 0x400 */
367# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
368
369
370/*-----------------------------------------------------------------------
371 * PCI stuff
372 *-----------------------------------------------------------------------
373 */
374
375#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
376#define PCI_HOST_FORCE 1 /* configure as pci host */
377#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
378
379#define CONFIG_PCI /* include pci support */
380#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
381#define CONFIG_PCI_PNP /* do pci plug-and-play */
382#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
383
384/* PCI MEMORY MAP section */
385#define CFG_PCI0_MEM_BASE 0x80000000
386#define CFG_PCI0_MEM_SIZE _128M
387#define CFG_PCI1_MEM_BASE 0x88000000
388#define CFG_PCI1_MEM_SIZE _128M
389
390#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
391#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
392
a20b27a3
SR		 393/* PCI I/O MAP section */
394#define CFG_PCI0_IO_BASE 0xfa000000
395#define CFG_PCI0_IO_SIZE _16M
396#define CFG_PCI1_IO_BASE 0xfb000000
397#define CFG_PCI1_IO_SIZE _16M
398
399#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
400#define CFG_PCI0_IO_SPACE_PCI 0x00000000
401#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
402#define CFG_PCI1_IO_SPACE_PCI 0x00000000
403
404#if defined (CONFIG_750CX)
405#define CFG_PCI_IDSEL 0x0
406#else
407#define CFG_PCI_IDSEL 0x30
408#endif
409
410/*-----------------------------------------------------------------------
411 * IDE/ATA stuff
412 *-----------------------------------------------------------------------
413 */
414#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
415#undef CONFIG_IDE_LED /* no led for ide supported */
416#define CONFIG_IDE_RESET /* no reset for ide supported */
417#define CONFIG_IDE_PREINIT /* check for units */
418
419#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */
420#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
421
422#define CFG_ATA_BASE_ADDR 0
423#define CFG_ATA_IDE0_OFFSET 0
424#define CFG_ATA_IDE1_OFFSET 0
425
426#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
427#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
428#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
429
430
431/*----------------------------------------------------------------------
432 * Initial BAT mappings
433 */
434
435/* NOTES:
436 * 1) GUARDED and WRITE_THRU not allowed in IBATS
437 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
438 */
439
440/* SDRAM */
441#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
442#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
443#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
444#define CFG_DBAT0U CFG_IBAT0U
445
446/* init ram */
447#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
448#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
449#define CFG_DBAT1L CFG_IBAT1L
450#define CFG_DBAT1U CFG_IBAT1U
451
452/* PCI0, PCI1 in one BAT */
453#define CFG_IBAT2L BATL_NO_ACCESS
454#define CFG_IBAT2U CFG_DBAT2U
455#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
456#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
457
458/* GT regs, bootrom, all the devices, PCI I/O */
459#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
460#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
461#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
462#define CFG_DBAT3U CFG_IBAT3U
463
464/*
465 * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
466 * IBAT4 and DBAT4
467 * FIXME: ingo disable BATs for Linux Kernel
468 */
469#undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */
470/*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */
471
472#ifdef SETUP_HIGH_BATS_FX750
473#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
474#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
475#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
476#define CFG_DBAT4U CFG_IBAT4U
477
478/* IBAT5 and DBAT5 */
479#define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
480#define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
481#define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
482#define CFG_DBAT5U CFG_IBAT5U
483
484/* IBAT6 and DBAT6 */
485#define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
486#define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
487#define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
488#define CFG_DBAT6U CFG_IBAT6U
489
490/* IBAT7 and DBAT7 */
491#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
492#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
493#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
494#define CFG_DBAT7U CFG_IBAT7U
495
496#else /* set em out of range for Linux !!!!!!!!!!! */
497#define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
498#define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
499#define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
500#define CFG_DBAT4U CFG_IBAT4U
501
502/* IBAT5 and DBAT5 */
503#define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
504#define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
505#define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
506#define CFG_DBAT5U CFG_IBAT4U
507
508/* IBAT6 and DBAT6 */
509#define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
510#define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
511#define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
512#define CFG_DBAT6U CFG_IBAT4U
513
514/* IBAT7 and DBAT7 */
515#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
516#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
517#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
518#define CFG_DBAT7U CFG_IBAT4U
519
520#endif
521/* FIXME: ingo end: disable BATs for Linux Kernel */
522
523/* I2C addresses for the two DIMM SPD chips */
524#define DIMM0_I2C_ADDR 0x51
525#define DIMM1_I2C_ADDR 0x52
526
527/*
528 * For booting Linux, the board info and command line data
529 * have to be in the first 8 MB of memory, since this is
530 * the maximum mapped by the Linux kernel during initialization.
531 */
532#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
533
534/*-----------------------------------------------------------------------
535 * FLASH organization
536 */
537#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */
538
539#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
540#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
541#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
542
543#if 0
544#define CFG_ENV_IS_IN_FLASH 0
545#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
546#define CFG_ENV_SECT_SIZE 0x10000
547#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
548/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
549#endif
550
551#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
552#define CFG_EEPROM_PAGE_WRITE_BITS 5
553#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
554#define CFG_I2C_EEPROM_ADDR 0x050
555#define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */
556#define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/
557
558#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
559#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
560#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
561
562/*-----------------------------------------------------------------------
563 * Cache Configuration
564 */
565#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
566#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
567#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
568#endif
569
570/*-----------------------------------------------------------------------
571 * L2CR setup -- make sure this is right for your board!
572 * look in include/mpc74xx.h for the defines used here
573 */
574
575/*#define CFG_L2*/
576#undef CFG_L2
577
578/* #ifdef CONFIG_750CX*/
579#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
580#define L2_INIT 0
581#else
582#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
583 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
584#endif
585
586#define L2_ENABLE (L2_INIT | L2CR_L2E)
587
588/*
589 * Internal Definitions
590 *
591 * Boot Flags
592 */
593#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
594#define BOOTFLAG_WARM 0x02 /* Software reboot */
595
596#define CFG_BOARD_ASM_INIT 1
597
598#endif /* __CONFIG_H */
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