[people/ms/u-boot.git] / include / configs / CPCIISER4.h

/*
 * (C) Copyright 2001-2003
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_CPCIISER4	1	/* ...on a CPCIISER4 board	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND	"bootm fff00000"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EEPROM


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#define CONFIG_SYS_EXT_SERIAL_CLOCK	1843200	 /* use external serial clock	*/

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404	/* PCI Device ID: CPCI-ISER4	*/
#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CONFIG_SYS_PCI_PTM1MS	0xff000001	/* 16MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CONFIG_SYS_PCI_PTM2LA	0xffe00000	/* point to flash		*/
#define CONFIG_SYS_PCI_PTM2MS	0xffe00001	/* 2MB, enable			*/
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_HARD_I2C			/* I2C with hardware support */
#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
				   /* total size of a CAT24WC08 is 1024 bytes */

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFFF00000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CONFIG_SYS_EBC_PB0AP		0x92015480
#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Uart 8bit) initialization					*/
#define CONFIG_SYS_EBC_PB1AP		0x01000480  /* TWT=2,TH=2,no Ready,BEM=0,SOR=1	*/
#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 2 (Uart 32bit) initialization					*/
#define CONFIG_SYS_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
#define CONFIG_SYS_EBC_PB2CR		0xF011C000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */

/* Memory Bank 3 (FPGA Reset) initialization					*/
#define CONFIG_SYS_EBC_PB3AP		0x010004C0  /* no Ready, BEM=1			*/
#define CONFIG_SYS_EBC_PB3CR		0xF021A000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_DCACHE_CS	7	/* use cs # 7 for data cache memory    */
#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000	/* Size of used area in RAM	       */
#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b	1	/*
2a9e02ea	2	* (C) Copyright 2001-2003
c609719b WD	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
c609719b WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1	21	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c609719b WD	22	#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */
c609719b WD	23
2ae18241 WD	24	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	25
c837dcb1	26	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c609719b	27
c837dcb1	28	#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
c609719b WD	29
	30	#define CONFIG_BAUDRATE 9600
	31	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	32
	33	#undef CONFIG_BOOTARGS
	34	#define CONFIG_BOOTCOMMAND "bootm fff00000"
	35
	36	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	37	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
c609719b	38
96e21f86	39	#define CONFIG_PPC4xx_EMAC
c609719b	40	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	41	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	42	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
c609719b	43
c609719b	44
11799434 JL	45	/*
	46	* BOOTP options
	47	*/
	48	#define CONFIG_BOOTP_BOOTFILESIZE
	49	#define CONFIG_BOOTP_BOOTPATH
	50	#define CONFIG_BOOTP_GATEWAY
	51	#define CONFIG_BOOTP_HOSTNAME
	52
	53
	54	/*
	55	* BOOTP options
	56	*/
	57	#define CONFIG_BOOTP_BOOTFILESIZE
	58	#define CONFIG_BOOTP_BOOTPATH
	59	#define CONFIG_BOOTP_GATEWAY
	60	#define CONFIG_BOOTP_HOSTNAME
	61
	62
49cf7e8e JL	63	/*
	64	* Command line configuration.
	65	*/
	66	#include <config_cmd_default.h>
	67
	68	#define CONFIG_CMD_PCI
	69	#define CONFIG_CMD_IRQ
	70	#define CONFIG_CMD_MII
	71	#define CONFIG_CMD_ELF
	72	#define CONFIG_CMD_EEPROM
	73
c609719b WD	74
	75	#undef CONFIG_WATCHDOG /* watchdog disabled */
	76
c837dcb1	77	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b WD	78
	79	/*
	80	* Miscellaneous configurable options
	81	*/
6d0f6bcf JCPV	82	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	83	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
49cf7e8e	84	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	85	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	86	#else
6d0f6bcf	87	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b	88	#endif
6d0f6bcf JCPV	89	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	90	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	91	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b	92
6d0f6bcf	93	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b	94
6d0f6bcf JCPV	95	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	96	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c609719b	97
550650dd SR	98	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	99	#define CONFIG_SYS_NS16550
	100	#define CONFIG_SYS_NS16550_SERIAL
	101	#define CONFIG_SYS_NS16550_REG_SIZE 1
	102	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	103
6d0f6bcf	104	#define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */
c609719b WD	105
c609719b WD	106	/* The following table includes the supported baudrates */
6d0f6bcf	107	#define CONFIG_SYS_BAUDRATE_TABLE \
8bde7f77 WD	108	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	109	57600, 115200, 230400, 460800, 921600 }
c609719b	110
6d0f6bcf JCPV	111	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	112	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
c609719b	113
6d0f6bcf	114	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b WD	115
	116	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	117
	118	/*-----------------------------------------------------------------------
	119	* PCI stuff
	120	*-----------------------------------------------------------------------
	121	*/
c837dcb1 WD	122	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	123	#define PCI_HOST_FORCE 1 /* configure as pci host */
	124	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	125
	126	#define CONFIG_PCI /* include pci support */
842033e6	127	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
c837dcb1 WD	128	#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
	129	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	130	/* resource configuration */
	131
6d0f6bcf JCPV	132	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	133	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */
	134	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	135	#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */
	136	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	137	#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */
	138	#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */
	139	#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
c609719b WD	140
	141	/*-----------------------------------------------------------------------
	142	* Start addresses for the final memory configuration
	143	* (Set up by the startup code)
6d0f6bcf	144	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	145	*/
6d0f6bcf JCPV	146	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	147	#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
	148	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	149	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	150	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
c609719b WD	151
	152	/*
	153	* For booting Linux, the board info and command line data
	154	* have to be in the first 8 MB of memory, since this is
	155	* the maximum mapped by the Linux kernel during initialization.
	156	*/
6d0f6bcf	157	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	158	/*-----------------------------------------------------------------------
	159	* FLASH organization
	160	*/
6d0f6bcf JCPV	161	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	162	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
c609719b	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	165	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b	166
6d0f6bcf JCPV	167	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	168	#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	169	#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	170	/*
	171	* The following defines are added for buggy IOP480 byte interface.
	172	* All other boards should use the standard values (CPCI405 etc.)
	173	*/
6d0f6bcf JCPV	174	#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
	175	#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
	176	#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	177
6d0f6bcf	178	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b WD	179
	180	/*-----------------------------------------------------------------------
	181	* I2C EEPROM (CAT24WC08) for environment
	182	*/
	183	#define CONFIG_HARD_I2C /* I2C with hardware support */
d0b0dcaa	184	#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
6d0f6bcf JCPV	185	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	186	#define CONFIG_SYS_I2C_SLAVE 0x7F
c609719b	187
6d0f6bcf JCPV	188	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
6d0f6bcf JCPV	189	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1	190	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	191	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
6d0f6bcf JCPV	192	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
c609719b	193	/* 16 byte page write mode using*/
c837dcb1	194	/* last 4 bits of the address */
6d0f6bcf	195	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
c609719b	196
bb1f8b4f	197	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	198	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	199	#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
8bde7f77	200	/* total size of a CAT24WC08 is 1024 bytes */
c609719b	201
c609719b WD	202	/*
	203	* Init Memory Controller:
	204	*
	205	* BR0/1 and OR0/1 (FLASH)
	206	*/
	207
	208	#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
	209	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	210
	211	/*-----------------------------------------------------------------------
	212	* External Bus Controller (EBC) Setup
	213	*/
	214
c837dcb1	215	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	216	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	217	#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	218
c837dcb1	219	/* Memory Bank 1 (Uart 8bit) initialization */
6d0f6bcf JCPV	220	#define CONFIG_SYS_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */
6d0f6bcf JCPV	221	#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c609719b	222
c837dcb1	223	/* Memory Bank 2 (Uart 32bit) initialization */
6d0f6bcf JCPV	224	#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
6d0f6bcf JCPV	225	#define CONFIG_SYS_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
c609719b	226
c837dcb1	227	/* Memory Bank 3 (FPGA Reset) initialization */
6d0f6bcf JCPV	228	#define CONFIG_SYS_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */
6d0f6bcf JCPV	229	#define CONFIG_SYS_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
c609719b WD	230
	231	/*-----------------------------------------------------------------------
	232	* Definitions for initial stack pointer and data area (in DPRAM)
	233	*/
6d0f6bcf JCPV	234	#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
6d0f6bcf JCPV	235	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
553f0982	236	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
25ddd1fb	237	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	238	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b	239
c609719b	240	#endif /* __CONFIG_H */