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384cc687 WD |
1 | /* |
2 | * (C) Copyright 2001-2005 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ | |
37 | #define CONFIG_CPU87 1 /* ...on a CPU87 board */ | |
38 | #define CONFIG_PCI | |
39 | ||
40 | /* | |
41 | * select serial console configuration | |
42 | * | |
43 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
44 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
45 | * for SCC). | |
46 | * | |
47 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
48 | * defined elsewhere (for example, on the cogent platform, there are serial | |
49 | * ports on the motherboard which are used for the serial console - see | |
50 | * cogent/cma101/serial.[ch]). | |
51 | */ | |
52 | #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
53 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
54 | #undef CONFIG_CONS_NONE /* define if console on something else*/ | |
55 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
56 | ||
57 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) | |
58 | #define CONFIG_BAUDRATE 230400 | |
59 | #else | |
60 | #define CONFIG_BAUDRATE 9600 | |
61 | #endif | |
62 | ||
63 | /* | |
64 | * select ethernet configuration | |
65 | * | |
66 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
67 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
68 | * for FCC) | |
69 | * | |
70 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
71 | * defined elsewhere (as for the console), or CFG_CMD_NET must be removed | |
72 | * from CONFIG_COMMANDS to remove support for networking. | |
73 | * | |
74 | */ | |
75 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
76 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
77 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
78 | #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ | |
79 | ||
80 | #define CONFIG_HAS_ETH1 1 | |
81 | #define CONFIG_HAS_ETH2 1 | |
82 | ||
83 | #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) | |
84 | ||
85 | /* | |
86 | * - Rx-CLK is CLK11 | |
87 | * - Tx-CLK is CLK12 | |
88 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
89 | * - Enable Full Duplex in FSMR | |
90 | */ | |
91 | # define CFG_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) | |
92 | # define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) | |
93 | # define CFG_CPMFCR_RAMTYPE 0 | |
94 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
95 | ||
96 | #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) | |
97 | ||
98 | /* | |
99 | * - Rx-CLK is CLK13 | |
100 | * - Tx-CLK is CLK14 | |
101 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) | |
102 | * - Enable Full Duplex in FSMR | |
103 | */ | |
104 | # define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) | |
105 | # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) | |
106 | # define CFG_CPMFCR_RAMTYPE 0 | |
107 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) | |
108 | ||
109 | #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ | |
110 | ||
111 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ | |
112 | #define CONFIG_8260_CLKIN 100000000 /* in Hz */ | |
113 | ||
114 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
115 | ||
116 | #undef CONFIG_CLOCKS_IN_MHZ | |
117 | ||
118 | #define CONFIG_PREBOOT \ | |
119 | "echo; " \ | |
120 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \ | |
121 | "echo" | |
122 | ||
123 | #undef CONFIG_BOOTARGS | |
124 | #define CONFIG_BOOTCOMMAND \ | |
125 | "bootp; " \ | |
126 | "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ | |
127 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ | |
128 | "bootm" | |
129 | ||
130 | /*----------------------------------------------------------------------- | |
131 | * I2C/EEPROM/RTC configuration | |
132 | */ | |
133 | #define CONFIG_SOFT_I2C /* Software I2C support enabled */ | |
134 | ||
135 | # define CFG_I2C_SPEED 50000 | |
136 | # define CFG_I2C_SLAVE 0xFE | |
137 | /* | |
138 | * Software (bit-bang) I2C driver configuration | |
139 | */ | |
140 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ | |
141 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) | |
142 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) | |
143 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) | |
144 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ | |
145 | else iop->pdat &= ~0x00010000 | |
146 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ | |
147 | else iop->pdat &= ~0x00020000 | |
148 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
149 | ||
150 | #define CONFIG_RTC_PCF8563 | |
151 | #define CFG_I2C_RTC_ADDR 0x51 | |
152 | ||
153 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
154 | ||
155 | /*----------------------------------------------------------------------- | |
156 | * Disk-On-Chip configuration | |
157 | */ | |
158 | ||
159 | #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ | |
160 | ||
161 | #define CFG_DOC_SUPPORT_2000 | |
162 | #define CFG_DOC_SUPPORT_MILLENNIUM | |
163 | ||
164 | /*----------------------------------------------------------------------- | |
165 | * Miscellaneous configuration options | |
166 | */ | |
167 | ||
168 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
169 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
170 | ||
171 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) | |
172 | ||
173 | #ifdef CONFIG_PCI | |
174 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
175 | CFG_CMD_BEDBUG | \ | |
176 | CFG_CMD_DATE | \ | |
177 | CFG_CMD_DOC | \ | |
178 | CFG_CMD_EEPROM | \ | |
179 | CFG_CMD_I2C | \ | |
180 | CFG_CMD_PCI) | |
181 | #else /* ! PCI */ | |
182 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
183 | CFG_CMD_BEDBUG | \ | |
184 | CFG_CMD_DATE | \ | |
185 | CFG_CMD_DOC | \ | |
186 | CFG_CMD_EEPROM | \ | |
187 | CFG_CMD_I2C ) | |
188 | #endif /* CONFIG_PCI */ | |
189 | ||
190 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
191 | #include <cmd_confdefs.h> | |
192 | ||
193 | /* | |
194 | * Miscellaneous configurable options | |
195 | */ | |
196 | #define CFG_LONGHELP /* undef to save memory */ | |
197 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
198 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
199 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
200 | #else | |
201 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
202 | #endif | |
203 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
204 | #define CFG_MAXARGS 16 /* max number of command args */ | |
205 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
206 | ||
207 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ | |
208 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
209 | ||
210 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
211 | ||
212 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
213 | ||
214 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
215 | ||
216 | #define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */ | |
217 | ||
218 | #define CONFIG_LOOPW | |
219 | ||
220 | /* | |
221 | * For booting Linux, the board info and command line data | |
222 | * have to be in the first 8 MB of memory, since this is | |
223 | * the maximum mapped by the Linux kernel during initialization. | |
224 | */ | |
225 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
226 | ||
227 | /*----------------------------------------------------------------------- | |
228 | * Flash configuration | |
229 | */ | |
230 | ||
231 | #define CFG_BOOTROM_BASE 0xFF800000 | |
232 | #define CFG_BOOTROM_SIZE 0x00080000 | |
233 | #define CFG_FLASH_BASE 0xFF000000 | |
234 | #define CFG_FLASH_SIZE 0x00800000 | |
235 | ||
236 | /*----------------------------------------------------------------------- | |
237 | * FLASH organization | |
238 | */ | |
239 | #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */ | |
240 | #define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */ | |
241 | ||
242 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
243 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
244 | ||
245 | /*----------------------------------------------------------------------- | |
246 | * Other areas to be mapped | |
247 | */ | |
248 | ||
249 | /* CS3: Dual ported SRAM */ | |
250 | #define CFG_DPSRAM_BASE 0x40000000 | |
251 | #define CFG_DPSRAM_SIZE 0x00100000 | |
252 | ||
253 | /* CS4: DiskOnChip */ | |
254 | #define CFG_DOC_BASE 0xF4000000 | |
255 | #define CFG_DOC_SIZE 0x00100000 | |
256 | ||
257 | /* CS5: FDC37C78 controller */ | |
258 | #define CFG_FDC37C78_BASE 0xF1000000 | |
259 | #define CFG_FDC37C78_SIZE 0x00100000 | |
260 | ||
261 | /* CS6: Board configuration registers */ | |
262 | #define CFG_BCRS_BASE 0xF2000000 | |
263 | #define CFG_BCRS_SIZE 0x00010000 | |
264 | ||
265 | /* CS7: VME Extended Access Range */ | |
266 | #define CFG_VMEEAR_BASE 0x60000000 | |
267 | #define CFG_VMEEAR_SIZE 0x01000000 | |
268 | ||
269 | /* CS8: VME Standard Access Range */ | |
270 | #define CFG_VMESAR_BASE 0xFE000000 | |
271 | #define CFG_VMESAR_SIZE 0x01000000 | |
272 | ||
273 | /* CS9: VME Short I/O Access Range */ | |
274 | #define CFG_VMESIOAR_BASE 0xFD000000 | |
275 | #define CFG_VMESIOAR_SIZE 0x01000000 | |
276 | ||
277 | /*----------------------------------------------------------------------- | |
278 | * Hard Reset Configuration Words | |
279 | * | |
280 | * if you change bits in the HRCW, you must also change the CFG_* | |
281 | * defines for the various registers affected by the HRCW e.g. changing | |
282 | * HRCW_DPPCxx requires you to also change CFG_SIUMCR. | |
283 | */ | |
284 | #if defined(CONFIG_BOOT_ROM) | |
285 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \ | |
286 | HRCW_BPS01 | HRCW_CS10PC01) | |
287 | #else | |
288 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01) | |
289 | #endif | |
290 | ||
291 | /* no slaves so just fill with zeros */ | |
292 | #define CFG_HRCW_SLAVE1 0 | |
293 | #define CFG_HRCW_SLAVE2 0 | |
294 | #define CFG_HRCW_SLAVE3 0 | |
295 | #define CFG_HRCW_SLAVE4 0 | |
296 | #define CFG_HRCW_SLAVE5 0 | |
297 | #define CFG_HRCW_SLAVE6 0 | |
298 | #define CFG_HRCW_SLAVE7 0 | |
299 | ||
300 | /*----------------------------------------------------------------------- | |
301 | * Internal Memory Mapped Register | |
302 | */ | |
303 | #define CFG_IMMR 0xF0000000 | |
304 | ||
305 | /*----------------------------------------------------------------------- | |
306 | * Definitions for initial stack pointer and data area (in DPRAM) | |
307 | */ | |
308 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
309 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
310 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ | |
311 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
312 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
313 | ||
314 | /*----------------------------------------------------------------------- | |
315 | * Start addresses for the final memory configuration | |
316 | * (Set up by the startup code) | |
317 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
318 | * | |
319 | * 60x SDRAM is mapped at CFG_SDRAM_BASE. | |
320 | */ | |
321 | #define CFG_SDRAM_BASE 0x00000000 | |
322 | #define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ | |
323 | #define CFG_MONITOR_BASE TEXT_BASE | |
324 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
325 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ | |
326 | ||
327 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
328 | # define CFG_RAMBOOT | |
329 | #endif | |
330 | ||
331 | #ifdef CONFIG_PCI | |
332 | #define CONFIG_PCI_PNP | |
333 | #define CONFIG_EEPRO100 | |
334 | #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ | |
335 | #endif | |
336 | ||
337 | #if 0 | |
338 | /* environment is in Flash */ | |
339 | #define CFG_ENV_IS_IN_FLASH 1 | |
340 | #ifdef CONFIG_BOOT_ROM | |
341 | # define CFG_ENV_ADDR (CFG_FLASH_BASE+0x70000) | |
342 | # define CFG_ENV_SIZE 0x10000 | |
343 | # define CFG_ENV_SECT_SIZE 0x10000 | |
344 | #endif | |
345 | #else | |
346 | /* environment is in EEPROM */ | |
347 | #define CFG_ENV_IS_IN_EEPROM 1 | |
348 | #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */ | |
349 | #define CFG_I2C_EEPROM_ADDR_LEN 1 | |
350 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
351 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
352 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 | |
353 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ | |
354 | #define CFG_ENV_OFFSET 512 | |
355 | #define CFG_ENV_SIZE (2048 - 512) | |
356 | #endif | |
357 | ||
358 | /* | |
359 | * Internal Definitions | |
360 | * | |
361 | * Boot Flags | |
362 | */ | |
363 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ | |
364 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
365 | ||
366 | ||
367 | /*----------------------------------------------------------------------- | |
368 | * Cache Configuration | |
369 | */ | |
370 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ | |
371 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
372 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
373 | #endif | |
374 | ||
375 | /*----------------------------------------------------------------------- | |
376 | * HIDx - Hardware Implementation-dependent Registers 2-11 | |
377 | *----------------------------------------------------------------------- | |
378 | * HID0 also contains cache control - initially enable both caches and | |
379 | * invalidate contents, then the final state leaves only the instruction | |
380 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
381 | * but Soft reset does not. | |
382 | * | |
383 | * HID1 has only read-only information - nothing to set. | |
384 | */ | |
385 | #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ | |
386 | HID0_DCI|HID0_IFEM|HID0_ABE) | |
387 | #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) | |
388 | #define CFG_HID2 0 | |
389 | ||
390 | /*----------------------------------------------------------------------- | |
391 | * RMR - Reset Mode Register 5-5 | |
392 | *----------------------------------------------------------------------- | |
393 | * turn on Checkstop Reset Enable | |
394 | */ | |
395 | #define CFG_RMR RMR_CSRE | |
396 | ||
397 | /*----------------------------------------------------------------------- | |
398 | * BCR - Bus Configuration 4-25 | |
399 | *----------------------------------------------------------------------- | |
400 | */ | |
401 | #define BCR_APD01 0x10000000 | |
402 | #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ | |
403 | ||
404 | /*----------------------------------------------------------------------- | |
405 | * SIUMCR - SIU Module Configuration 4-31 | |
406 | *----------------------------------------------------------------------- | |
407 | */ | |
408 | #define CFG_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\ | |
409 | SIUMCR_CS10PC01|SIUMCR_BCTLC10) | |
410 | ||
411 | /*----------------------------------------------------------------------- | |
412 | * SYPCR - System Protection Control 4-35 | |
413 | * SYPCR can only be written once after reset! | |
414 | *----------------------------------------------------------------------- | |
415 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable | |
416 | */ | |
417 | #if defined(CONFIG_WATCHDOG) | |
418 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
419 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) | |
420 | #else | |
421 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ | |
422 | SYPCR_SWRI|SYPCR_SWP) | |
423 | #endif /* CONFIG_WATCHDOG */ | |
424 | ||
425 | /*----------------------------------------------------------------------- | |
426 | * TMCNTSC - Time Counter Status and Control 4-40 | |
427 | *----------------------------------------------------------------------- | |
428 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, | |
429 | * and enable Time Counter | |
430 | */ | |
431 | #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
432 | ||
433 | /*----------------------------------------------------------------------- | |
434 | * PISCR - Periodic Interrupt Status and Control 4-42 | |
435 | *----------------------------------------------------------------------- | |
436 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable | |
437 | * Periodic timer | |
438 | */ | |
439 | #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
440 | ||
441 | /*----------------------------------------------------------------------- | |
442 | * SCCR - System Clock Control 9-8 | |
443 | *----------------------------------------------------------------------- | |
444 | * Ensure DFBRG is Divide by 16 | |
445 | */ | |
446 | #define CFG_SCCR SCCR_DFBRG01 | |
447 | ||
448 | /*----------------------------------------------------------------------- | |
449 | * RCCR - RISC Controller Configuration 13-7 | |
450 | *----------------------------------------------------------------------- | |
451 | */ | |
452 | #define CFG_RCCR 0 | |
453 | ||
454 | #define CFG_MIN_AM_MASK 0xC0000000 | |
455 | ||
456 | /* | |
457 | * we use the same values for 32 MB and 128 MB SDRAM | |
458 | * refresh rate = 7.68 uS (100 MHz Bus Clock) | |
459 | */ | |
460 | ||
461 | /*----------------------------------------------------------------------- | |
462 | * MPTPR - Memory Refresh Timer Prescaler Register 10-18 | |
463 | *----------------------------------------------------------------------- | |
464 | */ | |
465 | #define CFG_MPTPR 0x2000 | |
466 | ||
467 | /*----------------------------------------------------------------------- | |
468 | * PSRT - Refresh Timer Register 10-16 | |
469 | *----------------------------------------------------------------------- | |
470 | */ | |
471 | #define CFG_PSRT 0x16 | |
472 | ||
473 | /*----------------------------------------------------------------------- | |
474 | * PSRT - SDRAM Mode Register 10-10 | |
475 | *----------------------------------------------------------------------- | |
476 | */ | |
477 | ||
478 | /* SDRAM initialization values for 8-column chips | |
479 | */ | |
480 | #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ | |
481 | ORxS_BPD_4 |\ | |
482 | ORxS_ROWST_PBI0_A9 |\ | |
483 | ORxS_NUMR_12) | |
484 | ||
485 | #define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ | |
486 | PSDMR_BSMA_A14_A16 |\ | |
487 | PSDMR_SDA10_PBI0_A10 |\ | |
488 | PSDMR_RFRC_7_CLK |\ | |
489 | PSDMR_PRETOACT_2W |\ | |
490 | PSDMR_ACTTORW_2W |\ | |
491 | PSDMR_LDOTOPRE_1C |\ | |
492 | PSDMR_WRC_1C |\ | |
493 | PSDMR_CL_2) | |
494 | ||
495 | /* SDRAM initialization values for 9-column chips | |
496 | */ | |
497 | #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ | |
498 | ORxS_BPD_4 |\ | |
499 | ORxS_ROWST_PBI0_A7 |\ | |
500 | ORxS_NUMR_13) | |
501 | ||
502 | #define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ | |
503 | PSDMR_BSMA_A13_A15 |\ | |
504 | PSDMR_SDA10_PBI0_A9 |\ | |
505 | PSDMR_RFRC_7_CLK |\ | |
506 | PSDMR_PRETOACT_2W |\ | |
507 | PSDMR_ACTTORW_2W |\ | |
508 | PSDMR_LDOTOPRE_1C |\ | |
509 | PSDMR_WRC_1C |\ | |
510 | PSDMR_CL_2) | |
511 | ||
512 | /* | |
513 | * Init Memory Controller: | |
514 | * | |
515 | * Bank Bus Machine PortSz Device | |
516 | * ---- --- ------- ------ ------ | |
517 | * 0 60x GPCM 8 bit Boot ROM | |
518 | * 1 60x GPCM 64 bit FLASH | |
519 | * 2 60x SDRAM 64 bit SDRAM | |
520 | * | |
521 | */ | |
522 | ||
523 | #define CFG_MRS_OFFS 0x00000000 | |
524 | ||
525 | #ifdef CONFIG_BOOT_ROM | |
526 | /* Bank 0 - Boot ROM | |
527 | */ | |
528 | #define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ | |
529 | BRx_PS_8 |\ | |
530 | BRx_MS_GPCM_P |\ | |
531 | BRx_V) | |
532 | ||
533 | #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ | |
534 | ORxG_CSNT |\ | |
535 | ORxG_ACS_DIV1 |\ | |
536 | ORxG_SCY_5_CLK |\ | |
537 | ORxU_EHTR_8IDLE) | |
538 | ||
539 | /* Bank 1 - FLASH | |
540 | */ | |
541 | #define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ | |
542 | BRx_PS_64 |\ | |
543 | BRx_MS_GPCM_P |\ | |
544 | BRx_V) | |
545 | ||
546 | #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ | |
547 | ORxG_CSNT |\ | |
548 | ORxG_ACS_DIV1 |\ | |
549 | ORxG_SCY_5_CLK |\ | |
550 | ORxU_EHTR_8IDLE) | |
551 | ||
552 | #else /* CONFIG_BOOT_ROM */ | |
553 | /* Bank 0 - FLASH | |
554 | */ | |
555 | #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ | |
556 | BRx_PS_64 |\ | |
557 | BRx_MS_GPCM_P |\ | |
558 | BRx_V) | |
559 | ||
560 | #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ | |
561 | ORxG_CSNT |\ | |
562 | ORxG_ACS_DIV1 |\ | |
563 | ORxG_SCY_5_CLK |\ | |
564 | ORxU_EHTR_8IDLE) | |
565 | ||
566 | /* Bank 1 - Boot ROM | |
567 | */ | |
568 | #define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ | |
569 | BRx_PS_8 |\ | |
570 | BRx_MS_GPCM_P |\ | |
571 | BRx_V) | |
572 | ||
573 | #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ | |
574 | ORxG_CSNT |\ | |
575 | ORxG_ACS_DIV1 |\ | |
576 | ORxG_SCY_5_CLK |\ | |
577 | ORxU_EHTR_8IDLE) | |
578 | ||
579 | #endif /* CONFIG_BOOT_ROM */ | |
580 | ||
581 | ||
582 | /* Bank 2 - 60x bus SDRAM | |
583 | */ | |
584 | #ifndef CFG_RAMBOOT | |
585 | #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ | |
586 | BRx_PS_64 |\ | |
587 | BRx_MS_SDRAM_P |\ | |
588 | BRx_V) | |
589 | ||
590 | #define CFG_OR2_PRELIM CFG_OR2_9COL | |
591 | ||
592 | #define CFG_PSDMR CFG_PSDMR_9COL | |
593 | #endif /* CFG_RAMBOOT */ | |
594 | ||
595 | /* Bank 3 - Dual Ported SRAM | |
596 | */ | |
597 | #define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\ | |
598 | BRx_PS_16 |\ | |
599 | BRx_MS_GPCM_P |\ | |
600 | BRx_V) | |
601 | ||
602 | #define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\ | |
603 | ORxG_CSNT |\ | |
604 | ORxG_ACS_DIV1 |\ | |
605 | ORxG_SCY_7_CLK |\ | |
606 | ORxG_SETA) | |
607 | ||
608 | /* Bank 4 - DiskOnChip | |
609 | */ | |
610 | #define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ | |
611 | BRx_PS_8 |\ | |
612 | BRx_MS_GPCM_P |\ | |
613 | BRx_V) | |
614 | ||
615 | #define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ | |
616 | ORxG_CSNT |\ | |
617 | ORxG_ACS_DIV2 |\ | |
618 | ORxG_SCY_9_CLK |\ | |
619 | ORxU_EHTR_8IDLE) | |
620 | ||
621 | /* Bank 5 - FDC37C78 controller | |
622 | */ | |
623 | #define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\ | |
624 | BRx_PS_8 |\ | |
625 | BRx_MS_GPCM_P |\ | |
626 | BRx_V) | |
627 | ||
628 | #define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\ | |
629 | ORxG_ACS_DIV2 |\ | |
630 | ORxG_SCY_10_CLK |\ | |
631 | ORxU_EHTR_8IDLE) | |
632 | ||
633 | /* Bank 6 - Board control registers | |
634 | */ | |
635 | #define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\ | |
636 | BRx_PS_8 |\ | |
637 | BRx_MS_GPCM_P |\ | |
638 | BRx_V) | |
639 | ||
640 | #define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\ | |
641 | ORxG_CSNT |\ | |
642 | ORxG_SCY_7_CLK) | |
643 | ||
644 | /* Bank 7 - VME Extended Access Range | |
645 | */ | |
646 | #define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\ | |
647 | BRx_PS_32 |\ | |
648 | BRx_MS_GPCM_P |\ | |
649 | BRx_V) | |
650 | ||
651 | #define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\ | |
652 | ORxG_CSNT |\ | |
653 | ORxG_ACS_DIV1 |\ | |
654 | ORxG_SCY_7_CLK |\ | |
655 | ORxG_SETA) | |
656 | ||
657 | /* Bank 8 - VME Standard Access Range | |
658 | */ | |
659 | #define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\ | |
660 | BRx_PS_16 |\ | |
661 | BRx_MS_GPCM_P |\ | |
662 | BRx_V) | |
663 | ||
664 | #define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\ | |
665 | ORxG_CSNT |\ | |
666 | ORxG_ACS_DIV1 |\ | |
667 | ORxG_SCY_7_CLK |\ | |
668 | ORxG_SETA) | |
669 | ||
670 | /* Bank 9 - VME Short I/O Access Range | |
671 | */ | |
672 | #define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\ | |
673 | BRx_PS_16 |\ | |
674 | BRx_MS_GPCM_P |\ | |
675 | BRx_V) | |
676 | ||
677 | #define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\ | |
678 | ORxG_CSNT |\ | |
679 | ORxG_ACS_DIV1 |\ | |
680 | ORxG_SCY_7_CLK |\ | |
681 | ORxG_SETA) | |
682 | ||
683 | #endif /* __CONFIG_H */ |