[people/ms/u-boot.git] / include / configs / DK1S10_mtx_ldk_20.h

/*
 * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
 * Stephan Linz <linz@li-pro.net>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_DK1S10_MTX_LDK_20_H
#define __CONFIG_DK1S10_MTX_LDK_20_H

/*
 * NIOS CPU configuration. (PART OF configs/DK1S10.h)
 *
 * Here we must define CPU dependencies. Any unsupported option have to
 * be defined with zero, example CPU without data cache / OCI:
 *
 *	#define	CONFIG_SYS_NIOS_CPU_ICACHE	4096
 *	#define	CONFIG_SYS_NIOS_CPU_DCACHE	0
 *	#define	CONFIG_SYS_NIOS_CPU_OCI_BASE	0
 *	#define	CONFIG_SYS_NIOS_CPU_OCI_SIZE	0
 */

/* CPU core */
#define	CONFIG_SYS_NIOS_CPU_CLK	75000000	/* NIOS CPU clock	*/
#define	CONFIG_SYS_NIOS_CPU_ICACHE	(0)		/* instruction cache	*/
#define	CONFIG_SYS_NIOS_CPU_DCACHE	(0)		/* data cache		*/
#define	CONFIG_SYS_NIOS_CPU_REG_NUMS	512		/* number of register	*/
#define	CONFIG_SYS_NIOS_CPU_MUL	0		/* 16x16 MUL:	no(0)	*/
						/*		yes(1)	*/
#define	CONFIG_SYS_NIOS_CPU_MSTEP	1		/* 16x16 MSTEP:	no(0)	*/
						/*		yes(1)	*/
#define	CONFIG_SYS_NIOS_CPU_STACK	0x02000000	/* stack top	addr	*/
#define	CONFIG_SYS_NIOS_CPU_VEC_BASE	0x01000000	/* IRQ vectors	addr	*/
#define	CONFIG_SYS_NIOS_CPU_VEC_SIZE	256		/*		size	*/
#define	CONFIG_SYS_NIOS_CPU_VEC_NUMS	64		/*		numbers	*/
#define	CONFIG_SYS_NIOS_CPU_RST_VECT	0x00000000	/* RESET vector	addr	*/
#define	CONFIG_SYS_NIOS_CPU_DBG_CORE	0		/* CPU debug:	no(0)	*/
						/*		yes(1)	*/

/* The offset address in flash to check for the Nios signature "Ni".
 * (see GM_FlashExec in germs_monitor.s) */
#define	CONFIG_SYS_NIOS_CPU_EXES_OFFS	0x0C

/* on-chip extensions */
#undef	CONFIG_SYS_NIOS_CPU_RAM_BASE			/* on chip RAM	addr	*/
#undef	CONFIG_SYS_NIOS_CPU_RAM_SIZE			/* 64 KB	size	*/

#define	CONFIG_SYS_NIOS_CPU_ROM_BASE	0x00000000	/* on chip ROM	addr	*/
#define	CONFIG_SYS_NIOS_CPU_ROM_SIZE	(2 * 1024)	/*  2 KB	size	*/

#undef	CONFIG_SYS_NIOS_CPU_OCI_BASE			/* OCI core	addr	*/
#undef	CONFIG_SYS_NIOS_CPU_OCI_SIZE			/*		size	*/

/* timer */
#define	CONFIG_SYS_NIOS_CPU_TIMER_NUMS	1		/* number of timer	*/

#define	CONFIG_SYS_NIOS_CPU_TIMER0	0x00000840	/* TIMER0	addr	*/
#define	CONFIG_SYS_NIOS_CPU_TIMER0_IRQ	16		/*		IRQ	*/
#define	CONFIG_SYS_NIOS_CPU_TIMER0_PER	1000		/*  periode	usec	*/
#define	CONFIG_SYS_NIOS_CPU_TIMER0_AR	0		/*  always run:	no(0)	*/
						/*		yes(1)	*/
#define	CONFIG_SYS_NIOS_CPU_TIMER0_FP	0		/*  fixed per:	no(0)	*/
						/*		yes(1)	*/
#define	CONFIG_SYS_NIOS_CPU_TIMER0_SS	1		/*  snaphot:	no(0)	*/
						/*		yes(1)	*/

/* serial i/o */
#define	CONFIG_SYS_NIOS_CPU_UART_NUMS	2		/* number of uarts	*/

#define	CONFIG_SYS_NIOS_CPU_UART0	0x00000800	/* UART0	addr	*/
#define	CONFIG_SYS_NIOS_CPU_UART0_IRQ	17		/*		IRQ	*/
#define	CONFIG_SYS_NIOS_CPU_UART0_BR	115200		/*  baudrate	var(0)	*/
#define	CONFIG_SYS_NIOS_CPU_UART0_DB	8		/*  data bit		*/
#define	CONFIG_SYS_NIOS_CPU_UART0_SB	2		/*  stop bit		*/
#define	CONFIG_SYS_NIOS_CPU_UART0_PA	0		/*  parity	none(0)	*/
						/*		odd(1)	*/
						/*		even(2)	*/
#define	CONFIG_SYS_NIOS_CPU_UART0_HS	0		/*  handshake:	no(0)	*/
						/*		crts(1)	*/
#define	CONFIG_SYS_NIOS_CPU_UART0_EOP	0		/*  eop reg:	no(0)	*/
						/*		yes(1)	*/

#define	CONFIG_SYS_NIOS_CPU_UART1	0x000008a0	/* UART1	addr	*/
#define	CONFIG_SYS_NIOS_CPU_UART1_IRQ	18		/*		IRQ	*/
#define	CONFIG_SYS_NIOS_CPU_UART1_BR	115200		/*  baudrate	var(0)	*/
#define	CONFIG_SYS_NIOS_CPU_UART1_DB	8		/*  data bit		*/
#define	CONFIG_SYS_NIOS_CPU_UART1_SB	1		/*  stop bit		*/
#define	CONFIG_SYS_NIOS_CPU_UART1_PA	0		/*  parity	none(0)	*/
						/*		odd(1)	*/
						/*		even(2)	*/
#define	CONFIG_SYS_NIOS_CPU_UART1_HS	0		/*  handshake:	no(0)	*/
						/*		crts(1)	*/
#define	CONFIG_SYS_NIOS_CPU_UART1_EOP	0		/*  eop reg:	no(0)	*/
						/*		yes(1)	*/

/* parallel i/o */
#define	CONFIG_SYS_NIOS_CPU_PIO_NUMS	2		/* number of parports	*/

#define	CONFIG_SYS_NIOS_CPU_PIO0	0x00000860	/* PIO0		addr	*/
#undef	CONFIG_SYS_NIOS_CPU_PIO0_IRQ			/*		w/o IRQ	*/
#define	CONFIG_SYS_NIOS_CPU_PIO0_BITS	1		/*  number  of  bits	*/
#define	CONFIG_SYS_NIOS_CPU_PIO0_TYPE	1		/*  io type:	tris(0)	*/
						/*		out(1)	*/
						/*		in(2)	*/
#define	CONFIG_SYS_NIOS_CPU_PIO0_CAP	0		/*  capture:	no(0)	*/
						/*		yes(1)	*/
#define	CONFIG_SYS_NIOS_CPU_PIO0_EDGE	0		/*  edge type:	none(0)	*/
						/*		fall(1)	*/
						/*		rise(2)	*/
						/*		any(3)	*/
#define	CONFIG_SYS_NIOS_CPU_PIO0_ITYPE	0		/*  IRQ type:	none(0)	*/
						/*		level(1)*/
						/*		edge(2)	*/

#define	CONFIG_SYS_NIOS_CPU_PIO1	0x00000870	/* PIO1		addr	*/
#undef	CONFIG_SYS_NIOS_CPU_PIO1_IRQ			/*		w/o IRQ	*/
#define	CONFIG_SYS_NIOS_CPU_PIO1_BITS	4		/*  number  of  bits	*/
#define	CONFIG_SYS_NIOS_CPU_PIO1_TYPE	2		/*  io type:	tris(0)	*/
						/*		out(1)	*/
						/*		in(2)	*/
#define	CONFIG_SYS_NIOS_CPU_PIO1_CAP	0		/*  capture:	no(0)	*/
						/*		yes(1)	*/
#define	CONFIG_SYS_NIOS_CPU_PIO1_EDGE	0		/*  edge type:	none(0)	*/
						/*		fall(1)	*/
						/*		rise(2)	*/
						/*		any(3)	*/
#define	CONFIG_SYS_NIOS_CPU_PIO1_ITYPE	0		/*  IRQ type:	none(0)	*/
						/*		level(1)*/
						/*		edge(2)	*/

/* IDE i/f */
#define	CONFIG_SYS_NIOS_CPU_IDE_NUMS	1		/* number of IDE contr.	*/
#define	CONFIG_SYS_NIOS_CPU_IDE0	0x00000900	/* IDE0		addr	*/
#define	CONFIG_SYS_NIOS_CPU_IDE0_IRQ	25		/*		IRQ	*/

/* memory accessibility */
#undef	CONFIG_SYS_NIOS_CPU_SRAM_BASE			/* board SRAM	addr	*/
#undef	CONFIG_SYS_NIOS_CPU_SRAM_SIZE			/*  1 MB	size	*/

#define	CONFIG_SYS_NIOS_CPU_SDRAM_BASE	0x01000000	/* board SDRAM	addr	*/
#define	CONFIG_SYS_NIOS_CPU_SDRAM_SIZE	(16*1024*1024)	/* 16 MB	size	*/

#define	CONFIG_SYS_NIOS_CPU_FLASH_BASE	0x00800000	/* board Flash	addr	*/
#define	CONFIG_SYS_NIOS_CPU_FLASH_SIZE	(8*1024*1024)	/*  8 MB	size	*/

/* LAN */
#define	CONFIG_SYS_NIOS_CPU_LAN_NUMS	1		/* number of LAN i/f	*/

#define	CONFIG_SYS_NIOS_CPU_LAN0_BASE	0x00010000	/* LAN0		addr	*/
#define	CONFIG_SYS_NIOS_CPU_LAN0_OFFS	0x0300		/*		offset	*/
#define	CONFIG_SYS_NIOS_CPU_LAN0_IRQ	20		/*		IRQ	*/
#define	CONFIG_SYS_NIOS_CPU_LAN0_BUSW	32		/*	        buswidth*/
#define	CONFIG_SYS_NIOS_CPU_LAN0_TYPE	0		/*	smc91111(0)	*/
						/*	cs8900(1)	*/
						/* ex:	openmac(2)	*/
						/* ex:	alteramac(3)	*/

/* symbolic redefinition (undef, if not present) */
#define	CONFIG_SYS_NIOS_CPU_TICK_TIMER		0	/* TIMER0: tick (needed)*/
#undef	CONFIG_SYS_NIOS_CPU_USER_TIMER			/* TIMERx: users choice	*/

#define	CONFIG_SYS_NIOS_CPU_CFPOWER_PIO	0	/* PIO0: CF power/sw.	*/
#define	CONFIG_SYS_NIOS_CPU_BUTTON_PIO		1	/* PIO1: buttons	*/
#undef	CONFIG_SYS_NIOS_CPU_LCD_PIO			/* PIOx: ASCII LCD	*/
#undef	CONFIG_SYS_NIOS_CPU_LED_PIO			/* PIOx: LED bar	*/
#undef	CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO		/* PIOx: 7-seg. display	*/
#undef	CONFIG_SYS_NIOS_CPU_RECONF_PIO			/* PIOx: reconf pin	*/
#undef	CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO		/* PIOx: CF present IRQ	*/
#undef	CONFIG_SYS_NIOS_CPU_CFATASEL_PIO		/* PIOx: CF ATA select	*/

#endif	/* __CONFIG_DK1S10_MTX_LDK_20_H */
Commit	Line	Data
ec4c544b WD	1	/*
	2	* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
	3	* Stephan Linz <linz@li-pro.net>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_DK1S10_MTX_LDK_20_H
	25	#define __CONFIG_DK1S10_MTX_LDK_20_H
	26
	27	/*
	28	* NIOS CPU configuration. (PART OF configs/DK1S10.h)
	29	*
	30	* Here we must define CPU dependencies. Any unsupported option have to
	31	* be defined with zero, example CPU without data cache / OCI:
	32	*
6d0f6bcf JCPV	33	* #define CONFIG_SYS_NIOS_CPU_ICACHE 4096
	34	* #define CONFIG_SYS_NIOS_CPU_DCACHE 0
	35	* #define CONFIG_SYS_NIOS_CPU_OCI_BASE 0
	36	* #define CONFIG_SYS_NIOS_CPU_OCI_SIZE 0
ec4c544b WD	37	*/
	38
	39	/* CPU core */
6d0f6bcf JCPV	40	#define CONFIG_SYS_NIOS_CPU_CLK 75000000 /* NIOS CPU clock */
	41	#define CONFIG_SYS_NIOS_CPU_ICACHE (0) /* instruction cache */
	42	#define CONFIG_SYS_NIOS_CPU_DCACHE (0) /* data cache */
	43	#define CONFIG_SYS_NIOS_CPU_REG_NUMS 512 /* number of register */
	44	#define CONFIG_SYS_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */
ec4c544b	45	/* yes(1) */
6d0f6bcf	46	#define CONFIG_SYS_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */
ec4c544b	47	/* yes(1) */
6d0f6bcf JCPV	48	#define CONFIG_SYS_NIOS_CPU_STACK 0x02000000 /* stack top addr */
	49	#define CONFIG_SYS_NIOS_CPU_VEC_BASE 0x01000000 /* IRQ vectors addr */
	50	#define CONFIG_SYS_NIOS_CPU_VEC_SIZE 256 /* size */
	51	#define CONFIG_SYS_NIOS_CPU_VEC_NUMS 64 /* numbers */
	52	#define CONFIG_SYS_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */
	53	#define CONFIG_SYS_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */
ec4c544b WD	54	/* yes(1) */
	55
	56	/* The offset address in flash to check for the Nios signature "Ni".
	57	* (see GM_FlashExec in germs_monitor.s) */
6d0f6bcf	58	#define CONFIG_SYS_NIOS_CPU_EXES_OFFS 0x0C
ec4c544b WD	59
ec4c544b WD	60	/* on-chip extensions */
6d0f6bcf JCPV	61	#undef CONFIG_SYS_NIOS_CPU_RAM_BASE /* on chip RAM addr */
6d0f6bcf JCPV	62	#undef CONFIG_SYS_NIOS_CPU_RAM_SIZE /* 64 KB size */
ec4c544b	63
6d0f6bcf JCPV	64	#define CONFIG_SYS_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */
6d0f6bcf JCPV	65	#define CONFIG_SYS_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */
ec4c544b	66
6d0f6bcf JCPV	67	#undef CONFIG_SYS_NIOS_CPU_OCI_BASE /* OCI core addr */
6d0f6bcf JCPV	68	#undef CONFIG_SYS_NIOS_CPU_OCI_SIZE /* size */
ec4c544b WD	69
ec4c544b WD	70	/* timer */
6d0f6bcf	71	#define CONFIG_SYS_NIOS_CPU_TIMER_NUMS 1 /* number of timer */
ec4c544b	72
6d0f6bcf JCPV	73	#define CONFIG_SYS_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */
	74	#define CONFIG_SYS_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */
	75	#define CONFIG_SYS_NIOS_CPU_TIMER0_PER 1000 /* periode usec */
	76	#define CONFIG_SYS_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */
ec4c544b	77	/* yes(1) */
6d0f6bcf	78	#define CONFIG_SYS_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */
ec4c544b	79	/* yes(1) */
6d0f6bcf	80	#define CONFIG_SYS_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */
ec4c544b WD	81	/* yes(1) */
	82
	83	/* serial i/o */
6d0f6bcf JCPV	84	#define CONFIG_SYS_NIOS_CPU_UART_NUMS 2 /* number of uarts */
	85
	86	#define CONFIG_SYS_NIOS_CPU_UART0 0x00000800 /* UART0 addr */
	87	#define CONFIG_SYS_NIOS_CPU_UART0_IRQ 17 /* IRQ */
	88	#define CONFIG_SYS_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */
	89	#define CONFIG_SYS_NIOS_CPU_UART0_DB 8 /* data bit */
	90	#define CONFIG_SYS_NIOS_CPU_UART0_SB 2 /* stop bit */
	91	#define CONFIG_SYS_NIOS_CPU_UART0_PA 0 /* parity none(0) */
ec4c544b WD	92	/* odd(1) */
ec4c544b WD	93	/* even(2) */
6d0f6bcf	94	#define CONFIG_SYS_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */
ec4c544b	95	/* crts(1) */
6d0f6bcf	96	#define CONFIG_SYS_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */
ec4c544b WD	97	/* yes(1) */
ec4c544b WD	98
6d0f6bcf JCPV	99	#define CONFIG_SYS_NIOS_CPU_UART1 0x000008a0 /* UART1 addr */
	100	#define CONFIG_SYS_NIOS_CPU_UART1_IRQ 18 /* IRQ */
	101	#define CONFIG_SYS_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */
	102	#define CONFIG_SYS_NIOS_CPU_UART1_DB 8 /* data bit */
	103	#define CONFIG_SYS_NIOS_CPU_UART1_SB 1 /* stop bit */
	104	#define CONFIG_SYS_NIOS_CPU_UART1_PA 0 /* parity none(0) */
ec4c544b WD	105	/* odd(1) */
ec4c544b WD	106	/* even(2) */
6d0f6bcf	107	#define CONFIG_SYS_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */
ec4c544b	108	/* crts(1) */
6d0f6bcf	109	#define CONFIG_SYS_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */
ec4c544b WD	110	/* yes(1) */
	111
	112	/* parallel i/o */
6d0f6bcf	113	#define CONFIG_SYS_NIOS_CPU_PIO_NUMS 2 /* number of parports */
ec4c544b	114
6d0f6bcf JCPV	115	#define CONFIG_SYS_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */
	116	#undef CONFIG_SYS_NIOS_CPU_PIO0_IRQ /* w/o IRQ */
	117	#define CONFIG_SYS_NIOS_CPU_PIO0_BITS 1 /* number of bits */
	118	#define CONFIG_SYS_NIOS_CPU_PIO0_TYPE 1 /* io type: tris(0) */
ec4c544b WD	119	/* out(1) */
ec4c544b WD	120	/* in(2) */
6d0f6bcf	121	#define CONFIG_SYS_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */
ec4c544b	122	/* yes(1) */
6d0f6bcf	123	#define CONFIG_SYS_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */
ec4c544b WD	124	/* fall(1) */
	125	/* rise(2) */
	126	/* any(3) */
6d0f6bcf	127	#define CONFIG_SYS_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */
ec4c544b WD	128	/* level(1)*/
	129	/* edge(2) */
	130
6d0f6bcf JCPV	131	#define CONFIG_SYS_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */
	132	#undef CONFIG_SYS_NIOS_CPU_PIO1_IRQ /* w/o IRQ */
	133	#define CONFIG_SYS_NIOS_CPU_PIO1_BITS 4 /* number of bits */
	134	#define CONFIG_SYS_NIOS_CPU_PIO1_TYPE 2 /* io type: tris(0) */
ec4c544b WD	135	/* out(1) */
ec4c544b WD	136	/* in(2) */
6d0f6bcf	137	#define CONFIG_SYS_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */
ec4c544b	138	/* yes(1) */
6d0f6bcf	139	#define CONFIG_SYS_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */
ec4c544b WD	140	/* fall(1) */
	141	/* rise(2) */
	142	/* any(3) */
6d0f6bcf	143	#define CONFIG_SYS_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */
ec4c544b WD	144	/* level(1)*/
	145	/* edge(2) */
	146
	147	/* IDE i/f */
6d0f6bcf JCPV	148	#define CONFIG_SYS_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */
	149	#define CONFIG_SYS_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */
	150	#define CONFIG_SYS_NIOS_CPU_IDE0_IRQ 25 /* IRQ */
ec4c544b WD	151
ec4c544b WD	152	/* memory accessibility */
6d0f6bcf JCPV	153	#undef CONFIG_SYS_NIOS_CPU_SRAM_BASE /* board SRAM addr */
6d0f6bcf JCPV	154	#undef CONFIG_SYS_NIOS_CPU_SRAM_SIZE /* 1 MB size */
ec4c544b	155
6d0f6bcf JCPV	156	#define CONFIG_SYS_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */
6d0f6bcf JCPV	157	#define CONFIG_SYS_NIOS_CPU_SDRAM_SIZE (1610241024) /* 16 MB size */
ec4c544b	158
6d0f6bcf JCPV	159	#define CONFIG_SYS_NIOS_CPU_FLASH_BASE 0x00800000 /* board Flash addr */
6d0f6bcf JCPV	160	#define CONFIG_SYS_NIOS_CPU_FLASH_SIZE (810241024) /* 8 MB size */
ec4c544b WD	161
ec4c544b WD	162	/* LAN */
6d0f6bcf	163	#define CONFIG_SYS_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */
ec4c544b	164
6d0f6bcf JCPV	165	#define CONFIG_SYS_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */
	166	#define CONFIG_SYS_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */
	167	#define CONFIG_SYS_NIOS_CPU_LAN0_IRQ 20 /* IRQ */
	168	#define CONFIG_SYS_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/
	169	#define CONFIG_SYS_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */
ec4c544b WD	170	/* cs8900(1) */
	171	/* ex: openmac(2) */
	172	/* ex: alteramac(3) */
	173
	174	/* symbolic redefinition (undef, if not present) */
6d0f6bcf JCPV	175	#define CONFIG_SYS_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/
	176	#undef CONFIG_SYS_NIOS_CPU_USER_TIMER /* TIMERx: users choice */
	177
	178	#define CONFIG_SYS_NIOS_CPU_CFPOWER_PIO 0 /* PIO0: CF power/sw. */
	179	#define CONFIG_SYS_NIOS_CPU_BUTTON_PIO 1 /* PIO1: buttons */
	180	#undef CONFIG_SYS_NIOS_CPU_LCD_PIO /* PIOx: ASCII LCD */
	181	#undef CONFIG_SYS_NIOS_CPU_LED_PIO /* PIOx: LED bar */
	182	#undef CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO /* PIOx: 7-seg. display */
	183	#undef CONFIG_SYS_NIOS_CPU_RECONF_PIO /* PIOx: reconf pin */
	184	#undef CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO /* PIOx: CF present IRQ */
	185	#undef CONFIG_SYS_NIOS_CPU_CFATASEL_PIO /* PIOx: CF ATA select */
ec4c544b WD	186
ec4c544b WD	187	#endif /* __CONFIG_DK1S10_MTX_LDK_20_H */