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c609719b WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
82f4c6ac | 35 | #define CONFIG_IDENT_STRING " $Name: $" |
c609719b WD |
36 | |
37 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
c837dcb1 WD |
38 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
39 | #define CONFIG_DU405 1 /* ...on a DU405 board */ | |
c609719b | 40 | |
c837dcb1 | 41 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
82f4c6ac | 42 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
c609719b | 43 | |
c837dcb1 | 44 | #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ |
c609719b WD |
45 | |
46 | #define CONFIG_BAUDRATE 9600 | |
47 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ | |
48 | ||
49 | #undef CONFIG_BOOTARGS | |
50 | #define CONFIG_BOOTCOMMAND "bootm fff00000" | |
51 | ||
a20b27a3 SR |
52 | #define CONFIG_PREBOOT /* enable preboot variable */ |
53 | ||
c609719b | 54 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 55 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
c609719b | 56 | |
96e21f86 | 57 | #define CONFIG_PPC4xx_EMAC |
c609719b | 58 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 59 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 60 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
c609719b | 61 | |
3c3227f3 | 62 | |
11799434 JL |
63 | /* |
64 | * BOOTP options | |
65 | */ | |
66 | #define CONFIG_BOOTP_BOOTFILESIZE | |
67 | #define CONFIG_BOOTP_BOOTPATH | |
68 | #define CONFIG_BOOTP_GATEWAY | |
69 | #define CONFIG_BOOTP_HOSTNAME | |
70 | ||
71 | ||
3c3227f3 JL |
72 | /* |
73 | * Command line configuration. | |
74 | */ | |
75 | #include <config_cmd_default.h> | |
76 | ||
77 | #define CONFIG_CMD_PCI | |
78 | #define CONFIG_CMD_IRQ | |
79 | #define CONFIG_CMD_IDE | |
80 | #define CONFIG_CMD_ELF | |
81 | #define CONFIG_CMD_MII | |
82 | #define CONFIG_CMD_DATE | |
83 | #define CONFIG_CMD_EEPROM | |
84 | ||
c609719b WD |
85 | |
86 | #define CONFIG_MAC_PARTITION | |
87 | #define CONFIG_DOS_PARTITION | |
88 | ||
c609719b WD |
89 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
90 | ||
c837dcb1 | 91 | #define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/ |
6d0f6bcf | 92 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000080 /* RTC Base Address */ |
c609719b | 93 | |
c837dcb1 | 94 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
c609719b WD |
95 | |
96 | /* | |
97 | * Miscellaneous configurable options | |
98 | */ | |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
100 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
3c3227f3 | 101 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 102 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c609719b | 103 | #else |
6d0f6bcf | 104 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c609719b | 105 | #endif |
6d0f6bcf JCPV |
106 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
107 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
108 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c609719b | 109 | |
6d0f6bcf | 110 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
c609719b | 111 | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
113 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
c609719b | 114 | |
6d0f6bcf | 115 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */ |
c609719b WD |
116 | |
117 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 118 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8bde7f77 WD |
119 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
120 | 57600, 115200, 230400, 460800, 921600 } | |
c609719b | 121 | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
123 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
c609719b | 124 | |
6d0f6bcf | 125 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
c609719b WD |
126 | |
127 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ | |
128 | ||
6d0f6bcf | 129 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
a20b27a3 | 130 | |
c609719b WD |
131 | /*----------------------------------------------------------------------- |
132 | * PCI stuff | |
133 | *----------------------------------------------------------------------- | |
134 | */ | |
c837dcb1 WD |
135 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
136 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
137 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
c609719b | 138 | |
c837dcb1 WD |
139 | #define CONFIG_PCI /* include pci support */ |
140 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ | |
141 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
142 | /* resource configuration */ | |
c609719b | 143 | |
c837dcb1 | 144 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
ad10dd9a | 145 | |
c837dcb1 | 146 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ |
ad10dd9a | 147 | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
149 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ | |
150 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
151 | #define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ | |
152 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
153 | #define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */ | |
154 | #define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ | |
155 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
c609719b WD |
156 | |
157 | /*----------------------------------------------------------------------- | |
158 | * IDE/ATA stuff | |
159 | *----------------------------------------------------------------------- | |
160 | */ | |
c837dcb1 WD |
161 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
162 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
163 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
c609719b | 164 | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
166 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ | |
c609719b | 167 | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
169 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
c609719b | 170 | |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
172 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
173 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
c609719b WD |
174 | |
175 | /*----------------------------------------------------------------------- | |
176 | * Start addresses for the final memory configuration | |
177 | * (Set up by the startup code) | |
6d0f6bcf | 178 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 179 | */ |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
181 | #define CONFIG_SYS_FLASH_BASE 0xFFFD0000 | |
182 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
183 | #define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ | |
184 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
c609719b WD |
185 | |
186 | /* | |
187 | * For booting Linux, the board info and command line data | |
188 | * have to be in the first 8 MB of memory, since this is | |
189 | * the maximum mapped by the Linux kernel during initialization. | |
190 | */ | |
6d0f6bcf | 191 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
c609719b WD |
192 | /*----------------------------------------------------------------------- |
193 | * FLASH organization | |
194 | */ | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
196 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
c609719b | 197 | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
199 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b | 200 | |
6d0f6bcf JCPV |
201 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
202 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
203 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
c609719b WD |
204 | /* |
205 | * The following defines are added for buggy IOP480 byte interface. | |
206 | * All other boards should use the standard values (CPCI405 etc.) | |
207 | */ | |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
209 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
210 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
c609719b | 211 | |
6d0f6bcf | 212 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
c609719b WD |
213 | |
214 | /*----------------------------------------------------------------------- | |
215 | * I2C EEPROM (CAT24WC08) for environment | |
216 | */ | |
217 | #define CONFIG_HARD_I2C /* I2c with hardware support */ | |
6d0f6bcf JCPV |
218 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
219 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
c609719b | 220 | |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
222 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
c837dcb1 | 223 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
225 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
c609719b | 226 | /* 16 byte page write mode using*/ |
c837dcb1 | 227 | /* last 4 bits of the address */ |
6d0f6bcf | 228 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
c609719b | 229 | |
bb1f8b4f | 230 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
231 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
232 | #define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ | |
8bde7f77 | 233 | /* total size of a CAT24WC08 is 1024 bytes */ |
c609719b | 234 | |
c609719b WD |
235 | /* |
236 | * Init Memory Controller: | |
237 | * | |
238 | * BR0/1 and OR0/1 (FLASH) | |
239 | */ | |
240 | ||
241 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ | |
242 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ | |
243 | ||
244 | /*----------------------------------------------------------------------- | |
245 | * External Bus Controller (EBC) Setup | |
246 | */ | |
247 | ||
c837dcb1 WD |
248 | #define FLASH0_BA 0xFFC00000 /* FLASH 0 Base Address */ |
249 | #define FLASH1_BA 0xFF800000 /* FLASH 1 Base Address */ | |
250 | #define CAN_BA 0xF0000000 /* CAN Base Address */ | |
251 | #define DUART_BA 0xF0300000 /* DUART Base Address */ | |
252 | #define CF_BA 0xF0100000 /* CompactFlash Base Address */ | |
253 | #define SRAM_BA 0xF0200000 /* SRAM Base Address */ | |
254 | #define DURAG_IO_BA 0xF0400000 /* DURAG Bus IO Base Address */ | |
255 | #define DURAG_MEM_BA 0xF0500000 /* DURAG Bus Mem Base Address */ | |
c609719b | 256 | |
c837dcb1 | 257 | #define FPGA_MODE_REG (DUART_BA+0x80) /* FPGA Mode Register */ |
c609719b | 258 | |
c837dcb1 | 259 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
261 | #define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 262 | |
c837dcb1 | 263 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
265 | #define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 266 | |
c837dcb1 | 267 | /* Memory Bank 2 (CAN0) initialization */ |
6d0f6bcf JCPV |
268 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
269 | #define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
c609719b | 270 | |
c837dcb1 | 271 | /* Memory Bank 3 (DUART) initialization */ |
6d0f6bcf JCPV |
272 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
273 | #define CONFIG_SYS_EBC_PB3CR DUART_BA | 0x18000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ | |
c609719b | 274 | |
c837dcb1 | 275 | /* Memory Bank 4 (CompactFlash IDE) initialization */ |
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_EBC_PB4AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
277 | #define CONFIG_SYS_EBC_PB4CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
c609719b | 278 | |
c837dcb1 | 279 | /* Memory Bank 5 (SRAM) initialization */ |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_EBC_PB5AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
281 | #define CONFIG_SYS_EBC_PB5CR SRAM_BA | 0x1A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */ | |
c609719b | 282 | |
c837dcb1 | 283 | /* Memory Bank 6 (DURAG Bus IO Space) initialization */ |
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
285 | #define CONFIG_SYS_EBC_PB6CR DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/ | |
c609719b | 286 | |
c837dcb1 | 287 | /* Memory Bank 7 (DURAG Bus Mem Space) initialization */ |
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_EBC_PB7AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
289 | #define CONFIG_SYS_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */ | |
c609719b WD |
290 | |
291 | ||
292 | /*----------------------------------------------------------------------- | |
293 | * Definitions for initial stack pointer and data area (in DPRAM) | |
294 | */ | |
295 | ||
296 | /* use on chip memory ( OCM ) for temperary stack until sdram is tested */ | |
6d0f6bcf | 297 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
c609719b WD |
298 | |
299 | /* On Chip Memory location */ | |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
301 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
302 | ||
303 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ | |
304 | #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ | |
305 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
306 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
307 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
c609719b WD |
308 | |
309 | ||
310 | /* | |
311 | * Internal Definitions | |
312 | * | |
313 | * Boot Flags | |
314 | */ | |
315 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
316 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
317 | ||
318 | #endif /* __CONFIG_H */ |