[people/ms/u-boot.git] / include / configs / EB+MCF-EV123.h

/*
 * Configuation settings for the BuS EB+MCF-EV123 boards.
 *
 * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _CONFIG_EB_MCF_EV123_H_
#define _CONFIG_EB_MCF_EV123_H_

#define  CONFIG_EB_MCF_EV123

#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP

/*
 * High Level Configuration Options (easy to change)
 */

#define	CONFIG_MCF52x2			/* define processor family */
#define CONFIG_M5282			/* define processor type */

#define CONFIG_MISC_INIT_R

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }

#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */

#define CONFIG_BOOTCOMMAND "printenv"

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_ADDR		0xF003C000	/* End of 256K */
#define CONFIG_ENV_SECT_SIZE	0x4000
#define CONFIG_ENV_IS_IN_FLASH	1
/*
#define CONFIG_ENV_IS_EMBEDDED	1
#define CONFIG_ENV_ADDR_REDUND		0xF0018000
#define CONFIG_ENV_SECT_SIZE_REDUND	0x4000
*/
#else
#define CONFIG_ENV_ADDR		0xFFE04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_LOADB
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET

#define CONFIG_MCFTMR

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_MULTI		1
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#ifdef CONFIG_MCFFEC
#	define CONFIG_ETHADDR	00:CF:52:82:EB:01
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* CONFIG_MCFFEC */

#define CONFIG_BOOTDELAY	5
#define CONFIG_SYS_PROMPT		"\nEV123 U-Boot> "
#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_LOAD_ADDR		0x20000

#define CONFIG_SYS_MEMTEST_START	0x100000
#define CONFIG_SYS_MEMTEST_END		0x400000
/*#define CONFIG_SYS_DRAM_TEST		1 */
#undef CONFIG_SYS_DRAM_TEST

/* Clock and PLL Configuration */
#define CONFIG_SYS_HZ			10000000
#define	CONFIG_SYS_CLK			58982400       /* 9,8304MHz * 6 */

/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */

#define CONFIG_SYS_MFD			0x01	/* PLL Multiplication Factor Devider */
#define CONFIG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
#define	CONFIG_SYS_MBAR		0x40000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR       0x20000000
#define CONFIG_SYS_INIT_RAM_END	0x10000		/* End of used area in internal SRAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE1		0x00000000
#define	CONFIG_SYS_SDRAM_SIZE1		16		/* SDRAM size in MB */

/*
#define CONFIG_SYS_SDRAM_BASE0		CONFIG_SYS_SDRAM_BASE1+CONFIG_SYS_SDRAM_SIZE1*1024*1024
#define	CONFIG_SYS_SDRAM_SIZE0		16	*/	/* SDRAM size in MB */

#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_SDRAM_BASE1
#define	CONFIG_SYS_SDRAM_SIZE		CONFIG_SYS_SDRAM_SIZE1

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#define	CONFIG_SYS_INT_FLASH_BASE	0xF0000000
#define CONFIG_SYS_INT_FLASH_ENABLE	0x21

/* If M5282 port is fully implemented the monitor base will be behind
 * the vector table. */
#if (TEXT_BASE !=  CONFIG_SYS_INT_FLASH_BASE)
#define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
#else
#define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define	CONFIG_SYS_MAX_FLASH_SECT	35
#define	CONFIG_SYS_MAX_FLASH_BANKS	2
#define	CONFIG_SYS_FLASH_ERASE_TOUT	10000000
#define	CONFIG_SYS_FLASH_PROTECTION

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */

#define CONFIG_SYS_CS0_BASE		0xFFE00000
#define CONFIG_SYS_CS0_CTRL		0x00001980
#define CONFIG_SYS_CS0_MASK		0x001F0001

#define CONFIG_SYS_CS3_BASE		0xE0000000
#define CONFIG_SYS_CS0_CTRL		0x00001980
#define CONFIG_SYS_CS3_MASK		0x000F0001

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
#define CONFIG_SYS_PADDR		0x0000000
#define CONFIG_SYS_PADAT		0x0000000

#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
#define CONFIG_SYS_PBDDR		0x0000000
#define CONFIG_SYS_PBDAT		0x0000000

#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
#define CONFIG_SYS_PCDDR		0x0000000
#define CONFIG_SYS_PCDAT		0x0000000

#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
#define CONFIG_SYS_PCDDR		0x0000000
#define CONFIG_SYS_PCDAT		0x0000000

#define CONFIG_SYS_PEHLPAR		0xC0
#define CONFIG_SYS_PUAPAR		0x0F		/* UA0..UA3 = Uart 0 +1 */
#define CONFIG_SYS_DDRUA		0x05
#define CONFIG_SYS_PJPAR		0xFF

/*-----------------------------------------------------------------------
 * CCM configuration
 */

#define	CONFIG_SYS_CCM_SIZ		0

/*---------------------------------------------------------------------*/
#endif	/* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/
Commit	Line	Data
9acb626f HS	1	/*
	2	* Configuation settings for the BuS EB+MCF-EV123 boards.
	3	*
	4	* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef _CONFIG_EB_MCF_EV123_H_
	26	#define _CONFIG_EB_MCF_EV123_H_
	27
	28	#define CONFIG_EB_MCF_EV123
	29
6d0f6bcf	30	#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP
b1d71358	31
9acb626f HS	32	/*
	33	* High Level Configuration Options (easy to change)
	34	*/
	35
	36	#define CONFIG_MCF52x2 /* define processor family */
	37	#define CONFIG_M5282 /* define processor type */
	38
	39	#define CONFIG_MISC_INIT_R
	40
870470db	41	#define CONFIG_MCFUART
6d0f6bcf	42	#define CONFIG_SYS_UART_PORT (0)
9acb626f	43	#define CONFIG_BAUDRATE 9600
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
9acb626f HS	45
	46	#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
	47
	48	#define CONFIG_BOOTCOMMAND "printenv"
	49
	50	/* Configuration for environment
	51	* Environment is embedded in u-boot in the second sector of the flash
	52	*/
	53	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	54	#define CONFIG_ENV_ADDR 0xF003C000 /* End of 256K */
0e8d1586 JCPV	55	#define CONFIG_ENV_SECT_SIZE 0x4000
5a1aceb0	56	#define CONFIG_ENV_IS_IN_FLASH 1
9acb626f	57	/*
0e8d1586 JCPV	58	#define CONFIG_ENV_IS_EMBEDDED 1
	59	#define CONFIG_ENV_ADDR_REDUND 0xF0018000
	60	#define CONFIG_ENV_SECT_SIZE_REDUND 0x4000
9acb626f HS	61	*/
9acb626f HS	62	#else
0e8d1586 JCPV	63	#define CONFIG_ENV_ADDR 0xFFE04000
0e8d1586 JCPV	64	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	65	#define CONFIG_ENV_IS_IN_FLASH 1
9acb626f HS	66	#endif
9acb626f HS	67
9acb626f	68
11799434 JL	69	/*
	70	* BOOTP options
	71	*/
	72	#define CONFIG_BOOTP_BOOTFILESIZE
	73	#define CONFIG_BOOTP_BOOTPATH
	74	#define CONFIG_BOOTP_GATEWAY
	75	#define CONFIG_BOOTP_HOSTNAME
	76
	77
dcaa7156 JL	78	/*
	79	* Command line configuration.
	80	*/
	81	#include <config_cmd_default.h>
	82
	83	#undef CONFIG_CMD_LOADB
870470db TL	84	#define CONFIG_CMD_MII
	85	#define CONFIG_CMD_NET
	86
0e0c4357 TL	87	#define CONFIG_MCFTMR
0e0c4357 TL	88
870470db TL	89	#define CONFIG_MCFFEC
	90	#ifdef CONFIG_MCFFEC
	91	# define CONFIG_NET_MULTI 1
	92	# define CONFIG_MII 1
0f3ba7e9	93	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	94	# define CONFIG_SYS_DISCOVER_PHY
	95	# define CONFIG_SYS_RX_ETH_BUFFER 8
	96	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
870470db	97
6d0f6bcf JCPV	98	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	99	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	100	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	101	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	102	# ifndef CONFIG_SYS_DISCOVER_PHY
870470db TL	103	# define FECDUPLEX FULL
	104	# define FECSPEED _100BASET
	105	# else
6d0f6bcf JCPV	106	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	107	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
870470db	108	# endif
6d0f6bcf	109	# endif /* CONFIG_SYS_DISCOVER_PHY */
870470db	110	#endif
dcaa7156	111
870470db TL	112	#ifdef CONFIG_MCFFEC
	113	# define CONFIG_ETHADDR 00:CF:52:82:EB:01
	114	# define CONFIG_IPADDR 192.162.1.2
	115	# define CONFIG_NETMASK 255.255.255.0
	116	# define CONFIG_SERVERIP 192.162.1.1
	117	# define CONFIG_GATEWAYIP 192.162.1.1
	118	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	119	#endif /* CONFIG_MCFFEC */
9acb626f HS	120
9acb626f HS	121	#define CONFIG_BOOTDELAY 5
6d0f6bcf JCPV	122	#define CONFIG_SYS_PROMPT "\nEV123 U-Boot> "
6d0f6bcf JCPV	123	#define CONFIG_SYS_LONGHELP /* undef to save memory */
9acb626f	124
dcaa7156	125	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	126	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
9acb626f	127	#else
6d0f6bcf	128	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
9acb626f	129	#endif
6d0f6bcf JCPV	130	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	131	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	132	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
9acb626f	133
6d0f6bcf	134	#define CONFIG_SYS_LOAD_ADDR 0x20000
9acb626f	135
6d0f6bcf JCPV	136	#define CONFIG_SYS_MEMTEST_START 0x100000
	137	#define CONFIG_SYS_MEMTEST_END 0x400000
	138	/#define CONFIG_SYS_DRAM_TEST 1 /
	139	#undef CONFIG_SYS_DRAM_TEST
9acb626f HS	140
9acb626f HS	141	/* Clock and PLL Configuration */
6d0f6bcf JCPV	142	#define CONFIG_SYS_HZ 10000000
6d0f6bcf JCPV	143	#define CONFIG_SYS_CLK 58982400 /* 9,8304MHz * 6 */
9acb626f HS	144
	145	/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
	146
6d0f6bcf JCPV	147	#define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */
6d0f6bcf JCPV	148	#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
9acb626f HS	149
	150	/*
	151	* Low Level Configuration Settings
	152	* (address mappings, register initial values, etc.)
	153	* You should know what you are doing if you make changes here.
	154	*/
6d0f6bcf	155	#define CONFIG_SYS_MBAR 0x40000000
9acb626f	156
9acb626f HS	157	/*-----------------------------------------------------------------------
	158	* Definitions for initial stack pointer and data area (in DPRAM)
	159	*/
6d0f6bcf JCPV	160	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
	161	#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
	162	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	163	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	164	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
9acb626f HS	165
	166	/*-----------------------------------------------------------------------
	167	* Start addresses for the final memory configuration
	168	* (Set up by the startup code)
6d0f6bcf	169	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
9acb626f	170	*/
6d0f6bcf JCPV	171	#define CONFIG_SYS_SDRAM_BASE1 0x00000000
6d0f6bcf JCPV	172	#define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */
9acb626f HS	173
9acb626f HS	174	/*
6d0f6bcf JCPV	175	#define CONFIG_SYS_SDRAM_BASE0 CONFIG_SYS_SDRAM_BASE1+CONFIG_SYS_SDRAM_SIZE110241024
6d0f6bcf JCPV	176	#define CONFIG_SYS_SDRAM_SIZE0 16 / / SDRAM size in MB */
9acb626f	177
6d0f6bcf JCPV	178	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1
6d0f6bcf JCPV	179	#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1
9acb626f	180
012522fe	181	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
6d0f6bcf JCPV	182	#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
6d0f6bcf JCPV	183	#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
9acb626f HS	184
	185	/* If M5282 port is fully implemented the monitor base will be behind
	186	* the vector table. */
6d0f6bcf JCPV	187	#if (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
6d0f6bcf JCPV	188	#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
9acb626f	189	#else
6d0f6bcf	190	#define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
9acb626f HS	191	#endif
9acb626f HS	192
6d0f6bcf JCPV	193	#define CONFIG_SYS_MONITOR_LEN 0x20000
	194	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	195	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
9acb626f HS	196
	197	/*
	198	* For booting Linux, the board info and command line data
	199	* have to be in the first 8 MB of memory, since this is
	200	* the maximum mapped by the Linux kernel during initialization ??
	201	*/
6d0f6bcf	202	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
9acb626f HS	203
	204	/*-----------------------------------------------------------------------
	205	* FLASH organization
	206	*/
6d0f6bcf JCPV	207	#define CONFIG_SYS_MAX_FLASH_SECT 35
	208	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	209	#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
	210	#define CONFIG_SYS_FLASH_PROTECTION
9acb626f HS	211
	212	/*-----------------------------------------------------------------------
	213	* Cache Configuration
	214	*/
6d0f6bcf	215	#define CONFIG_SYS_CACHELINE_SIZE 16
9acb626f HS	216
	217	/*-----------------------------------------------------------------------
	218	* Memory bank definitions
	219	*/
	220
012522fe TL	221	#define CONFIG_SYS_CS0_BASE 0xFFE00000
	222	#define CONFIG_SYS_CS0_CTRL 0x00001980
	223	#define CONFIG_SYS_CS0_MASK 0x001F0001
9acb626f	224
6d0f6bcf	225	#define CONFIG_SYS_CS3_BASE 0xE0000000
012522fe TL	226	#define CONFIG_SYS_CS0_CTRL 0x00001980
012522fe TL	227	#define CONFIG_SYS_CS3_MASK 0x000F0001
9acb626f HS	228
	229	/*-----------------------------------------------------------------------
	230	* Port configuration
	231	*/
6d0f6bcf JCPV	232	#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
	233	#define CONFIG_SYS_PADDR 0x0000000
	234	#define CONFIG_SYS_PADAT 0x0000000
9acb626f	235
6d0f6bcf JCPV	236	#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
	237	#define CONFIG_SYS_PBDDR 0x0000000
	238	#define CONFIG_SYS_PBDAT 0x0000000
9acb626f	239
6d0f6bcf JCPV	240	#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
	241	#define CONFIG_SYS_PCDDR 0x0000000
	242	#define CONFIG_SYS_PCDAT 0x0000000
9acb626f	243
6d0f6bcf JCPV	244	#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
	245	#define CONFIG_SYS_PCDDR 0x0000000
	246	#define CONFIG_SYS_PCDAT 0x0000000
9acb626f	247
6d0f6bcf JCPV	248	#define CONFIG_SYS_PEHLPAR 0xC0
	249	#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
	250	#define CONFIG_SYS_DDRUA 0x05
	251	#define CONFIG_SYS_PJPAR 0xFF
9acb626f HS	252
	253	/*-----------------------------------------------------------------------
	254	* CCM configuration
	255	*/
	256
6d0f6bcf	257	#define CONFIG_SYS_CCM_SIZ 0
9acb626f HS	258
	259	/---------------------------------------------------------------------/
	260	#endif /* _CONFIG_M5282EVB_H */
	261	/---------------------------------------------------------------------/