[people/ms/u-boot.git] / include / configs / ESTEEM192E.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_ESTEEM192E	1	/* ...on a EST ESTEEM192E	*/

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define CONFIG_FLASH_16BIT	1	/* Rom 16 bit data bus		*/

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef  CONFIG_8xx_CONS_NONE

#define MPC8XX_FACT	10		/* Multiply by 10		*/
#define MPC8XX_XIN	4915200	/* 4.915200 MHz in	- ??? - XXX	*/
#define CONFIG_SYS_PLPRCR_MF	((MPC8XX_FACT-1) << 20)
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz	*/

#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ	/* Force it - dont measure it */

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_BAUDRATE		9600
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootm 40030000" /* autoboot command	*/

#define CONFIG_BOOTARGS		"root=/dev/ram rw ramdisk=8192 "			\
				"ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
/*
 * Miscellaneous configurable options
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"BOOT: "	/* Monitor Command Prompt	*/
#define	CONFIG_SYS_CBSIZE	256			/* Console I/O Buffer Size	*/
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	8			/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks	*/


#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }


/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000

  /*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET


/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#ifdef	DEBUG
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)

/*-----------------------------------------------------------------------
 * SUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)

/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */


/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CONFIG_SYS_PLPRCR	(CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

#define CONFIG_SYS_PCMCIA_INTERRUPT	SIU_LEVEL6

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0
/*#define CONFIG_SYS_DER	0x02002000 */


/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CONFIG_SYS_OR_TIMING_FLASH	0x00000160
				/*(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
				 OR_SCY_5_CLK | OR_EHTR) */

#define CONFIG_SYS_OR0_REMAP	0x80000160     /*(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)*/
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	( FLASH_BASE0_PRELIM | 0x00000801 )

#define CONFIG_SYS_OR1_REMAP	CONFIG_SYS_OR0_REMAP
#define CONFIG_SYS_OR1_PRELIM	CONFIG_SYS_OR0_PRELIM
#define CONFIG_SYS_BR1_PRELIM	( FLASH_BASE1_PRELIM | 0x00000801 )

/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_BASE3_PRELIM	0x04000000	/* SDRAM bank #1	*/
#define	SDRAM_MAX_SIZE		0x02000000	/* max 32 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	0xFC000E00
#define CONFIG_SYS_BR2_PRELIM	(SDRAM_BASE2_PRELIM | 0x00000081)

#define	CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_OR2_PRELIM
#define CONFIG_SYS_BR3_PRELIM	(SDRAM_BASE3_PRELIM | 0x00000081)


/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA	97		/* start with divider for 100 MHz	*/

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	0x18803112
#define CONFIG_SYS_MAMR_9COL	0x18803112	/* same as 8 column because its just easier to port with*/

#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	37	#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */
	38
2ae18241 WD	39	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	40
0f8c9768 WD	41	#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */
	42
	43	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	44	#undef CONFIG_8xx_CONS_SMC2
	45	#undef CONFIG_8xx_CONS_NONE
	46
	47	#define MPC8XX_FACT 10 /* Multiply by 10 */
	48	#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */
6d0f6bcf	49	#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20)
0f8c9768 WD	50	#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */
	51
	52	#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
	53
	54	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	55
	56	#define CONFIG_BAUDRATE 9600
	57	#if 0
	58	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	59	#else
	60	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	61	#endif
	62	#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */
	63
	64	#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \
	65	"ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
	66	/*
	67	* Miscellaneous configurable options
	68	*/
	69
	70	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	71	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
0f8c9768 WD	72
	73	#undef CONFIG_WATCHDOG /* watchdog disabled */
	74
5d2ebe1b JL	75	/*
	76	* BOOTP options
	77	*/
	78	#define CONFIG_BOOTP_SUBNETMASK
	79	#define CONFIG_BOOTP_GATEWAY
	80	#define CONFIG_BOOTP_HOSTNAME
	81	#define CONFIG_BOOTP_BOOTPATH
	82	#define CONFIG_BOOTP_BOOTFILESIZE
	83
0f8c9768	84
dcaa7156 JL	85	/*
	86	* Command line configuration.
	87	*/
	88	#include <config_cmd_default.h>
	89
0f8c9768	90
6d0f6bcf JCPV	91	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	92	#define CONFIG_SYS_PROMPT "BOOT: " /* Monitor Command Prompt */
	93	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	94	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	95	#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
	96	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	97
6d0f6bcf JCPV	98	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	99	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
0f8c9768	100
6d0f6bcf	101	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
0f8c9768	102
6d0f6bcf	103	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
0f8c9768 WD	104
0f8c9768 WD	105
6d0f6bcf	106	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
0f8c9768 WD	107
	108
	109	/*
	110	* Low Level Configuration Settings
	111	* (address mappings, register initial values, etc.)
	112	* You should know what you are doing if you make changes here.
	113	*/
	114	/*-----------------------------------------------------------------------
	115	* Internal Memory Mapped Register
	116	*/
6d0f6bcf	117	#define CONFIG_SYS_IMMR 0xFF000000
0f8c9768 WD	118
	119	/*-----------------------------------------------------------------------
	120	* Definitions for initial stack pointer and data area (in DPRAM)
	121	*/
6d0f6bcf	122	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	123	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	124	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	125	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	126
0f8c9768 WD	127
0f8c9768 WD	128	/*-----------------------------------------------------------------------
	129	* Start addresses for the final memory configuration
	130	* (Set up by the startup code)
6d0f6bcf	131	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768	132	*/
6d0f6bcf JCPV	133	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	134	#define CONFIG_SYS_FLASH_BASE 0x40000000
0f8c9768	135	#ifdef DEBUG
6d0f6bcf	136	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
0f8c9768	137	#else
6d0f6bcf	138	#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
0f8c9768	139	#endif
6d0f6bcf JCPV	140	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	141	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
0f8c9768 WD	142
	143	/*
	144	* For booting Linux, the board info and command line data
	145	* have to be in the first 8 MB of memory, since this is
	146	* the maximum mapped by the Linux kernel during initialization.
	147	*/
6d0f6bcf	148	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0f8c9768 WD	149	/*-----------------------------------------------------------------------
	150	* FLASH organization
	151	*/
6d0f6bcf JCPV	152	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	153	#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
0f8c9768	154
6d0f6bcf JCPV	155	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	156	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0f8c9768	157
5a1aceb0	158	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	159	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	160	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
0f8c9768 WD	161	/*-----------------------------------------------------------------------
	162	* Cache Configuration
	163	*/
6d0f6bcf	164	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
0f8c9768 WD	165
	166	/*-----------------------------------------------------------------------
	167	* SYPCR - System Protection Control 11-9
	168	* SYPCR can only be written once after reset!
	169	*-----------------------------------------------------------------------
	170	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	171	*/
6d0f6bcf	172	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
0f8c9768 WD	173
	174	/*-----------------------------------------------------------------------
	175	* SUMCR - SIU Module Configuration 11-6
	176	*-----------------------------------------------------------------------
	177	* PCMCIA config., multi-function pin tri-state
	178	*/
6d0f6bcf	179	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01) /* DBGC00 */
0f8c9768 WD	180
	181	/*-----------------------------------------------------------------------
	182	* TBSCR - Time Base Status and Control 11-26
	183	*-----------------------------------------------------------------------
	184	* Clear Reference Interrupt Status, Timebase freezing enabled
	185	*/
6d0f6bcf	186	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF \| TBSCR_TBE)
0f8c9768 WD	187
	188	/* (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF) */
	189
	190
	191	/*-----------------------------------------------------------------------
	192	* PISCR - Periodic Interrupt Status and Control 11-31
	193	*-----------------------------------------------------------------------
	194	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	195	*/
6d0f6bcf	196	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
0f8c9768 WD	197
	198	/*-----------------------------------------------------------------------
	199	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	200	*-----------------------------------------------------------------------
	201	* Reset PLL lock status sticky bit, timer expired status bit and timer
	202	* interrupt status bit - leave PLL multiplication factor unchanged !
	203	*/
6d0f6bcf	204	#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF \| PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
0f8c9768 WD	205
	206	/*-----------------------------------------------------------------------
	207	* SCCR - System Clock and reset Control Register 15-27
	208	*-----------------------------------------------------------------------
	209	* Set clock output, timebase and RTC source and divider,
	210	* power management and some other internal clocks
	211	*/
	212	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	213	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
0f8c9768 WD	214	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	215	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	216	SCCR_DFALCD00)
	217
	218	/*-----------------------------------------------------------------------
	219	* PCMCIA stuff
	220	*-----------------------------------------------------------------------
	221	*
	222	*/
6d0f6bcf JCPV	223	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	224	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	225	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	226	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	227	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	228	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	229	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	230	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
0f8c9768	231
6d0f6bcf	232	#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6
0f8c9768 WD	233
	234	/*-----------------------------------------------------------------------
	235	*
	236	*-----------------------------------------------------------------------
	237	*
	238	*/
6d0f6bcf JCPV	239	/#define CONFIG_SYS_DER 0x2002000F/
	240	#define CONFIG_SYS_DER 0
	241	/#define CONFIG_SYS_DER 0x02002000 /
0f8c9768 WD	242
	243
	244	/*
	245	* Init Memory Controller:
	246	*
	247	* BR0/1 and OR0/1 (FLASH)
	248	*/
	249
	250	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	251	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	252
	253	/* used to re-map FLASH both when starting from SRAM or FLASH:
	254	* restrict access enough to keep SRAM working (if any)
	255	* but not too much to meddle with FLASH accesses
	256	*/
6d0f6bcf JCPV	257	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	258	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
0f8c9768 WD	259
0f8c9768 WD	260	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf	261	#define CONFIG_SYS_OR_TIMING_FLASH 0x00000160
0f8c9768 WD	262	/*(OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| \
	263	OR_SCY_5_CLK \| OR_EHTR) */
	264
6d0f6bcf JCPV	265	#define CONFIG_SYS_OR0_REMAP 0x80000160 /(CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)/
	266	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	267	#define CONFIG_SYS_BR0_PRELIM ( FLASH_BASE0_PRELIM \| 0x00000801 )
0f8c9768	268
6d0f6bcf JCPV	269	#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
	270	#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
	271	#define CONFIG_SYS_BR1_PRELIM ( FLASH_BASE1_PRELIM \| 0x00000801 )
0f8c9768 WD	272
	273	/*
	274	* BR2/3 and OR2/3 (SDRAM)
	275	*
	276	*/
	277	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	278	#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */
	279	#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */
	280
	281	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	282	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
0f8c9768	283
6d0f6bcf JCPV	284	#define CONFIG_SYS_OR2_PRELIM 0xFC000E00
6d0f6bcf JCPV	285	#define CONFIG_SYS_BR2_PRELIM (SDRAM_BASE2_PRELIM \| 0x00000081)
0f8c9768	286
6d0f6bcf JCPV	287	#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
6d0f6bcf JCPV	288	#define CONFIG_SYS_BR3_PRELIM (SDRAM_BASE3_PRELIM \| 0x00000081)
0f8c9768 WD	289
	290
	291	/*
	292	* Memory Periodic Timer Prescaler
	293	*/
	294
	295	/* periodic timer for refresh */
6d0f6bcf	296	#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
0f8c9768 WD	297
0f8c9768 WD	298	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	299	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	300	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
0f8c9768 WD	301
0f8c9768 WD	302	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	303	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	304	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
0f8c9768 WD	305
	306	/*
	307	* MAMR settings for SDRAM
	308	*/
	309
	310	/* 8 column SDRAM */
6d0f6bcf JCPV	311	#define CONFIG_SYS_MAMR_8COL 0x18803112
6d0f6bcf JCPV	312	#define CONFIG_SYS_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/
0f8c9768	313
0f8c9768	314	#endif /* __CONFIG_H */