[people/ms/u-boot.git] / include / configs / FADS823.h

 /*
  * A collection of structures, addresses, and values associated with
  * the Motorola 860T FADS board.  Copied from the MBX stuff.
  * Magnus Damm added defines for 8xxrom and extended bd_info.
  * Helmut Buchsbaum added bitvalues for BCSRx
  *
  * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
  */

/*
 * 1999-nov-26: The FADS is using the following physical memorymap:
 *
 * ff020000 -> ff02ffff : pcmcia     io remapping
 * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by U-Boot
 * ff000000 -> ff00ffff : IMAP       internal in the cpu
 * e0000000 -> f3ffffff : pcmcia     memory remapping by m8xx_pcmcia
 * fe000000 -> fe1fffff : flash      connected to CS0, setup by U-Boot
 * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
*/

#define CFG_PCMCIA_IO_ADDR	0xff020000
#define CFG_PCMCIA_IO_SIZE	0x10000
#define CFG_PCMCIA_MEM_ADDR	0xe0000000
#define CFG_PCMCIA_MEM_SIZE	0x10000
#define CFG_IMMR		0xFF000000
#define	CFG_SDRAM_SIZE		(4<<20) /* standard FADS has 4M */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x02800000
#define BCSR_ADDR		((uint) 0xff010000)
#define FLASH_BASE0_PRELIM	0x02800000	/* FLASH bank #0	*/

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define	CONFIG_ETHADDR		08:00:22:50:70:63	/* Ethernet address */
#define CONFIG_ENV_OVERWRITE	1	/* Overwrite the environment */

#define CONFIG_VIDEO		1	/* To enable video controller support */
#define CONFIG_HARD_I2C		1	/* To I2C with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

/*#define CONFIG_PCMCIA		1	/ * To enable PCMCIA support */

/* Video related */

#define CONFIG_VIDEO_LOGO			1	/* Show the logo */
#define CONFIG_VIDEO_ENCODER_AD7176		1	/* Enable this encoder */
#define CONFIG_VIDEO_ENCODER_AD7176_ADDR	0x54	/* Default on fads */
#define CONFIG_VIDEO_SIZE			(2*1024*1024)
/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */

/* Wireless 56Khz 4PPM keyboard on SMCx */

/*#define CONFIG_KEYBOARD		1 */
#define CONFIG_WL_4PPM_KEYBOARD_SMC	0	/* SMC to use (0 indexed) */

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC823		1
#define CONFIG_MPC823FADS	1
#define CONFIG_FADS		1

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200

/* Set the CPU speed to 50Mhz on the FADS */

#if 0
#define MPC8XX_FACT	10			/* Multiply by 10		*/
#define MPC8XX_XIN	5000000			/* 5 MHz in	*/
#else
#define MPC8XX_FACT	10			/* Multiply by 10 */
#define MPC8XX_XIN	5000000			/* 5 MHz in */
#define CFG_PLPRCR_MF	(MPC8XX_FACT-1) << 20	/* From 0 to 4095 */
#endif
#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#if 1
#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
#define CONFIG_LOADS_ECHO	0	/* Dont echoes received characters */
#define CONFIG_BOOTARGS		""
#define CONFIG_BOOTCOMMAND							\
"bootp ;" 									\
"setenv bootargs console=tty0 console=ttyS0 " 					\
"root=/dev/nfs nfsroot=${serverip}:${rootpath} " 				\
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" 	\
"bootm"
#else
#define CONFIG_BOOTDELAY	0	/* autoboot disabled		*/
#endif

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_NISDOMAIN
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_NTPSERVER
#define CONFIG_BOOTP_TIMEOFFSET


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>


/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP				/* undef to save memory		*/
#define	CFG_PROMPT		":>"		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS		16		/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x01000000	/* 0 ... 16 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x00100000	/* default load address */

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR_SIZE		((uint)(64 * 1024))

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
 */
#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte */
#if 0
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CFG_MONITOR_LEN		(512 << 10)	/* Reserve 512 kB for Monitor	*/
#endif
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
#define	CFG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control					11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration						11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control					11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer  *
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CFG_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CFG_PLPRCR_MF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR       (SCCR_TBS     | \
				SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
				SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
				SCCR_DFALCD00)

 /*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER		0

/* Because of the way the 860 starts up and assigns CS0 the
* entire address space, we have to set the memory controller
* differently.  Normally, you write the option register
* first, and then enable the chip select by writing the
* base register.  For CS0, you must write the base register
* first, followed by the option register.
*/

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */
/* the other CS:s are determined by looking at parameters in BCSRx */

#define BCSR_SIZE		((uint)(64 * 1024))

#define FLASH_BASE1_PRELIM	0x00000000	/* FLASH bank #1	*/

#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xFFE00000	/* OR addr mask */

/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0	*/
#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 1 Mbyte until detected and only 1 Mbyte is needed*/
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )

/* BCSRx - Board Control and Status Registers */
#define CFG_OR1_REMAP	CFG_OR0_REMAP
#define CFG_OR1_PRELIM	0xffff8110									/* 64Kbyte address space */
#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V )


/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CFG_MAMR_PTA		97		/* start with divider for 100 MHz	*/

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#define CFG_MAMR		0x13a01114
/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD			0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM			0x02		/* Software reboot			*/

/* values according to the manual */

#define	BCSR0			((uint) (BCSR_ADDR + 00))
#define	BCSR1			((uint) (BCSR_ADDR + 0x04))
#define	BCSR2			((uint) (BCSR_ADDR + 0x08))
#define	BCSR3			((uint) (BCSR_ADDR + 0x0c))
#define	BCSR4			((uint) (BCSR_ADDR + 0x10))

/* FADS bitvalues by Helmut Buchsbaum
 * see MPC8xxADS User's Manual for a proper description
 * of the following structures
 */

#define BCSR0_ERB       ((uint)0x80000000)
#define BCSR0_IP        ((uint)0x40000000)
#define BCSR0_BDIS      ((uint)0x10000000)
#define BCSR0_BPS_MASK  ((uint)0x0C000000)
#define BCSR0_ISB_MASK  ((uint)0x01800000)
#define BCSR0_DBGC_MASK ((uint)0x00600000)
#define BCSR0_DBPC_MASK ((uint)0x00180000)
#define BCSR0_EBDF_MASK ((uint)0x00060000)

#define BCSR1_FLASH_EN           ((uint)0x80000000)
#define BCSR1_DRAM_EN            ((uint)0x40000000)
#define BCSR1_ETHEN              ((uint)0x20000000)
#define BCSR1_IRDEN              ((uint)0x10000000)
#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
#define BCSR1_BCSR_EN            ((uint)0x02000000)
#define BCSR1_RS232EN_1          ((uint)0x01000000)
#define BCSR1_PCCEN              ((uint)0x00800000)
#define BCSR1_PCCVCC0            ((uint)0x00400000)
#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
#define BCSR1_RS232EN_2          ((uint)0x00040000)
#define BCSR1_SDRAM_EN           ((uint)0x00020000)
#define BCSR1_PCCVCC1            ((uint)0x00010000)

#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
#define BCSR2_FLASH_PD_SHIFT	 28
#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
#define BCSR2_DRAM_PD_SHIFT      23
#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)

#define BCSR3_DBID_MASK          ((ushort)0x3800)
#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
#define BCSR3_BREVNR0            ((ushort)0x0080)
#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
#define BCSR3_BREVN1             ((ushort)0x0008)
#define BCSR3_BREVN2_MASK        ((ushort)0x0003)

#define BCSR4_ETHLOOP            ((uint)0x80000000)
#define BCSR4_TFPLDL             ((uint)0x40000000)
#define BCSR4_TPSQEL             ((uint)0x20000000)
#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
#ifdef CONFIG_MPC823
#define BCSR4_USB_EN             ((uint)0x08000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860SAR
#define BCSR4_UTOPIA_EN          ((uint)0x08000000)
#endif /* CONFIG_MPC860SAR */
#ifdef CONFIG_MPC860T
#define BCSR4_FETH_EN            ((uint)0x08000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_USB_SPEED          ((uint)0x04000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG0           ((uint)0x04000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VCCO               ((uint)0x02000000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHFDE            ((uint)0x02000000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_ON           ((uint)0x00800000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_VDO_EKT_CLK_EN     ((uint)0x00400000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHCFG1           ((uint)0x00400000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_VIDEO_RST          ((uint)0x00200000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC860T
#define BCSR4_FETHRST            ((uint)0x00200000)
#endif /* CONFIG_MPC860T */
#ifdef CONFIG_MPC823
#define BCSR4_MODEM_EN           ((uint)0x00100000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC823
#define BCSR4_DATA_VOICE         ((uint)0x00080000)
#endif /* CONFIG_MPC823 */
#ifdef CONFIG_MPC850
#define BCSR4_DATA_VOICE         ((uint)0x00080000)
#endif /* CONFIG_MPC850 */

#define CONFIG_DRAM_50MHZ		1
#define CONFIG_SDRAM_50MHZ

/* We don't use the 8259.
*/
#define NR_8259_INTS	0

/* Machine type
*/
#define _MACH_8xx (_MACH_fads)

/*
 * MPC8xx CPM Options
 */
#define CONFIG_SCC_ENET 1
#define CONFIG_SCC2_ENET 1
#undef  CONFIG_FEC_ENET
#undef  CONFIG_CPM_IIC
#undef  CONFIG_UCODE_PATCH

#define CONFIG_DISK_SPINUP_TIME 1000000

/* PCMCIA configuration */

#define PCMCIA_MAX_SLOTS    1

#ifdef CONFIG_MPC860
#define PCMCIA_SLOT_A 1
#endif

#define CFG_DAUGHTERBOARD

#endif	/* __CONFIG_H */
Commit	Line	Data
5b1d7137 WD	1	/*
	2	* A collection of structures, addresses, and values associated with
	3	* the Motorola 860T FADS board. Copied from the MBX stuff.
	4	* Magnus Damm added defines for 8xxrom and extended bd_info.
	5	* Helmut Buchsbaum added bitvalues for BCSRx
	6	*
	7	* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
	8	*/
	9
	10	/*
	11	* 1999-nov-26: The FADS is using the following physical memorymap:
	12	*
	13	* ff020000 -> ff02ffff : pcmcia io remapping
	14	* ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot
	15	* ff000000 -> ff00ffff : IMAP internal in the cpu
	16	* e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia
	17	* fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot
	18	* 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
	19	*/
	20
	21	#define CFG_PCMCIA_IO_ADDR 0xff020000
	22	#define CFG_PCMCIA_IO_SIZE 0x10000
	23	#define CFG_PCMCIA_MEM_ADDR 0xe0000000
	24	#define CFG_PCMCIA_MEM_SIZE 0x10000
	25	#define CFG_IMMR 0xFF000000
2535d602	26	#define CFG_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
5b1d7137 WD	27	#define CFG_SDRAM_BASE 0x00000000
	28	#define CFG_FLASH_BASE 0x02800000
	29	#define BCSR_ADDR ((uint) 0xff010000)
	30	#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
	31
	32	/* ------------------------------------------------------------------------- */
	33
	34	/*
	35	* board/config.h - configuration options, board specific
	36	*/
	37
	38	#ifndef __CONFIG_H
	39	#define __CONFIG_H
	40
	41	#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
	42	#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
	43
	44	#define CONFIG_VIDEO 1 /* To enable video controller support */
	45	#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
	46	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	47	#define CFG_I2C_SLAVE 0x7F
	48
5b1d7137 WD	49	/#define CONFIG_PCMCIA 1 / To enable PCMCIA support */
	50
	51	/* Video related */
	52
	53	#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
	54	#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
	55	#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
	56	#define CONFIG_VIDEO_SIZE (210241024)
	57	/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
	58
	59	/* Wireless 56Khz 4PPM keyboard on SMCx */
	60
682011ff	61	/#define CONFIG_KEYBOARD 1 /
5b1d7137 WD	62	#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
	63
	64	/*
	65	* High Level Configuration Options
	66	* (easy to change)
	67	*/
5b1d7137 WD	68	#define CONFIG_MPC823 1
	69	#define CONFIG_MPC823FADS 1
	70	#define CONFIG_FADS 1
	71
	72	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	73	#undef CONFIG_8xx_CONS_SMC2
	74	#undef CONFIG_8xx_CONS_NONE
	75	#define CONFIG_BAUDRATE 115200
	76
	77	/* Set the CPU speed to 50Mhz on the FADS */
	78
	79	#if 0
	80	#define MPC8XX_FACT 10 /* Multiply by 10 */
	81	#define MPC8XX_XIN 5000000 /* 5 MHz in */
	82	#else
	83	#define MPC8XX_FACT 10 /* Multiply by 10 */
	84	#define MPC8XX_XIN 5000000 /* 5 MHz in */
	85	#define CFG_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */
	86	#endif
	87	#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
	88
	89	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	90
	91	#if 1
	92	#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
	93	#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
	94	#define CONFIG_BOOTARGS ""
	95	#define CONFIG_BOOTCOMMAND \
	96	"bootp ;" \
	97	"setenv bootargs console=tty0 console=ttyS0 " \
fe126d8b WD	98	"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	99	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \
5b1d7137 WD	100	"bootm"
	101	#else
	102	#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
	103	#endif
	104
	105	#undef CONFIG_WATCHDOG /* watchdog disabled */
	106
5d2ebe1b JL	107
	108	/*
	109	* BOOTP options
	110	*/
	111	#define CONFIG_BOOTP_SUBNETMASK
	112	#define CONFIG_BOOTP_GATEWAY
	113	#define CONFIG_BOOTP_HOSTNAME
	114	#define CONFIG_BOOTP_BOOTPATH
	115	#define CONFIG_BOOTP_BOOTFILESIZE
	116	#define CONFIG_BOOTP_SUBNETMASK
	117	#define CONFIG_BOOTP_GATEWAY
	118	#define CONFIG_BOOTP_HOSTNAME
	119	#define CONFIG_BOOTP_NISDOMAIN
	120	#define CONFIG_BOOTP_BOOTPATH
	121	#define CONFIG_BOOTP_DNS
	122	#define CONFIG_BOOTP_DNS2
	123	#define CONFIG_BOOTP_SEND_HOSTNAME
	124	#define CONFIG_BOOTP_NTPSERVER
	125	#define CONFIG_BOOTP_TIMEOFFSET
	126
5b1d7137	127
60a0876b JL	128	/*
	129	* Command line configuration.
	130	*/
	131	#include <config_cmd_default.h>
	132
5b1d7137 WD	133
	134	/*
	135	* Miscellaneous configurable options
	136	*/
	137	#define CFG_LONGHELP /* undef to save memory */
	138	#define CFG_PROMPT ":>" /* Monitor Command Prompt */
60a0876b	139	#if defined(CONFIG_CMD_KGDB)
5b1d7137 WD	140	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	141	#else
	142	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	143	#endif
	144	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	145	#define CFG_MAXARGS 16 /* max number of command args */
	146	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	147
	148	#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
	149	#define CFG_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */
	150
	151	#define CFG_LOAD_ADDR 0x00100000 /* default load address */
	152
	153	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	154
	155	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	156
	157	/*
	158	* Low Level Configuration Settings
	159	* (address mappings, register initial values, etc.)
	160	* You should know what you are doing if you make changes here.
	161	*/
	162	/*-----------------------------------------------------------------------
	163	* Internal Memory Mapped Register
	164	*/
	165	#define CFG_IMMR_SIZE ((uint)(64 * 1024))
	166
	167	/*-----------------------------------------------------------------------
	168	* Definitions for initial stack pointer and data area (in DPRAM)
	169	*/
	170	#define CFG_INIT_RAM_ADDR CFG_IMMR
	171	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	172	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	173	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	174	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	175
	176	/*-----------------------------------------------------------------------
	177	* Start addresses for the final memory configuration
	178	* (Set up by the startup code)
	179	* Please note that CFG_SDRAM_BASE _must_ start at 0
	180	* Also NOTE that it doesn't mean SDRAM - it means MEMORY.
	181	*/
	182	#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
	183	#if 0
	184	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	185	#else
	186	#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
	187	#endif
	188	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	189	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	190
	191	/*
	192	* For booting Linux, the board info and command line data
	193	* have to be in the first 8 MB of memory, since this is
	194	* the maximum mapped by the Linux kernel during initialization.
	195	*/
	196	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	197	/*-----------------------------------------------------------------------
	198	* FLASH organization
	199	*/
	200	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	201	#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
	202
	203	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
204	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
205
206	#define CFG_ENV_IS_IN_FLASH 1
207	#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
208	#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
209
210	/*-----------------------------------------------------------------------
211	* Cache Configuration
212	*/
213	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
60a0876b	214	#if defined(CONFIG_CMD_KGDB)
5b1d7137 WD	215	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	216	#endif
	217
	218	/*-----------------------------------------------------------------------
	219	* SYPCR - System Protection Control 11-9
	220	* SYPCR can only be written once after reset!
	221	*-----------------------------------------------------------------------
	222	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	223	*/
	224	#if defined(CONFIG_WATCHDOG)
	225	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	226	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	227	#else
	228	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	229	#endif
	230
	231	/*-----------------------------------------------------------------------
	232	* SIUMCR - SIU Module Configuration 11-6
	233	*-----------------------------------------------------------------------
	234	* PCMCIA config., multi-function pin tri-state
	235	*/
	236	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
	237
	238	/*-----------------------------------------------------------------------
	239	* TBSCR - Time Base Status and Control 11-26
	240	*-----------------------------------------------------------------------
	241	* Clear Reference Interrupt Status, Timebase freezing enabled
	242	*/
	243	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
	244
	245	/*-----------------------------------------------------------------------
	246	* PISCR - Periodic Interrupt Status and Control 11-31
	247	*-----------------------------------------------------------------------
	248	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	249	*/
	250	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	251
	252	/*-----------------------------------------------------------------------
	253	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	254	*-----------------------------------------------------------------------
	255	* Reset PLL lock status sticky bit, timer expired status bit and timer *
	256	* interrupt status bit - leave PLL multiplication factor unchanged !
	257	*/
	258	#define CFG_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST \| CFG_PLPRCR_MF)
	259
	260	/*-----------------------------------------------------------------------
	261	* SCCR - System Clock and reset Control Register 15-27
	262	*-----------------------------------------------------------------------
	263	* Set clock output, timebase and RTC source and divider,
	264	* power management and some other internal clocks
	265	*/
	266	#define SCCR_MASK SCCR_EBDF11
	267	#define CFG_SCCR (SCCR_TBS \| \
	268	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	269	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	270	SCCR_DFALCD00)
	271
	272	/*-----------------------------------------------------------------------
	273	*
	274	*-----------------------------------------------------------------------
	275	*
	276	*/
	277	#define CFG_DER 0
	278
279	/* Because of the way the 860 starts up and assigns CS0 the
280	* entire address space, we have to set the memory controller
281	* differently. Normally, you write the option register
282	* first, and then enable the chip select by writing the
283	* base register. For CS0, you must write the base register
284	* first, followed by the option register.
285	*/
286
287	/*
288	* Init Memory Controller:
289	*
290	* BR0/1 and OR0/1 (FLASH)
291	*/
292	/* the other CS:s are determined by looking at parameters in BCSRx */
293
294	#define BCSR_SIZE ((uint)(64 * 1024))
295
296	#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
297
298	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
299	#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
300
301	/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
302	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_3_CLK \| OR_TRLX)
303
304	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
305	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
306	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
307
308	/* BCSRx - Board Control and Status Registers */
309	#define CFG_OR1_REMAP CFG_OR0_REMAP
310	#define CFG_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
311	#define CFG_BR1_PRELIM ((BCSR_ADDR) \| BR_V )
312
313
314	/*
315	* Memory Periodic Timer Prescaler
316	*/
317
318	/* periodic timer for refresh */
319	#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
320
321	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
322	#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
323	#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
324
325	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
326	#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
327	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
328
329	/*
330	* MAMR settings for SDRAM
331	*/
332
333	/* 8 column SDRAM */
334	#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
335	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
336	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
337	/* 9 column SDRAM */
338	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
339	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
340	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
341
342	#define CFG_MAMR 0x13a01114
343	/*
344	* Internal Definitions
345	*
346	* Boot Flags
347	*/
348	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
349	#define BOOTFLAG_WARM 0x02 /* Software reboot */
350
351	/* values according to the manual */
352
353	#define BCSR0 ((uint) (BCSR_ADDR + 00))
354	#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
355	#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
356	#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
357	#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
358
359	/* FADS bitvalues by Helmut Buchsbaum
360	* see MPC8xxADS User's Manual for a proper description
361	* of the following structures
362	*/
363
364	#define BCSR0_ERB ((uint)0x80000000)
365	#define BCSR0_IP ((uint)0x40000000)
366	#define BCSR0_BDIS ((uint)0x10000000)
367	#define BCSR0_BPS_MASK ((uint)0x0C000000)
368	#define BCSR0_ISB_MASK ((uint)0x01800000)
369	#define BCSR0_DBGC_MASK ((uint)0x00600000)
370	#define BCSR0_DBPC_MASK ((uint)0x00180000)
371	#define BCSR0_EBDF_MASK ((uint)0x00060000)
372
373	#define BCSR1_FLASH_EN ((uint)0x80000000)
374	#define BCSR1_DRAM_EN ((uint)0x40000000)
375	#define BCSR1_ETHEN ((uint)0x20000000)
376	#define BCSR1_IRDEN ((uint)0x10000000)
377	#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
378	#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
379	#define BCSR1_BCSR_EN ((uint)0x02000000)
380	#define BCSR1_RS232EN_1 ((uint)0x01000000)
381	#define BCSR1_PCCEN ((uint)0x00800000)
382	#define BCSR1_PCCVCC0 ((uint)0x00400000)
383	#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
384	#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
385	#define BCSR1_RS232EN_2 ((uint)0x00040000)
386	#define BCSR1_SDRAM_EN ((uint)0x00020000)
387	#define BCSR1_PCCVCC1 ((uint)0x00010000)
388
389	#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
b54d32b4	390	#define BCSR2_FLASH_PD_SHIFT 28
5b1d7137	391	#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
b54d32b4	392	#define BCSR2_DRAM_PD_SHIFT 23
5b1d7137 WD	393	#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
	394	#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
	395
	396	#define BCSR3_DBID_MASK ((ushort)0x3800)
	397	#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
	398	#define BCSR3_BREVNR0 ((ushort)0x0080)
	399	#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
	400	#define BCSR3_BREVN1 ((ushort)0x0008)
	401	#define BCSR3_BREVN2_MASK ((ushort)0x0003)
	402
	403	#define BCSR4_ETHLOOP ((uint)0x80000000)
	404	#define BCSR4_TFPLDL ((uint)0x40000000)
	405	#define BCSR4_TPSQEL ((uint)0x20000000)
	406	#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
	407	#ifdef CONFIG_MPC823
	408	#define BCSR4_USB_EN ((uint)0x08000000)
	409	#endif /* CONFIG_MPC823 */
	410	#ifdef CONFIG_MPC860SAR
	411	#define BCSR4_UTOPIA_EN ((uint)0x08000000)
	412	#endif /* CONFIG_MPC860SAR */
	413	#ifdef CONFIG_MPC860T
	414	#define BCSR4_FETH_EN ((uint)0x08000000)
	415	#endif /* CONFIG_MPC860T */
	416	#ifdef CONFIG_MPC823
	417	#define BCSR4_USB_SPEED ((uint)0x04000000)
	418	#endif /* CONFIG_MPC823 */
	419	#ifdef CONFIG_MPC860T
	420	#define BCSR4_FETHCFG0 ((uint)0x04000000)
	421	#endif /* CONFIG_MPC860T */
	422	#ifdef CONFIG_MPC823
	423	#define BCSR4_VCCO ((uint)0x02000000)
	424	#endif /* CONFIG_MPC823 */
	425	#ifdef CONFIG_MPC860T
	426	#define BCSR4_FETHFDE ((uint)0x02000000)
	427	#endif /* CONFIG_MPC860T */
	428	#ifdef CONFIG_MPC823
	429	#define BCSR4_VIDEO_ON ((uint)0x00800000)
	430	#endif /* CONFIG_MPC823 */
	431	#ifdef CONFIG_MPC823
	432	#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
	433	#endif /* CONFIG_MPC823 */
	434	#ifdef CONFIG_MPC860T
	435	#define BCSR4_FETHCFG1 ((uint)0x00400000)
	436	#endif /* CONFIG_MPC860T */
	437	#ifdef CONFIG_MPC823
	438	#define BCSR4_VIDEO_RST ((uint)0x00200000)
	439	#endif /* CONFIG_MPC823 */
	440	#ifdef CONFIG_MPC860T
	441	#define BCSR4_FETHRST ((uint)0x00200000)
	442	#endif /* CONFIG_MPC860T */
	443	#ifdef CONFIG_MPC823
	444	#define BCSR4_MODEM_EN ((uint)0x00100000)
	445	#endif /* CONFIG_MPC823 */
	446	#ifdef CONFIG_MPC823
	447	#define BCSR4_DATA_VOICE ((uint)0x00080000)
	448	#endif /* CONFIG_MPC823 */
	449	#ifdef CONFIG_MPC850
	450	#define BCSR4_DATA_VOICE ((uint)0x00080000)
	451	#endif /* CONFIG_MPC850 */
	452
	453	#define CONFIG_DRAM_50MHZ 1
	454	#define CONFIG_SDRAM_50MHZ
	455
5b1d7137 WD	456	/* We don't use the 8259.
	457	*/
	458	#define NR_8259_INTS 0
	459
	460	/* Machine type
	461	*/
	462	#define _MACH_8xx (_MACH_fads)
	463
	464	/*
	465	* MPC8xx CPM Options
	466	*/
	467	#define CONFIG_SCC_ENET 1
	468	#define CONFIG_SCC2_ENET 1
	469	#undef CONFIG_FEC_ENET
	470	#undef CONFIG_CPM_IIC
	471	#undef CONFIG_UCODE_PATCH
	472
	473	#define CONFIG_DISK_SPINUP_TIME 1000000
	474
	475	/* PCMCIA configuration */
	476
	477	#define PCMCIA_MAX_SLOTS 1
	478
	479	#ifdef CONFIG_MPC860
	480	#define PCMCIA_SLOT_A 1
	481	#endif
	482
180d3f74 WD	483	#define CFG_DAUGHTERBOARD
180d3f74 WD	484
5b1d7137	485	#endif /* __CONFIG_H */