]>
Commit | Line | Data |
---|---|---|
5b1d7137 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * Keith Outwater, keith_outwater@mvis.com | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
26 | * board/config_GEN860T.h - board specific configuration options | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_GEN860T_H | |
30 | #define __CONFIG_H | |
31 | ||
32 | /* | |
33 | * High Level Configuration Options | |
34 | */ | |
35 | #define CONFIG_MPC860 | |
36 | #define CONFIG_GEN860T | |
37 | ||
38 | /* | |
39 | * Identify the board | |
40 | */ | |
7aa78614 WD |
41 | #if !defined(CONFIG_SC) |
42 | #define CONFIG_IDENT_STRING " B2" | |
43 | #else | |
44 | #define CONFIG_IDENT_STRING " SC" | |
45 | #endif | |
5b1d7137 WD |
46 | |
47 | /* | |
48 | * Don't depend on the RTC clock to determine clock frequency - | |
49 | * the 860's internal rtc uses a 32.768 KHz clock which is | |
50 | * generated by the DS1337 - and the DS1337 clock can be turned off. | |
51 | */ | |
7aa78614 | 52 | #if !defined(CONFIG_SC) |
8bde7f77 | 53 | #define CONFIG_8xx_GCLK_FREQ 66600000 |
7aa78614 WD |
54 | #else |
55 | #define CONFIG_8xx_GCLK_FREQ 48000000 | |
56 | #endif | |
5b1d7137 WD |
57 | |
58 | /* | |
59 | * The RS-232 console port is on SMC1 | |
60 | */ | |
61 | #define CONFIG_8xx_CONS_SMC1 | |
62 | #define CONFIG_BAUDRATE 38400 | |
63 | ||
64 | /* | |
65 | * Set allowable console baud rates | |
66 | */ | |
67 | #define CFG_BAUDRATE_TABLE { 9600, \ | |
68 | 19200, \ | |
69 | 38400, \ | |
70 | 57600, \ | |
71 | 115200, \ | |
72 | } | |
73 | ||
74 | /* | |
75 | * Print console information | |
76 | */ | |
77 | #undef CFG_CONSOLE_INFO_QUIET | |
78 | ||
79 | /* | |
80 | * Set the autoboot delay in seconds. A delay of -1 disables autoboot | |
81 | */ | |
82 | #define CONFIG_BOOTDELAY 5 | |
83 | ||
84 | /* | |
85 | * Pass the clock frequency to the Linux kernel in units of MHz | |
86 | */ | |
87 | #define CONFIG_CLOCKS_IN_MHZ | |
88 | ||
89 | #define CONFIG_PREBOOT \ | |
90 | "echo;echo" | |
91 | ||
92 | #undef CONFIG_BOOTARGS | |
93 | #define CONFIG_BOOTCOMMAND \ | |
94 | "bootp;" \ | |
fe126d8b WD |
95 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
96 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
5b1d7137 WD |
97 | "bootm" |
98 | ||
99 | /* | |
100 | * Turn off echo for serial download by default. Allow baud rate to be changed | |
101 | * for downloads | |
102 | */ | |
103 | #undef CONFIG_LOADS_ECHO | |
104 | #define CFG_LOADS_BAUD_CHANGE | |
105 | ||
106 | /* | |
107 | * Set default load address for tftp network downloads | |
108 | */ | |
109 | #define CFG_TFTP_LOADADDR 0x01000000 | |
110 | ||
111 | /* | |
112 | * Turn off the watchdog timer | |
113 | */ | |
114 | #undef CONFIG_WATCHDOG | |
115 | ||
116 | /* | |
117 | * Do not reboot if a panic occurs | |
118 | */ | |
119 | #define CONFIG_PANIC_HANG | |
120 | ||
121 | /* | |
122 | * Enable the status LED | |
123 | */ | |
124 | #define CONFIG_STATUS_LED | |
125 | ||
126 | /* | |
127 | * Reset address. We pick an address such that when an instruction | |
128 | * is executed at that address, a machine check exception occurs | |
129 | */ | |
130 | #define CFG_RESET_ADDRESS ((ulong) -1) | |
131 | ||
132 | /* | |
133 | * BOOTP options | |
134 | */ | |
135 | #define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ | |
136 | CONFIG_BOOTP_BOOTFILESIZE \ | |
137 | ) | |
138 | ||
139 | /* | |
140 | * The GEN860T network interface uses the on-chip 10/100 FEC with | |
141 | * an Intel LXT971A PHY connected to the 860T's MII. The PHY's | |
142 | * MII address is hardwired on the board to zero. | |
143 | */ | |
144 | #define CONFIG_FEC_ENET | |
145 | #define CFG_DISCOVER_PHY | |
146 | #define CONFIG_MII | |
147 | #define CONFIG_PHY_ADDR 0 | |
148 | ||
149 | /* | |
150 | * Set default IP stuff just to get bootstrap entries into the | |
151 | * environment so that we can autoscript the full default environment. | |
152 | */ | |
153 | #define CONFIG_ETHADDR 9a:52:63:15:85:25 | |
7aa78614 | 154 | #define CONFIG_SERVERIP 10.0.4.201 |
5b1d7137 WD |
155 | #define CONFIG_IPADDR 10.0.4.111 |
156 | ||
157 | /* | |
158 | * This board has a 32 kibibyte EEPROM (Atmel AT24C256) connected to | |
159 | * the MPC860T I2C interface. | |
160 | */ | |
161 | #define CFG_I2C_EEPROM_ADDR 0x50 | |
162 | #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ | |
163 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10 mS w/ 20% margin */ | |
164 | #define CFG_I2C_EEPROM_ADDR_LEN 2 /* need 16 bit address */ | |
165 | #define CFG_ENV_EEPROM_SIZE (32 * 1024) | |
166 | ||
5b1d7137 | 167 | /* |
7aa78614 | 168 | * Enable I2C and select the hardware/software driver |
5b1d7137 | 169 | */ |
7aa78614 WD |
170 | #define CONFIG_HARD_I2C 1 /* CPM based I2C */ |
171 | #undef CONFIG_SOFT_I2C /* Bit-banged I2C */ | |
172 | ||
173 | #ifdef CONFIG_HARD_I2C | |
174 | #define CFG_I2C_SPEED 100000 /* clock speed in Hz */ | |
175 | #define CFG_I2C_SLAVE 0xFE /* I2C slave address */ | |
176 | #endif | |
177 | ||
178 | #ifdef CONFIG_SOFT_I2C | |
5b1d7137 WD |
179 | #define PB_SCL 0x00000020 /* PB 26 */ |
180 | #define PB_SDA 0x00000010 /* PB 27 */ | |
5b1d7137 WD |
181 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) |
182 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
183 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
184 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
185 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
186 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
187 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
188 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
189 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
7aa78614 | 190 | #endif |
5b1d7137 WD |
191 | |
192 | /* | |
193 | * Allow environment overwrites by anyone | |
194 | */ | |
195 | #define CONFIG_ENV_OVERWRITE | |
196 | ||
7aa78614 | 197 | #if !defined(CONFIG_SC) |
5b1d7137 WD |
198 | /* |
199 | * The MPC860's internal RTC is horribly broken in rev D masks. Three | |
200 | * internal MPC860T circuit nodes were inadvertently left floating; this | |
201 | * causes KAPWR current in power down mode to be three orders of magnitude | |
202 | * higher than specified in the datasheet (from 10 uA to 10 mA). No | |
203 | * reasonable battery can keep that kind RTC running during powerdown for any | |
204 | * length of time, so we use an external RTC on the I2C bus instead. | |
205 | */ | |
5b1d7137 | 206 | #define CONFIG_RTC_DS1337 |
8bde7f77 | 207 | #define CFG_I2C_RTC_ADDR 0x68 |
5b1d7137 | 208 | |
7aa78614 | 209 | #else |
5b1d7137 | 210 | /* |
7aa78614 | 211 | * No external RTC on SC variant, so we're stuck with the internal one. |
5b1d7137 | 212 | */ |
7aa78614 WD |
213 | #define CONFIG_RTC_MPC8xx |
214 | #endif | |
215 | ||
216 | /* | |
217 | * Power On Self Test support | |
218 | */ | |
219 | #define CONFIG_POST ( CFG_POST_CACHE | \ | |
220 | CFG_POST_MEMORY | \ | |
221 | CFG_POST_CPU | \ | |
222 | CFG_POST_UART | \ | |
223 | CFG_POST_SPR ) | |
224 | ||
60a0876b | 225 | |
5b1d7137 | 226 | /* |
60a0876b JL |
227 | * Command line configuration. |
228 | */ | |
229 | #include <config_cmd_default.h> | |
230 | ||
231 | #define CONFIG_CMD_ASKENV | |
232 | #define CONFIG_CMD_DHCP | |
233 | #define CONFIG_CMD_I2C | |
234 | #define CONFIG_CMD_EEPROM | |
235 | #define CONFIG_CMD_REGINFO | |
236 | #define CONFIG_CMD_IMMAP | |
237 | #define CONFIG_CMD_ELF | |
238 | #define CONFIG_CMD_DATE | |
239 | #define CONFIG_CMD_FPGA | |
240 | #define CONFIG_CMD_MII | |
241 | #define CONFIG_CMD_BEDBUG | |
7aa78614 WD |
242 | |
243 | #if !defined(CONFIG_SC) | |
60a0876b | 244 | #define CONFIG_CMD_DOC |
7aa78614 | 245 | #endif |
5b1d7137 | 246 | |
af075ee9 JL |
247 | #ifdef CONFIG_POST |
248 | u #define CONFIG_CMD_DIAG | |
249 | #endif | |
60a0876b | 250 | |
5b1d7137 WD |
251 | /* |
252 | * There is no IDE/PCMCIA hardware support on the board. | |
253 | */ | |
254 | #undef CONFIG_IDE_PCMCIA | |
255 | #undef CONFIG_IDE_LED | |
256 | #undef CONFIG_IDE_RESET | |
257 | ||
258 | /* | |
259 | * Enable the call to misc_init_r() for miscellaneous platform | |
260 | * dependent initialization. | |
261 | */ | |
262 | #define CONFIG_MISC_INIT_R | |
263 | ||
264 | /* | |
265 | * Enable call to last_stage_init() so we can twiddle some LEDS :) | |
266 | */ | |
267 | #define CONFIG_LAST_STAGE_INIT | |
268 | ||
269 | /* | |
270 | * Virtex2 FPGA configuration support | |
271 | */ | |
272 | #define CONFIG_FPGA_COUNT 1 | |
273 | #define CONFIG_FPGA CFG_XILINX_VIRTEX2 | |
274 | #define CFG_FPGA_PROG_FEEDBACK | |
275 | ||
276 | ||
addb2e16 BS |
277 | #define CFG_NAND_LEGACY |
278 | ||
5b1d7137 WD |
279 | /* |
280 | * Verbose help from command monitor. | |
281 | */ | |
282 | #define CFG_LONGHELP | |
7aa78614 WD |
283 | #if !defined(CONFIG_SC) |
284 | #define CFG_PROMPT "B2> " | |
285 | #else | |
286 | #define CFG_PROMPT "SC> " | |
287 | #endif | |
288 | ||
5b1d7137 WD |
289 | |
290 | /* | |
291 | * Use the "hush" command parser | |
292 | */ | |
293 | #define CFG_HUSH_PARSER | |
294 | #define CFG_PROMPT_HUSH_PS2 "> " | |
295 | ||
296 | /* | |
297 | * Set buffer size for console I/O | |
298 | */ | |
60a0876b | 299 | #if defined(CONFIG_CMD_KGDB) |
5b1d7137 WD |
300 | #define CFG_CBSIZE 1024 |
301 | #else | |
302 | #define CFG_CBSIZE 256 | |
303 | #endif | |
304 | ||
305 | /* | |
306 | * Print buffer size | |
307 | */ | |
308 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) | |
309 | ||
310 | /* | |
311 | * Maximum number of arguments that a command can accept | |
312 | */ | |
313 | #define CFG_MAXARGS 16 | |
314 | ||
315 | /* | |
316 | * Boot argument buffer size | |
317 | */ | |
318 | #define CFG_BARGSIZE CFG_CBSIZE | |
319 | ||
320 | /* | |
321 | * Default memory test range | |
322 | */ | |
323 | #define CFG_MEMTEST_START 0x0100000 | |
324 | #define CFG_MEMTEST_END (CFG_MEMTEST_START + (128 * 1024)) | |
325 | ||
326 | /* | |
327 | * Select the more full-featured memory test | |
328 | */ | |
329 | #define CFG_ALT_MEMTEST | |
330 | ||
331 | /* | |
332 | * Default load address | |
333 | */ | |
334 | #define CFG_LOAD_ADDR 0x01000000 | |
335 | ||
336 | /* | |
337 | * Set decrementer frequency (1 ms ticks) | |
338 | */ | |
339 | #define CFG_HZ 1000 | |
340 | ||
341 | /* | |
342 | * Device memory map (after SDRAM remap to 0x0): | |
343 | * | |
344 | * CS Device Base Addr Size | |
345 | * ---------------------------------------------------- | |
346 | * CS0* Flash 0x40000000 64 M | |
347 | * CS1* SDRAM 0x00000000 16 M | |
348 | * CS2* Disk-On-Chip 0x50000000 32 K | |
349 | * CS3* FPGA 0x60000000 64 M | |
350 | * CS4* SelectMap 0x70000000 32 K | |
351 | * CS5* Mil-Std 1553 I/F 0x80000000 32 K | |
352 | * CS6* Unused | |
353 | * CS7* Unused | |
354 | * IMMR 860T Registers 0xfff00000 | |
355 | */ | |
356 | ||
357 | /* | |
358 | * Base addresses and block sizes | |
359 | */ | |
360 | #define CFG_IMMR 0xFF000000 | |
361 | ||
362 | #define SDRAM_BASE 0x00000000 | |
363 | #define SDRAM_SIZE (64 * 1024 * 1024) | |
364 | ||
365 | #define FLASH_BASE 0x40000000 | |
366 | #define FLASH_SIZE (16 * 1024 * 1024) | |
367 | ||
368 | #define DOC_BASE 0x50000000 | |
369 | #define DOC_SIZE (32 * 1024) | |
370 | ||
371 | #define FPGA_BASE 0x60000000 | |
372 | #define FPGA_SIZE (64 * 1024 * 1024) | |
373 | ||
374 | #define SELECTMAP_BASE 0x70000000 | |
375 | #define SELECTMAP_SIZE (32 * 1024) | |
376 | ||
377 | #define M1553_BASE 0x80000000 | |
378 | #define M1553_SIZE (64 * 1024) | |
379 | ||
380 | /* | |
381 | * Definitions for initial stack pointer and data area (in DPRAM) | |
382 | */ | |
383 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
384 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
385 | #define CFG_INIT_DATA_SIZE 64 /* # bytes reserved for initial data*/ | |
386 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE) | |
387 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
388 | ||
389 | /* | |
390 | * Start addresses for the final memory configuration | |
391 | * (Set up by the startup code) | |
392 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
393 | */ | |
394 | #define CFG_SDRAM_BASE SDRAM_BASE | |
395 | ||
396 | /* | |
397 | * FLASH organization | |
398 | */ | |
399 | #define CFG_FLASH_BASE FLASH_BASE | |
400 | #define CFG_FLASH_SIZE FLASH_SIZE | |
401 | #define CFG_FLASH_SECT_SIZE (128 * 1024) | |
402 | #define CFG_MAX_FLASH_BANKS 1 | |
403 | #define CFG_MAX_FLASH_SECT 128 | |
404 | ||
405 | /* | |
406 | * The timeout values are for an entire chip and are in milliseconds. | |
407 | * Yes I know that the write timeout is huge. Accroding to the | |
408 | * datasheet a single byte takes 630 uS (round to 1 ms) max at worst | |
409 | * case VCC and temp after 100K programming cycles. It works out | |
410 | * to 280 minutes (might as well be forever). | |
411 | */ | |
412 | #define CFG_FLASH_ERASE_TOUT (CFG_MAX_FLASH_SECT * 5000) | |
413 | #define CFG_FLASH_WRITE_TOUT (CFG_MAX_FLASH_SECT * 128 * 1024 * 1) | |
414 | ||
415 | /* | |
416 | * Allow direct writes to FLASH from tftp transfers (** dangerous **) | |
417 | */ | |
418 | #define CFG_DIRECT_FLASH_TFTP | |
419 | ||
420 | /* | |
421 | * Reserve memory for U-Boot. | |
422 | */ | |
7aa78614 WD |
423 | #define CFG_MAX_UBOOT_SECTS 4 |
424 | #define CFG_MONITOR_LEN (CFG_MAX_UBOOT_SECTS * CFG_FLASH_SECT_SIZE) | |
425 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
5b1d7137 WD |
426 | |
427 | /* | |
428 | * Select environment placement. NOTE that u-boot.lds must | |
429 | * be edited if this is changed! | |
430 | */ | |
431 | #undef CFG_ENV_IS_IN_FLASH | |
432 | #define CFG_ENV_IS_IN_EEPROM | |
433 | ||
434 | #if defined(CFG_ENV_IS_IN_EEPROM) | |
435 | #define CFG_ENV_SIZE (2 * 1024) | |
436 | #define CFG_ENV_OFFSET (CFG_ENV_EEPROM_SIZE - (8 * 1024)) | |
437 | #else | |
7aa78614 WD |
438 | #define CFG_ENV_SIZE 0x1000 |
439 | #define CFG_ENV_SECT_SIZE CFG_FLASH_SECT_SIZE | |
440 | ||
441 | /* | |
442 | * This ultimately gets passed right into the linker script, so we have to | |
443 | * use a number :( | |
444 | */ | |
445 | #define CFG_ENV_OFFSET 0x060000 | |
5b1d7137 WD |
446 | #endif |
447 | ||
448 | /* | |
449 | * Reserve memory for malloc() | |
450 | */ | |
451 | #define CFG_MALLOC_LEN (128 * 1024) | |
452 | ||
453 | /* | |
454 | * For booting Linux, the board info and command line data | |
455 | * have to be in the first 8 MB of memory, since this is | |
456 | * the maximum mapped by the Linux kernel during initialization. | |
457 | */ | |
458 | #define CFG_BOOTMAPSZ (8 * 1024 * 1024) | |
459 | ||
460 | /* | |
461 | * Cache Configuration | |
462 | */ | |
463 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
60a0876b | 464 | #if defined(CONFIG_CMD_KGDB) |
5b1d7137 WD |
465 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */ |
466 | #endif | |
467 | ||
468 | /*------------------------------------------------------------------------ | |
7aa78614 | 469 | * SYPCR - System Protection Control UM 11-9 |
5b1d7137 WD |
470 | * ----------------------------------------------------------------------- |
471 | * SYPCR can only be written once after reset! | |
472 | * | |
473 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
474 | */ | |
475 | #if defined(CONFIG_WATCHDOG) | |
476 | #define CFG_SYPCR ( SYPCR_SWTC | \ | |
477 | SYPCR_BMT | \ | |
478 | SYPCR_BME | \ | |
479 | SYPCR_SWF | \ | |
480 | SYPCR_SWE | \ | |
481 | SYPCR_SWRI | \ | |
482 | SYPCR_SWP \ | |
483 | ) | |
484 | #else | |
485 | #define CFG_SYPCR ( SYPCR_SWTC | \ | |
486 | SYPCR_BMT | \ | |
487 | SYPCR_BME | \ | |
488 | SYPCR_SWF | \ | |
489 | SYPCR_SWP \ | |
490 | ) | |
491 | #endif | |
492 | ||
493 | /*----------------------------------------------------------------------- | |
494 | * SIUMCR - SIU Module Configuration UM 11-6 | |
495 | *----------------------------------------------------------------------- | |
496 | * Set debug pin mux, enable SPKROUT and GPLB5*. | |
497 | */ | |
498 | #define CFG_SIUMCR ( SIUMCR_DBGC11 | \ | |
499 | SIUMCR_DBPC11 | \ | |
500 | SIUMCR_MLRC11 | \ | |
501 | SIUMCR_GB5E \ | |
502 | ) | |
503 | ||
504 | /*----------------------------------------------------------------------- | |
505 | * TBSCR - Time Base Status and Control UM 11-26 | |
506 | *----------------------------------------------------------------------- | |
507 | * Clear Reference Interrupt Status, Timebase freeze enabled | |
508 | */ | |
509 | #define CFG_TBSCR ( TBSCR_REFA | \ | |
510 | TBSCR_REFB | \ | |
511 | TBSCR_TBF \ | |
512 | ) | |
513 | ||
514 | /*----------------------------------------------------------------------- | |
515 | * RTCSC - Real-Time Clock Status and Control Register UM 11-27 | |
516 | *----------------------------------------------------------------------- | |
517 | */ | |
518 | #define CFG_RTCSC ( RTCSC_SEC | \ | |
519 | RTCSC_ALR | \ | |
520 | RTCSC_RTF | \ | |
521 | RTCSC_RTE \ | |
522 | ) | |
523 | ||
524 | /*----------------------------------------------------------------------- | |
525 | * PISCR - Periodic Interrupt Status and Control UM 11-31 | |
526 | *----------------------------------------------------------------------- | |
527 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
528 | */ | |
529 | #define CFG_PISCR ( PISCR_PS | \ | |
530 | PISCR_PITF \ | |
531 | ) | |
532 | ||
533 | /*----------------------------------------------------------------------- | |
534 | * PLPRCR - PLL, Low-Power, and Reset Control Register UM 15-30 | |
535 | *----------------------------------------------------------------------- | |
536 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
537 | * interrupt status bit. Set MF for 1:2:1 mode. | |
538 | */ | |
539 | #define CFG_PLPRCR ( ((0x1 << PLPRCR_MF_SHIFT) & PLPRCR_MF_MSK) | \ | |
540 | PLPRCR_SPLSS | \ | |
541 | PLPRCR_TEXPS | \ | |
542 | PLPRCR_TMIST \ | |
543 | ) | |
544 | ||
545 | /*----------------------------------------------------------------------- | |
546 | * SCCR - System Clock and reset Control Register UM 15-27 | |
547 | *----------------------------------------------------------------------- | |
548 | * Set clock output, timebase and RTC source and divider, | |
549 | * power management and some other internal clocks | |
550 | */ | |
551 | #define SCCR_MASK SCCR_EBDF11 | |
552 | ||
7aa78614 | 553 | #if !defined(CONFIG_SC) |
5b1d7137 WD |
554 | #define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ |
555 | SCCR_COM00 | /* full strength CLKOUT */ \ | |
556 | SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ | |
557 | SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ | |
558 | SCCR_DFNL000 | \ | |
559 | SCCR_DFNH000 \ | |
560 | ) | |
7aa78614 WD |
561 | #else |
562 | #define CFG_SCCR ( SCCR_TBS | /* timebase = GCLK/2 */ \ | |
563 | SCCR_COM00 | /* full strength CLKOUT */ \ | |
564 | SCCR_DFSYNC00 | /* SYNCLK / 1 (normal) */ \ | |
565 | SCCR_DFBRG00 | /* BRGCLK / 1 (normal) */ \ | |
566 | SCCR_DFNL000 | \ | |
567 | SCCR_DFNH000 | \ | |
568 | SCCR_RTDIV | \ | |
569 | SCCR_RTSEL \ | |
570 | ) | |
571 | #endif | |
5b1d7137 WD |
572 | |
573 | /*----------------------------------------------------------------------- | |
574 | * DER - Debug Enable Register UM 37-46 | |
575 | *----------------------------------------------------------------------- | |
576 | * Mask all events that can cause entry into debug mode | |
577 | */ | |
578 | #define CFG_DER 0 | |
579 | ||
580 | /* | |
581 | * Initialize Memory Controller: | |
582 | * | |
583 | * BR0 and OR0 (FLASH memory) | |
584 | */ | |
585 | #define FLASH_BASE0_PRELIM FLASH_BASE | |
586 | ||
587 | /* | |
588 | * Flash address mask | |
589 | */ | |
590 | #define CFG_PRELIM_OR_AM 0xfe000000 | |
591 | ||
592 | /* | |
593 | * FLASH timing: | |
594 | * 33 Mhz bus with ACS = 11, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 | |
595 | */ | |
596 | #define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | \ | |
597 | OR_ACS_DIV2 | \ | |
598 | OR_BI | \ | |
599 | OR_SCY_2_CLK | \ | |
600 | OR_TRLX | \ | |
601 | OR_EHTR \ | |
602 | ) | |
603 | ||
604 | #define CFG_OR0_PRELIM ( CFG_PRELIM_OR_AM | \ | |
605 | CFG_OR_TIMING_FLASH \ | |
606 | ) | |
607 | ||
608 | #define CFG_BR0_PRELIM ( (FLASH_BASE0_PRELIM & BR_BA_MSK) | \ | |
609 | BR_MS_GPCM | \ | |
610 | BR_PS_8 | \ | |
611 | BR_V \ | |
612 | ) | |
613 | ||
614 | /* | |
615 | * SDRAM configuration | |
616 | */ | |
617 | #define CFG_OR1_AM 0xfc000000 | |
618 | #define CFG_OR1 ( (CFG_OR1_AM & OR_AM_MSK) | \ | |
619 | OR_CSNT_SAM \ | |
620 | ) | |
621 | ||
622 | #define CFG_BR1 ( (SDRAM_BASE & BR_BA_MSK) | \ | |
623 | BR_MS_UPMA | \ | |
624 | BR_PS_32 | \ | |
625 | BR_V \ | |
626 | ) | |
627 | ||
628 | /* | |
629 | * Refresh rate 7.8 us (= 64 ms / 8K = 31.2 uS quad bursts) for one bank | |
630 | * of 256 MBit SDRAM | |
631 | */ | |
632 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 | |
633 | ||
634 | /* | |
635 | * Periodic timer for refresh @ 33 MHz system clock | |
636 | */ | |
637 | #define CFG_MAMR_PTA 64 | |
638 | ||
639 | /* | |
640 | * MAMR settings for SDRAM | |
641 | */ | |
642 | #define CFG_MAMR_8COL ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \ | |
643 | MAMR_PTAE | \ | |
644 | MAMR_AMA_TYPE_1 | \ | |
645 | MAMR_DSA_1_CYCL | \ | |
646 | MAMR_G0CLA_A10 | \ | |
647 | MAMR_RLFA_1X | \ | |
648 | MAMR_WLFA_1X | \ | |
649 | MAMR_TLFA_4X \ | |
650 | ) | |
651 | ||
652 | /* | |
653 | * CS2* configuration for Disk On Chip: | |
654 | * 33 MHz bus with TRLX=1, ACS=11, CSNT=1, EBDF=1, SCY=2, EHTR=1, | |
655 | * no burst. | |
656 | */ | |
657 | #define CFG_OR2_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ | |
658 | OR_CSNT_SAM | \ | |
659 | OR_ACS_DIV2 | \ | |
660 | OR_BI | \ | |
661 | OR_SCY_2_CLK | \ | |
662 | OR_TRLX | \ | |
663 | OR_EHTR \ | |
664 | ) | |
665 | ||
666 | #define CFG_BR2_PRELIM ( (DOC_BASE & BR_BA_MSK) | \ | |
667 | BR_PS_8 | \ | |
668 | BR_MS_GPCM | \ | |
669 | BR_V \ | |
670 | ) | |
671 | ||
672 | /* | |
673 | * CS3* configuration for FPGA: | |
674 | * 33 MHz bus with SCY=15, no burst. | |
675 | * The FPGA uses TA and TEA to terminate bus cycles, but we | |
676 | * clear SETA and set the cycle length to a large number so that | |
677 | * the cycle will still complete even if there is a configuration | |
678 | * error that prevents TA from asserting on FPGA accesss. | |
679 | */ | |
680 | #define CFG_OR3_PRELIM ( (0xfc000000 & OR_AM_MSK) | \ | |
681 | OR_SCY_15_CLK | \ | |
682 | OR_BI \ | |
683 | ) | |
684 | ||
685 | #define CFG_BR3_PRELIM ( (FPGA_BASE & BR_BA_MSK) | \ | |
686 | BR_PS_32 | \ | |
687 | BR_MS_GPCM | \ | |
688 | BR_V \ | |
689 | ) | |
690 | /* | |
691 | * CS4* configuration for FPGA SelectMap configuration interface. | |
692 | * 33 MHz bus, UPMB, no burst. Do not assert GPLB5 on falling edge | |
693 | * of GCLK1_50 | |
694 | */ | |
695 | #define CFG_OR4_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ | |
696 | OR_G5LS | \ | |
697 | OR_BI \ | |
698 | ) | |
699 | ||
700 | #define CFG_BR4_PRELIM ( (SELECTMAP_BASE & BR_BA_MSK) | \ | |
701 | BR_PS_8 | \ | |
702 | BR_MS_UPMB | \ | |
703 | BR_V \ | |
704 | ) | |
705 | ||
706 | /* | |
707 | * CS5* configuration for Mil-Std 1553 databus interface. | |
708 | * 33 MHz bus, GPCM, no burst. | |
709 | * The 1553 interface uses TA and TEA to terminate bus cycles, | |
710 | * but we clear SETA and set the cycle length to a large number so that | |
711 | * the cycle will still complete even if there is a configuration | |
712 | * error that prevents TA from asserting on FPGA accesss. | |
713 | */ | |
714 | #define CFG_OR5_PRELIM ( (0xffff0000 & OR_AM_MSK) | \ | |
715 | OR_SCY_15_CLK | \ | |
716 | OR_EHTR | \ | |
717 | OR_TRLX | \ | |
718 | OR_CSNT_SAM | \ | |
719 | OR_BI \ | |
720 | ) | |
721 | ||
722 | #define CFG_BR5_PRELIM ( (M1553_BASE & BR_BA_MSK) | \ | |
723 | BR_PS_16 | \ | |
724 | BR_MS_GPCM | \ | |
725 | BR_V \ | |
726 | ) | |
727 | ||
728 | /* | |
729 | * Boot Flags | |
730 | */ | |
731 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
732 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
733 | ||
734 | /* | |
735 | * Disk On Chip (millenium) configuration | |
736 | */ | |
7aa78614 | 737 | #if !defined(CONFIG_SC) |
5b1d7137 WD |
738 | #define CFG_MAX_DOC_DEVICE 1 |
739 | #undef CFG_DOC_SUPPORT_2000 | |
740 | #define CFG_DOC_SUPPORT_MILLENNIUM | |
741 | #undef CFG_DOC_PASSIVE_PROBE | |
7aa78614 | 742 | #endif |
5b1d7137 WD |
743 | |
744 | /* | |
745 | * FEC interrupt assignment | |
746 | */ | |
747 | #define FEC_INTERRUPT SIU_LEVEL1 | |
748 | ||
749 | /* | |
750 | * Sanity checks | |
751 | */ | |
752 | #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) | |
753 | #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured | |
754 | #endif | |
755 | ||
756 | #endif /* __CONFIG_GEN860T_H */ | |
757 | ||
758 | /* vim: set ts=4 tw=78 ai shiftwidth=4: */ |