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Commit | Line | Data |
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0f8c9768 WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
0f8c9768 WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ | |
21 | #define CONFIG_IVML24 1 /* ...on a IVML24 board */ | |
22 | ||
2ae18241 WD |
23 | #define CONFIG_SYS_TEXT_BASE 0xFF000000 |
24 | ||
0f8c9768 WD |
25 | #if defined (CONFIG_IVML24_16M) |
26 | # define CONFIG_IDENT_STRING " IVML24" | |
27 | #elif defined (CONFIG_IVML24_32M) | |
28 | # define CONFIG_IDENT_STRING " IVML24_128" | |
29 | #elif defined (CONFIG_IVML24_64M) | |
30 | # define CONFIG_IDENT_STRING " IVML24_256" | |
31 | #endif | |
32 | ||
33 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
34 | #undef CONFIG_8xx_CONS_SMC2 | |
35 | #undef CONFIG_8xx_CONS_NONE | |
36 | #define CONFIG_BAUDRATE 115200 | |
37 | ||
38 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
39 | #define CONFIG_8xx_GCLK_FREQ 50331648 | |
40 | ||
004eca0c PT |
41 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
42 | ||
0f8c9768 WD |
43 | #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ |
44 | ||
45 | #if 0 | |
46 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
47 | #else | |
48 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
49 | #endif | |
50 | #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ | |
51 | ||
52 | #define CONFIG_BOOTARGS "root=/dev/nfs rw " \ | |
53 | "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \ | |
54 | "nfsaddrs=10.0.0.99:10.0.0.2" | |
55 | ||
56 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 57 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
0f8c9768 WD |
58 | |
59 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
60 | ||
61 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
62 | ||
348f258f JL |
63 | |
64 | /* | |
65 | * Command line configuration. | |
66 | */ | |
67 | #include <config_cmd_default.h> | |
68 | ||
69 | #define CONFIG_CMD_IDE | |
70 | ||
71 | ||
0f8c9768 WD |
72 | #define CONFIG_MAC_PARTITION |
73 | #define CONFIG_DOS_PARTITION | |
74 | ||
7be044e4 JL |
75 | /* |
76 | * BOOTP options | |
77 | */ | |
78 | #define CONFIG_BOOTP_SUBNETMASK | |
79 | #define CONFIG_BOOTP_HOSTNAME | |
80 | #define CONFIG_BOOTP_BOOTPATH | |
81 | #define CONFIG_BOOTP_BOOTFILESIZE | |
82 | ||
0f8c9768 | 83 | |
0f8c9768 WD |
84 | /* |
85 | * Miscellaneous configurable options | |
86 | */ | |
6d0f6bcf JCPV |
87 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
88 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
348f258f | 89 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 90 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
0f8c9768 | 91 | #else |
6d0f6bcf | 92 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
0f8c9768 | 93 | #endif |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
95 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
96 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
0f8c9768 | 97 | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
99 | #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ | |
0f8c9768 | 100 | |
6d0f6bcf | 101 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */ |
0f8c9768 | 102 | |
6d0f6bcf | 103 | #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ |
0f8c9768 | 104 | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_PB_12V_ENABLE 0x00002000 /* PB 18 */ |
106 | #define CONFIG_SYS_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */ | |
107 | #define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */ | |
108 | #define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */ | |
109 | #define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */ | |
0f8c9768 | 110 | |
6d0f6bcf JCPV |
111 | #define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */ |
112 | #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */ | |
0f8c9768 | 113 | |
6d0f6bcf | 114 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
0f8c9768 | 115 | |
0f8c9768 WD |
116 | /* |
117 | * Low Level Configuration Settings | |
118 | * (address mappings, register initial values, etc.) | |
119 | * You should know what you are doing if you make changes here. | |
120 | */ | |
121 | /*----------------------------------------------------------------------- | |
122 | * Internal Memory Mapped Register | |
123 | */ | |
6d0f6bcf | 124 | #define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */ |
0f8c9768 WD |
125 | |
126 | /*----------------------------------------------------------------------- | |
127 | * Definitions for initial stack pointer and data area (in DPRAM) | |
128 | */ | |
6d0f6bcf | 129 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
0f8c9768 WD |
130 | |
131 | #if defined (CONFIG_IVML24_16M) | |
553f0982 | 132 | # define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
0f8c9768 | 133 | #elif defined (CONFIG_IVML24_32M) |
553f0982 | 134 | # define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
0f8c9768 | 135 | #elif defined (CONFIG_IVML24_64M) |
553f0982 | 136 | # define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
0f8c9768 WD |
137 | #endif |
138 | ||
25ddd1fb | 139 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 140 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
0f8c9768 WD |
141 | |
142 | /*----------------------------------------------------------------------- | |
143 | * Start addresses for the final memory configuration | |
144 | * (Set up by the startup code) | |
6d0f6bcf | 145 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
0f8c9768 | 146 | */ |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
148 | #define CONFIG_SYS_FLASH_BASE 0xFF000000 | |
0f8c9768 | 149 | #ifdef DEBUG |
6d0f6bcf | 150 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
0f8c9768 | 151 | #else |
6d0f6bcf | 152 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
0f8c9768 | 153 | #endif |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE |
155 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
0f8c9768 WD |
156 | |
157 | /* | |
158 | * For booting Linux, the board info and command line data | |
159 | * have to be in the first 8 MB of memory, since this is | |
160 | * the maximum mapped by the Linux kernel during initialization. | |
161 | */ | |
6d0f6bcf | 162 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
0f8c9768 WD |
163 | /*----------------------------------------------------------------------- |
164 | * FLASH organization | |
165 | */ | |
6d0f6bcf JCPV |
166 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
167 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
0f8c9768 | 168 | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
170 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
0f8c9768 | 171 | |
5a1aceb0 | 172 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
173 | #define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */ |
174 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
0f8c9768 WD |
175 | /*----------------------------------------------------------------------- |
176 | * Cache Configuration | |
177 | */ | |
6d0f6bcf | 178 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
348f258f | 179 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 180 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
0f8c9768 WD |
181 | #endif |
182 | ||
183 | /*----------------------------------------------------------------------- | |
184 | * SYPCR - System Protection Control 11-9 | |
185 | * SYPCR can only be written once after reset! | |
186 | *----------------------------------------------------------------------- | |
187 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
188 | */ | |
189 | #if defined(CONFIG_WATCHDOG) | |
190 | ||
191 | # if defined (CONFIG_IVML24_16M) | |
6d0f6bcf | 192 | # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
53677ef1 | 193 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
0f8c9768 | 194 | # elif defined (CONFIG_IVML24_32M) |
6d0f6bcf | 195 | # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
0f8c9768 WD |
196 | SYPCR_SWE | SYPCR_SWP) |
197 | # elif defined (CONFIG_IVML24_64M) | |
6d0f6bcf | 198 | # define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
0f8c9768 WD |
199 | SYPCR_SWE | SYPCR_SWP) |
200 | # endif | |
201 | ||
202 | #else | |
6d0f6bcf | 203 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
0f8c9768 WD |
204 | #endif |
205 | ||
206 | /*----------------------------------------------------------------------- | |
207 | * SIUMCR - SIU Module Configuration 11-6 | |
208 | *----------------------------------------------------------------------- | |
209 | * PCMCIA config., multi-function pin tri-state | |
210 | */ | |
211 | /* EARB, DBGC and DBPC are initialised by the HCW */ | |
212 | /* => 0x000000C0 */ | |
6d0f6bcf | 213 | #define CONFIG_SYS_SIUMCR (SIUMCR_BSC | SIUMCR_GB5E) |
0f8c9768 WD |
214 | |
215 | /*----------------------------------------------------------------------- | |
216 | * TBSCR - Time Base Status and Control 11-26 | |
217 | *----------------------------------------------------------------------- | |
218 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
219 | */ | |
6d0f6bcf | 220 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
0f8c9768 WD |
221 | |
222 | /*----------------------------------------------------------------------- | |
223 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
224 | *----------------------------------------------------------------------- | |
225 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
226 | */ | |
6d0f6bcf | 227 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
0f8c9768 WD |
228 | |
229 | /*----------------------------------------------------------------------- | |
230 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
231 | *----------------------------------------------------------------------- | |
232 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
233 | * interrupt status bit, set PLL multiplication factor ! | |
234 | */ | |
235 | /* 0x00B0C0C0 */ | |
6d0f6bcf | 236 | #define CONFIG_SYS_PLPRCR \ |
0f8c9768 WD |
237 | ( (11 << PLPRCR_MF_SHIFT) | \ |
238 | PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \ | |
239 | /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ | |
240 | PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ | |
241 | ) | |
242 | ||
243 | /*----------------------------------------------------------------------- | |
244 | * SCCR - System Clock and reset Control Register 15-27 | |
245 | *----------------------------------------------------------------------- | |
246 | * Set clock output, timebase and RTC source and divider, | |
247 | * power management and some other internal clocks | |
248 | */ | |
249 | #define SCCR_MASK SCCR_EBDF11 | |
250 | /* 0x01800014 */ | |
6d0f6bcf | 251 | #define CONFIG_SYS_SCCR (SCCR_COM01 | /*SCCR_TBS|*/ \ |
0f8c9768 | 252 | SCCR_RTDIV | SCCR_RTSEL | \ |
53677ef1 | 253 | /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ |
0f8c9768 WD |
254 | SCCR_EBDF00 | SCCR_DFSYNC00 | \ |
255 | SCCR_DFBRG00 | SCCR_DFNL000 | \ | |
256 | SCCR_DFNH000 | SCCR_DFLCD101 | \ | |
257 | SCCR_DFALCD00) | |
258 | ||
259 | /*----------------------------------------------------------------------- | |
260 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
261 | *----------------------------------------------------------------------- | |
262 | */ | |
263 | /* 0x00C3 */ | |
6d0f6bcf | 264 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
0f8c9768 WD |
265 | |
266 | ||
267 | /*----------------------------------------------------------------------- | |
268 | * RCCR - RISC Controller Configuration Register 19-4 | |
269 | *----------------------------------------------------------------------- | |
270 | */ | |
271 | /* TIMEP=2 */ | |
6d0f6bcf | 272 | #define CONFIG_SYS_RCCR 0x0200 |
0f8c9768 WD |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * RMDS - RISC Microcode Development Support Control Register | |
276 | *----------------------------------------------------------------------- | |
277 | */ | |
6d0f6bcf | 278 | #define CONFIG_SYS_RMDS 0 |
0f8c9768 WD |
279 | |
280 | /*----------------------------------------------------------------------- | |
281 | * | |
282 | * Interrupt Levels | |
283 | *----------------------------------------------------------------------- | |
284 | */ | |
6d0f6bcf | 285 | #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */ |
0f8c9768 WD |
286 | |
287 | /*----------------------------------------------------------------------- | |
288 | * PCMCIA stuff | |
289 | *----------------------------------------------------------------------- | |
290 | * | |
291 | */ | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
293 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
294 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
295 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
296 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
297 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
298 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
299 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
0f8c9768 WD |
300 | |
301 | /*----------------------------------------------------------------------- | |
302 | * IDE/ATA stuff | |
303 | *----------------------------------------------------------------------- | |
304 | */ | |
8d1165e1 PH |
305 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
306 | #define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ | |
0f8c9768 WD |
307 | #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */ |
308 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ | |
309 | ||
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/ |
311 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */ | |
0f8c9768 | 312 | |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000 |
314 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
315 | #undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */ | |
0f8c9768 | 316 | |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
318 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */ | |
319 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */ | |
0f8c9768 WD |
320 | |
321 | /*----------------------------------------------------------------------- | |
322 | * | |
323 | *----------------------------------------------------------------------- | |
324 | * | |
325 | */ | |
6d0f6bcf | 326 | #define CONFIG_SYS_DER 0 |
0f8c9768 WD |
327 | |
328 | /* | |
329 | * Init Memory Controller: | |
330 | * | |
331 | * BR0 and OR0 (FLASH) | |
332 | */ | |
333 | ||
334 | #define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */ | |
335 | ||
336 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
337 | * restrict access enough to keep SRAM working (if any) | |
338 | * but not too much to meddle with FLASH accesses | |
339 | */ | |
340 | /* EPROMs are 512kb */ | |
6d0f6bcf JCPV |
341 | #define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */ |
342 | #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */ | |
0f8c9768 WD |
343 | |
344 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
6d0f6bcf | 345 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_5_CLK | OR_EHTR) |
0f8c9768 | 346 | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \ |
348 | CONFIG_SYS_OR_TIMING_FLASH) | |
349 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \ | |
350 | CONFIG_SYS_OR_TIMING_FLASH) | |
0f8c9768 | 351 | /* 16 bit, bank valid */ |
6d0f6bcf | 352 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) |
0f8c9768 WD |
353 | |
354 | /* | |
355 | * BR1/OR1 - ELIC SACCO bank @ 0xFE000000 | |
356 | * | |
357 | * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 | |
358 | */ | |
359 | #define ELIC_SACCO_BASE 0xFE000000 | |
360 | #define ELIC_SACCO_OR_AM 0xFFFF8000 | |
361 | #define ELIC_SACCO_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) | |
362 | ||
6d0f6bcf | 363 | #define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
0f8c9768 | 364 | ELIC_SACCO_TIMING) |
6d0f6bcf | 365 | #define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
0f8c9768 WD |
366 | |
367 | /* | |
368 | * BR2/OR2 - ELIC EPIC bank @ 0xFE008000 | |
369 | * | |
370 | * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1 | |
371 | */ | |
372 | #define ELIC_EPIC_BASE 0xFE008000 | |
373 | #define ELIC_EPIC_OR_AM 0xFFFF8000 | |
374 | #define ELIC_EPIC_TIMING (OR_SCY_2_CLK | OR_TRLX | OR_EHTR) | |
375 | ||
6d0f6bcf | 376 | #define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ |
0f8c9768 | 377 | ELIC_EPIC_TIMING) |
6d0f6bcf | 378 | #define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) |
0f8c9768 WD |
379 | |
380 | /* | |
381 | * BR3/OR3: SDRAM | |
382 | * | |
383 | * Multiplexed addresses, GPL5 output to GPL5_A (don't care) | |
384 | */ | |
385 | #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ | |
386 | #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ | |
387 | #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ | |
388 | ||
389 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ | |
390 | ||
6d0f6bcf JCPV |
391 | #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING ) |
392 | #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V ) | |
0f8c9768 WD |
393 | |
394 | /* | |
395 | * BR4/OR4 - HDLC Address | |
396 | * | |
397 | * AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0 | |
398 | */ | |
399 | #define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */ | |
400 | #define HDLC_ADDR_OR_AM 0xFFFF8000 | |
401 | #define HDLC_ADDR_TIMING OR_SCY_1_CLK | |
402 | ||
6d0f6bcf JCPV |
403 | #define CONFIG_SYS_OR4 (HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING) |
404 | #define CONFIG_SYS_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V ) | |
0f8c9768 WD |
405 | |
406 | /* | |
407 | * BR5/OR5: SHARC ADSP-2165L | |
408 | * | |
409 | * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0 | |
410 | */ | |
411 | #define SHARC_BASE 0xFE400000 | |
412 | #define SHARC_OR_AM 0xFFC00000 | |
413 | #define SHARC_TIMING OR_SCY_0_CLK | |
414 | ||
6d0f6bcf JCPV |
415 | #define CONFIG_SYS_OR5 (SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING ) |
416 | #define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V ) | |
0f8c9768 WD |
417 | |
418 | /* | |
419 | * Memory Periodic Timer Prescaler | |
420 | */ | |
421 | ||
422 | /* periodic timer for refresh */ | |
6d0f6bcf | 423 | #define CONFIG_SYS_MBMR_PTB 204 |
0f8c9768 WD |
424 | |
425 | /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ | |
6d0f6bcf JCPV |
426 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
427 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
0f8c9768 WD |
428 | |
429 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf | 430 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
0f8c9768 WD |
431 | |
432 | #if defined (CONFIG_IVML24_16M) | |
6d0f6bcf | 433 | # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
0f8c9768 | 434 | #elif defined (CONFIG_IVML24_32M) |
6d0f6bcf | 435 | # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ |
0f8c9768 | 436 | #elif defined (CONFIG_IVML24_64M) |
6d0f6bcf | 437 | # define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */ |
0f8c9768 WD |
438 | #endif |
439 | ||
440 | ||
441 | /* | |
442 | * MBMR settings for SDRAM | |
443 | */ | |
444 | ||
445 | #if defined (CONFIG_IVML24_16M) | |
446 | /* 8 column SDRAM */ | |
6d0f6bcf | 447 | # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ |
53677ef1 WD |
448 | MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \ |
449 | MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) | |
0f8c9768 WD |
450 | #elif defined (CONFIG_IVML24_32M) |
451 | /* 128 MBit SDRAM */ | |
6d0f6bcf | 452 | # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ |
2535d602 WD |
453 | MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ |
454 | MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) | |
0f8c9768 WD |
455 | #elif defined (CONFIG_IVML24_64M) |
456 | /* 128 MBit SDRAM */ | |
6d0f6bcf | 457 | # define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ |
2535d602 WD |
458 | MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 | \ |
459 | MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X) | |
0f8c9768 | 460 | #endif |
0f8c9768 | 461 | #endif /* __CONFIG_H */ |