[people/ms/u-boot.git] / include / configs / IceCube.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_ICECUBE		1	/* ... on IceCube board */

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }


#ifdef CONFIG_MPC5200	/* MPC5100 PCI is not supported yet. */
/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI

#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000
#endif

#define CONFIG_SYS_XLB_PIPELINING	1

#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_EEPRO100		1
#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
#define CONFIG_NS8382X		1

#else
#define CONFIG_MII		1
#endif

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/* USB */
#define CONFIG_USB_OHCI_NEW
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_OHCI_BE_CONTROLLER
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
#define CONFIG_SYS_USB_OHCI_REGS_BASE	MPC5XXX_USB
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"mpc5200"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15

#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif


#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
#   define CONFIG_SYS_LOWBOOT	        1
#   define CONFIG_SYS_LOWBOOT16	1
#endif
#if (TEXT_BASE == 0xFF800000)		/* Boot low with  8 MB Flash */
#if defined(CONFIG_LITE5200B)
#   error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
#else
#   define CONFIG_SYS_LOWBOOT	        1
#   define CONFIG_SYS_LOWBOOT08	1
#endif
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	"bootfile=/tftpboot/MPC5200/uImage\0"				\
	""

#define CONFIG_BOOTCOMMAND	"run flash_self"

#if defined(CONFIG_MPC5200)
/*
 * IPB Bus clocking configuration.
 */
#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
#else
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
#endif
#endif /* CONFIG_MPC5200 */

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70

/*
 * Flash configuration
 */
#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_FLASH_BASE		0xFE000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
#else	/* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_SYS_LOWBOOT08)
# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
#endif
#if defined(CONFIG_SYS_LOWBOOT16)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x01060000)
#endif
#endif /* CONFIG_SYS_LOWBOOT */
#else /* !CONFIG_LITE5200B (IceCube)*/
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_SIZE		0x01000000
#if !defined(CONFIG_SYS_LOWBOOT)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
#else	/* CONFIG_SYS_LOWBOOT */
#if defined(CONFIG_SYS_LOWBOOT08)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
#endif
#if defined(CONFIG_SYS_LOWBOOT16)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
#endif
#endif	/* CONFIG_SYS_LOWBOOT */
#endif /* CONFIG_LITE5200B */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max num of memory banks      */

#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */

#if defined(CONFIG_LITE5200B)
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
#endif


/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#if defined(CONFIG_LITE5200B)
#define CONFIG_ENV_SECT_SIZE	0x20000
#else
#define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#define CONFIG_ENV_OVERWRITE	1

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

/* Use SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */


#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00
#if defined(CONFIG_LITE5200B)
#define CONFIG_FEC_MII100	1
#endif

/*
 * GPIO configuration
 */
#ifdef CONFIG_MPC5200_DDR
#define CONFIG_SYS_GPS_PORT_CONFIG	0x90000004
#else
#define CONFIG_SYS_GPS_PORT_CONFIG	0x10000004
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE
#else
#define CONFIG_SYS_HID0_INIT		0
#define CONFIG_SYS_HID0_FINAL		0
#endif

#if defined(CONFIG_LITE5200B)
#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_CS1_CFG		0x00047800
#define CONFIG_SYS_CS0_START		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_CS0_START
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047800
#else /* IceCube aka Lite5200 */
#ifdef CONFIG_MPC5200_DDR

#define CONFIG_SYS_BOOTCS_START	(CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
#define CONFIG_SYS_BOOTCS_SIZE		0x00800000
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS1_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS1_SIZE		0x00800000
#define CONFIG_SYS_CS1_CFG		0x00047800

#else /* !CONFIG_MPC5200_DDR */

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00047801
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

#endif /* CONFIG_MPC5200_DDR */
#endif /*CONFIG_LITE5200B */

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

#define CONFIG_SYS_RESET_ADDRESS	0xff000000

/*-----------------------------------------------------------------------
 * USB stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define	CONFIG_IDE_RESET		/* reset for ide supported	*/
#define CONFIG_IDE_PREINIT

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#define CONFIG_ATAPI            1

#endif /* __CONFIG_H */
Commit	Line	Data
945af8d7	1	/*
414eec35	2	* (C) Copyright 2003-2005
945af8d7 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
	27	/*
	28	* High Level Configuration Options
	29	* (easy to change)
	30	*/
	31
cbd8a35c	32	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
945af8d7 WD	33	#define CONFIG_ICECUBE 1 /* ... on IceCube board */
945af8d7 WD	34
6d0f6bcf	35	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
945af8d7 WD	36
	37	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	38	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	39
31d82672 BB	40	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	41
945af8d7 WD	42	/*
	43	* Serial console configuration
	44	*/
	45	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	46	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	47	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
945af8d7	48
96e48cf6 WD	49
	50	#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
	51	/*
	52	* PCI Mapping:
	53	* 0x40000000 - 0x4fffffff - PCI Memory
	54	* 0x50000000 - 0x50ffffff - PCI IO Space
	55	*/
b66a9383 RJ	56	#define CONFIG_PCI
	57
	58	#if defined(CONFIG_PCI)
96e48cf6 WD	59	#define CONFIG_PCI_PNP 1
96e48cf6 WD	60	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	61	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
96e48cf6 WD	62
	63	#define CONFIG_PCI_MEM_BUS 0x40000000
	64	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	65	#define CONFIG_PCI_MEM_SIZE 0x10000000
	66
	67	#define CONFIG_PCI_IO_BUS 0x50000000
	68	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	69	#define CONFIG_PCI_IO_SIZE 0x01000000
b66a9383	70	#endif
96e48cf6	71
6d0f6bcf	72	#define CONFIG_SYS_XLB_PIPELINING 1
e1599e83	73
96e48cf6	74	#define CONFIG_NET_MULTI 1
63ff004c	75	#define CONFIG_MII 1
96e48cf6	76	#define CONFIG_EEPRO100 1
6d0f6bcf	77	#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
f54ebdfa	78	#define CONFIG_NS8382X 1
96e48cf6	79
11799434	80	#else
63ff004c	81	#define CONFIG_MII 1
96e48cf6 WD	82	#endif
96e48cf6 WD	83
132ba5fd WD	84	/* Partitions */
	85	#define CONFIG_MAC_PARTITION
	86	#define CONFIG_DOS_PARTITION
64f70bed	87	#define CONFIG_ISO_PARTITION
132ba5fd	88
80885a9d	89	/* USB */
ae3b770e	90	#define CONFIG_USB_OHCI_NEW
80885a9d	91	#define CONFIG_USB_STORAGE
6d0f6bcf JCPV	92	#define CONFIG_SYS_OHCI_BE_CONTROLLER
	93	#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
	94	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	95	#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
	96	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
	97	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
ae3b770e	98
414eec35 WD	99	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
414eec35 WD	100
348f258f	101
945af8d7	102	/*
11799434	103	* BOOTP options
945af8d7	104	*/
11799434 JL	105	#define CONFIG_BOOTP_BOOTFILESIZE
	106	#define CONFIG_BOOTP_BOOTPATH
	107	#define CONFIG_BOOTP_GATEWAY
	108	#define CONFIG_BOOTP_HOSTNAME
	109
	110
945af8d7	111	/*
348f258f	112	* Command line configuration.
945af8d7	113	*/
348f258f JL	114	#include <config_cmd_default.h>
	115
	116	#define CONFIG_CMD_EEPROM
	117	#define CONFIG_CMD_FAT
	118	#define CONFIG_CMD_I2C
	119	#define CONFIG_CMD_IDE
	120	#define CONFIG_CMD_NFS
	121	#define CONFIG_CMD_SNTP
11799434 JL	122	#define CONFIG_CMD_USB
	123
	124	#if defined(CONFIG_PCI)
	125	#define CONFIG_CMD_PCI
	126	#endif
348f258f	127
945af8d7	128
5cf9da48	129	#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
6d0f6bcf JCPV	130	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	131	# define CONFIG_SYS_LOWBOOT16 1
5cf9da48 WD	132	#endif
5cf9da48 WD	133	#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
09e4b0c5	134	#if defined(CONFIG_LITE5200B)
6d0f6bcf	135	# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
09e4b0c5	136	#else
6d0f6bcf JCPV	137	# define CONFIG_SYS_LOWBOOT 1
6d0f6bcf JCPV	138	# define CONFIG_SYS_LOWBOOT08 1
5cf9da48	139	#endif
09e4b0c5	140	#endif
5cf9da48	141
945af8d7 WD	142	/*
	143	* Autobooting
	144	*/
	145	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
5cf9da48 WD	146
5cf9da48 WD	147	#define CONFIG_PREBOOT "echo;" \
32bf3d14	148	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
5cf9da48 WD	149	"echo"
	150
	151	#undef CONFIG_BOOTARGS
	152
	153	#define CONFIG_EXTRA_ENV_SETTINGS \
	154	"netdev=eth0\0" \
	155	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	156	"nfsroot=${serverip}:${rootpath}\0" \
5cf9da48	157	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	158	"addip=setenv bootargs ${bootargs} " \
	159	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	160	":${hostname}:${netdev}:off panic=1\0" \
5cf9da48	161	"flash_nfs=run nfsargs addip;" \
fe126d8b	162	"bootm ${kernel_addr}\0" \
5cf9da48	163	"flash_self=run ramargs addip;" \
fe126d8b WD	164	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	165	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
5cf9da48 WD	166	"rootpath=/opt/eldk/ppc_82xx\0" \
	167	"bootfile=/tftpboot/MPC5200/uImage\0" \
	168	""
	169
	170	#define CONFIG_BOOTCOMMAND "run flash_self"
945af8d7	171
acf98e7f WD	172	#if defined(CONFIG_MPC5200)
	173	/*
	174	* IPB Bus clocking configuration.
	175	*/
09e4b0c5	176	#if defined(CONFIG_LITE5200B)
6d0f6bcf	177	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
09e4b0c5	178	#else
6d0f6bcf	179	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
acf98e7f	180	#endif
09e4b0c5	181	#endif /* CONFIG_MPC5200 */
e59581c5 SR	182
e59581c5 SR	183	/* pass open firmware flat tree */
cf2817a8	184	#define CONFIG_OF_LIBFDT 1
e59581c5 SR	185	#define CONFIG_OF_BOARD_SETUP 1
e59581c5 SR	186
e59581c5 SR	187	#define OF_CPU "PowerPC,5200@0"
e59581c5 SR	188	#define OF_SOC "soc5200@f0000000"
39f23cd9	189	#define OF_TBCLK (bd->bi_busfreq / 4)
e59581c5 SR	190	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
e59581c5 SR	191
945af8d7 WD	192	/*
	193	* I2C configuration
	194	*/
531716e1	195	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	196	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
ab209d51	197
6d0f6bcf JCPV	198	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	199	#define CONFIG_SYS_I2C_SLAVE 0x7F
531716e1 WD	200
	201	/*
	202	* EEPROM configuration
	203	*/
6d0f6bcf JCPV	204	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	205	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	206	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	207	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
945af8d7 WD	208
	209	/*
	210	* Flash configuration
	211	*/
09e4b0c5	212	#if defined(CONFIG_LITE5200B)
6d0f6bcf JCPV	213	#define CONFIG_SYS_FLASH_BASE 0xFE000000
	214	#define CONFIG_SYS_FLASH_SIZE 0x01000000
	215	#if !defined(CONFIG_SYS_LOWBOOT)
	216	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
	217	#else /* CONFIG_SYS_LOWBOOT */
	218	#if defined(CONFIG_SYS_LOWBOOT08)
	219	# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
09e4b0c5	220	#endif
6d0f6bcf JCPV	221	#if defined(CONFIG_SYS_LOWBOOT16)
6d0f6bcf JCPV	222	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
09e4b0c5	223	#endif
6d0f6bcf	224	#endif /* CONFIG_SYS_LOWBOOT */
09e4b0c5	225	#else /* !CONFIG_LITE5200B (IceCube)*/
6d0f6bcf JCPV	226	#define CONFIG_SYS_FLASH_BASE 0xFF000000
	227	#define CONFIG_SYS_FLASH_SIZE 0x01000000
	228	#if !defined(CONFIG_SYS_LOWBOOT)
	229	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
	230	#else /* CONFIG_SYS_LOWBOOT */
	231	#if defined(CONFIG_SYS_LOWBOOT08)
	232	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
5cf9da48	233	#endif
6d0f6bcf JCPV	234	#if defined(CONFIG_SYS_LOWBOOT16)
6d0f6bcf JCPV	235	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
7152b1d0	236	#endif
6d0f6bcf	237	#endif /* CONFIG_SYS_LOWBOOT */
09e4b0c5	238	#endif /* CONFIG_LITE5200B */
6d0f6bcf	239	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
7152b1d0	240
6d0f6bcf	241	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
945af8d7	242
6d0f6bcf JCPV	243	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	244	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
945af8d7	245
96e48cf6	246	#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
945af8d7	247
09e4b0c5	248	#if defined(CONFIG_LITE5200B)
00b1883a	249	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	250	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	251	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
09e4b0c5 WD	252	#endif
09e4b0c5 WD	253
945af8d7 WD	254
	255	/*
	256	* Environment settings
	257	*/
5a1aceb0	258	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	259	#define CONFIG_ENV_SIZE 0x10000
09e4b0c5	260	#if defined(CONFIG_LITE5200B)
0e8d1586	261	#define CONFIG_ENV_SECT_SIZE 0x20000
09e4b0c5	262	#else
0e8d1586	263	#define CONFIG_ENV_SECT_SIZE 0x10000
09e4b0c5	264	#endif
96e48cf6	265	#define CONFIG_ENV_OVERWRITE 1
945af8d7 WD	266
	267	/*
	268	* Memory map
	269	*/
6d0f6bcf JCPV	270	#define CONFIG_SYS_MBAR 0xF0000000
	271	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	272	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
945af8d7 WD	273
945af8d7 WD	274	/* Use SRAM until RAM will be available */
6d0f6bcf JCPV	275	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
6d0f6bcf JCPV	276	#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
945af8d7 WD	277
945af8d7 WD	278
6d0f6bcf JCPV	279	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	280	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	281	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
945af8d7	282
6d0f6bcf JCPV	283	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
	284	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	285	# define CONFIG_SYS_RAMBOOT 1
945af8d7 WD	286	#endif
945af8d7 WD	287
6d0f6bcf JCPV	288	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	289	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	290	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
945af8d7 WD	291
	292	/*
	293	* Ethernet configuration
	294	*/
cbd8a35c	295	#define CONFIG_MPC5xxx_FEC 1
04a85b3b	296	/*
7e780369 WD	297	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	298	*/
	299	/* #define CONFIG_FEC_10MBIT 1 */
d4ca31c4	300	#define CONFIG_PHY_ADDR 0x00
09e4b0c5 WD	301	#if defined(CONFIG_LITE5200B)
	302	#define CONFIG_FEC_MII100 1
	303	#endif
945af8d7 WD	304
	305	/*
	306	* GPIO configuration
	307	*/
b2001f27	308	#ifdef CONFIG_MPC5200_DDR
6d0f6bcf	309	#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004
b2001f27	310	#else
6d0f6bcf	311	#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
b2001f27	312	#endif
945af8d7 WD	313
	314	/*
	315	* Miscellaneous configurable options
	316	*/
6d0f6bcf JCPV	317	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	318	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
348f258f	319	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	320	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
945af8d7	321	#else
6d0f6bcf	322	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
945af8d7	323	#endif
6d0f6bcf JCPV	324	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	325	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	326	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
945af8d7	327
6d0f6bcf JCPV	328	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	329	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
945af8d7	330
6d0f6bcf	331	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
945af8d7	332
6d0f6bcf	333	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
945af8d7	334
6d0f6bcf	335	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
348f258f	336	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	337	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
348f258f JL	338	#endif
348f258f JL	339
945af8d7 WD	340	/*
	341	* Various low-level settings
	342	*/
b13fb01a	343	#if defined(CONFIG_MPC5200)
6d0f6bcf JCPV	344	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	345	#define CONFIG_SYS_HID0_FINAL HID0_ICE
b13fb01a	346	#else
6d0f6bcf JCPV	347	#define CONFIG_SYS_HID0_INIT 0
6d0f6bcf JCPV	348	#define CONFIG_SYS_HID0_FINAL 0
b13fb01a	349	#endif
945af8d7	350
09e4b0c5	351	#if defined(CONFIG_LITE5200B)
6d0f6bcf JCPV	352	#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
	353	#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
	354	#define CONFIG_SYS_CS1_CFG 0x00047800
	355	#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
	356	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
	357	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
	358	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	359	#define CONFIG_SYS_BOOTCS_CFG 0x00047800
09e4b0c5	360	#else /* IceCube aka Lite5200 */
b2001f27 WD	361	#ifdef CONFIG_MPC5200_DDR
b2001f27 WD	362
6d0f6bcf JCPV	363	#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
	364	#define CONFIG_SYS_BOOTCS_SIZE 0x00800000
	365	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	366	#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
	367	#define CONFIG_SYS_CS1_SIZE 0x00800000
	368	#define CONFIG_SYS_CS1_CFG 0x00047800
b2001f27 WD	369
	370	#else /* !CONFIG_MPC5200_DDR */
	371
6d0f6bcf JCPV	372	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	373	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	374	#define CONFIG_SYS_BOOTCS_CFG 0x00047801
	375	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	376	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
945af8d7	377
b2001f27	378	#endif /* CONFIG_MPC5200_DDR */
09e4b0c5	379	#endif /CONFIG_LITE5200B /
b2001f27	380
6d0f6bcf JCPV	381	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	382	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
945af8d7	383
6d0f6bcf	384	#define CONFIG_SYS_RESET_ADDRESS 0xff000000
c3f9d493 WD	385
	386	/*-----------------------------------------------------------------------
	387	* USB stuff
	388	*-----------------------------------------------------------------------
	389	*/
4d13cbad WD	390	#define CONFIG_USB_CLOCK 0x0001BBBB
4d13cbad WD	391	#define CONFIG_USB_CONFIG 0x00001000
945af8d7	392
132ba5fd WD	393	/*-----------------------------------------------------------------------
	394	* IDE/ATA stuff Supports IDE harddisk
	395	*-----------------------------------------------------------------------
	396	*/
	397
	398	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	399
	400	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	401	#undef CONFIG_IDE_LED /* LED for ide not supported */
	402
	403	#define CONFIG_IDE_RESET /* reset for ide supported */
	404	#define CONFIG_IDE_PREINIT
	405
6d0f6bcf JCPV	406	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	407	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
132ba5fd	408
6d0f6bcf	409	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
132ba5fd	410
6d0f6bcf	411	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
132ba5fd WD	412
132ba5fd WD	413	/* Offset for data I/O */
6d0f6bcf	414	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
132ba5fd WD	415
132ba5fd WD	416	/* Offset for normal register accesses */
6d0f6bcf	417	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
132ba5fd WD	418
132ba5fd WD	419	/* Offset for alternate registers */
6d0f6bcf	420	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
132ba5fd WD	421
132ba5fd WD	422	/* Interval between registers */
6d0f6bcf	423	#define CONFIG_SYS_ATA_STRIDE 4
132ba5fd	424
64f70bed WD	425	#define CONFIG_ATAPI 1
64f70bed WD	426
945af8d7	427	#endif /* __CONFIG_H */