[people/ms/u-boot.git] / include / configs / KUP4X.h

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 * Derived from ../tqm8xx/tqm8xx.c
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC859T		1	/* This is a MPC859T CPU		*/
#define CONFIG_KUP4X		1	/* ...on a KUP4X module			*/

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1			*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate			*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled			*/
#else
#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second		*/
#endif

#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz	*/

#define CONFIG_BOARD_TYPES	1	/* support board types			*/

#define CFG_8XX_FACT		8	/* Multiply by 8			*/
#define CFG_8XX_XIN		16000000	/* 16 MHz in			*/


#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))

/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
/* in general, we always know this for FADS+new ADS anyway */
#define CONFIG_8xx_GCLK_FREQ	 MPC8XX_HZ


#undef	CONFIG_BOOTARGS


#define CONFIG_EXTRA_ENV_SETTINGS						\
"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
  "run addhw;diskboot 200000 0:1;bootm 200000\0"				\
"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
 "run addhw;diskboot 200000 2:1;bootm 200000\0"					\
"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0"				\
"panic_boot=echo No Bootdevice !!! reset\0"					\
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0"	\
"ramargs=setenv bootargs root=/dev/ram rw\0"					\
"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)"	\
 ":$(netmask):$(hostname):$(netdev):off\0"					\
"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0"		\
"netdev=eth0\0"									\
"silent=1\0"									\
"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0"		\
"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);"		\
 "cp.b 200000 40040000 14000\0"

#define CONFIG_BOOTCOMMAND  \
    "run slot_a_boot;run nfs_boot;run panic_boot"


#define CONFIG_MISC_INIT_R	1
#define CONFIG_MISC_INIT_F	1

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define CONFIG_HARD_I2C
#define CFG_I2C_SPEED 40000
#define CFG_I2C_SLAVE 0x7F

#define CONFIG_ETHADDR			00:0B:64:80:00:00 /* our OUI from IEEE */
#undef CONFIG_KUP4K_LOGO

/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_I2C	| \
				CFG_CMD_IDE	| \
				CFG_CMD_USB	| \
				CFG_CMD_FAT)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x000400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x003C00000	/* 4 ... 60 MB in DRAM	*/
#define CFG_LOAD_ADDR		0x200000	/* default load address */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }

#define CFG_CONSOLE_INFO_QUIET 1

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000
#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		0x30000 /*   Offset   of Environment Sector	*/
#define CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
#define CFG_ENV_SECT_SIZE	0x10000

/* Address and size of Redundant Environment Sector	*/
#if 0
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#if 0
#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CFG_HWINFO_SIZE		0x00000040	/* size	  of HW Info block */
#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
#endif
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)


/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)


/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * set the PLL, the low-power modes and the reset control (15-29)
 */
#define CFG_PLPRCR	((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) |	\
				PLPRCR_SPLSS | PLPRCR_TEXPS)


/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF00
#define CFG_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */

/* KUP4K use both slots, SLOT_A as "primary". */
#define CONFIG_PCMCIA_SLOT_A 1

#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )

#define PCMCIA_SOCKETS_NO 1
#define PCMCIA_MEM_WIN_NO 8
/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#define CONFIG_IDE_LED			1   /* LED   for ide supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1
#define CFG_IDE_MAXDEVICE	2

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_IDE1_OFFSET	(4 * CFG_PCMCIA_MEM_SIZE)

#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x0100


/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */
#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_2_CLK | OR_EHTR | OR_BI)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )


/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	0x00000A00


#define CFG_MPTPR 0x400

/*
 * MAMR settings for SDRAM
 */
#define CFG_MAMR 0x80802114


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/


#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot	*/
#if 0
#define CONFIG_AUTOBOOT_PROMPT		"Boote in %d Sekunden - stop mit \"2\"\n"
#endif
#define CONFIG_AUTOBOOT_STOP_STR	"."	/* easy to stop for now		*/
#define CONFIG_SILENT_CONSOLE	1

#define CONFIG_USB_STORAGE	1
#define CONFIG_USB_SL811HS	1

#endif	/* __CONFIG_H */
Commit	Line	Data
0608e04d WD	1	/*
	2	* (C) Copyright 2000-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* board/config.h - configuration options, board specific
	27	* Derived from ../tqm8xx/tqm8xx.c
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37
	38	#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */
	39	#define CONFIG_KUP4X 1 /* ...on a KUP4X module */
	40
	41	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	42	#undef CONFIG_8xx_CONS_SMC2
	43	#undef CONFIG_8xx_CONS_NONE
	44	#define CONFIG_BAUDRATE 115200 /* console baudrate */
	45	#if 0
	46	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	47	#else
	48	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
	49	#endif
	50
	51	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	52
	53	#define CONFIG_BOARD_TYPES 1 /* support board types */
	54
	55	#define CFG_8XX_FACT 8 /* Multiply by 8 */
	56	#define CFG_8XX_XIN 16000000 /* 16 MHz in */
	57
	58
	59	#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
	60
	61	/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
	62	/* in general, we always know this for FADS+new ADS anyway */
	63	#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
	64
65
66	#undef CONFIG_BOOTARGS
67
68
69	#define CONFIG_EXTRA_ENV_SETTINGS \
70	"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
71	"run addhw;diskboot 200000 0:1;bootm 200000\0" \
72	"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \
73	"run addhw;diskboot 200000 2:1;bootm 200000\0" \
74	"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
75	"panic_boot=echo No Bootdevice !!! reset\0" \
76	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
77	"ramargs=setenv bootargs root=/dev/ram rw\0" \
78	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \
79	":$(netmask):$(hostname):$(netdev):off\0" \
80	"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \
81	"netdev=eth0\0" \
82	"silent=1\0" \
83	"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
84	"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);" \
85	"cp.b 200000 40040000 14000\0"
86
87	#define CONFIG_BOOTCOMMAND \
88	"run slot_a_boot;run nfs_boot;run panic_boot"
89
90
91	#define CONFIG_MISC_INIT_R 1
92	#define CONFIG_MISC_INIT_F 1
93
94	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
95	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
96
97	#undef CONFIG_WATCHDOG /* watchdog disabled */
98
99	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
100
101	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
102
103	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE)
104
105	#define CONFIG_MAC_PARTITION
106	#define CONFIG_DOS_PARTITION
107
108	#define CONFIG_HARD_I2C
109	#define CFG_I2C_SPEED 40000
110	#define CFG_I2C_SLAVE 0x7F
111
112	#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
113	#undef CONFIG_KUP4K_LOGO
114
115	/* Define to allow the user to overwrite serial and ethaddr */
116	#define CONFIG_ENV_OVERWRITE
117
118	#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
119	CFG_CMD_DHCP \| \
120	CFG_CMD_I2C \| \
5cf91d6b WD	121	CFG_CMD_IDE \| \
	122	CFG_CMD_USB \| \
	123	CFG_CMD_FAT)
0608e04d WD	124
	125	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	126	#include <cmd_confdefs.h>
	127
	128	/*
	129	* Miscellaneous configurable options
	130	*/
	131	#define CFG_LONGHELP /* undef to save memory */
	132	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	133	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	134	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	135	#else
	136	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	137	#endif
	138	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	139	#define CFG_MAXARGS 16 /* max number of command args */
	140	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	141
	142	#define CFG_MEMTEST_START 0x000400000 /* memtest works on */
	143	#define CFG_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */
	144	#define CFG_LOAD_ADDR 0x200000 /* default load address */
	145
	146	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	147
	148	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
	149
	150	#define CFG_CONSOLE_INFO_QUIET 1
	151
	152	/*
	153	* Low Level Configuration Settings
	154	* (address mappings, register initial values, etc.)
	155	* You should know what you are doing if you make changes here.
	156	*/
	157	/*-----------------------------------------------------------------------
	158	* Internal Memory Mapped Register
	159	*/
	160	#define CFG_IMMR 0xFFF00000
	161
	162	/*-----------------------------------------------------------------------
	163	* Definitions for initial stack pointer and data area (in DPRAM)
	164	*/
	165	#define CFG_INIT_RAM_ADDR CFG_IMMR
	166	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	167	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	168	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	169	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	170
	171	/*-----------------------------------------------------------------------
	172	* Start addresses for the final memory configuration
	173	* (Set up by the startup code)
	174	* Please note that CFG_SDRAM_BASE _must_ start at 0
	175	*/
	176	#define CFG_SDRAM_BASE 0x00000000
	177	#define CFG_FLASH_BASE 0x40000000
	178	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */
	179	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	180	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	181
	182	/*
	183	* For booting Linux, the board info and command line data
	184	* have to be in the first 8 MB of memory, since this is
	185	* the maximum mapped by the Linux kernel during initialization.
	186	*/
	187	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
188
189	/*-----------------------------------------------------------------------
190	* FLASH organization
191	*/
192	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
193	#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
194
195	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
196	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
197
198	#define CFG_ENV_IS_IN_FLASH 1
199	#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
200	#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
201	#define CFG_ENV_SECT_SIZE 0x10000
202
203	/* Address and size of Redundant Environment Sector */
204	#if 0
205	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
206	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
207	#endif
208	/*-----------------------------------------------------------------------
209	* Hardware Information Block
210	*/
211	#if 0
212	#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
213	#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
214	#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
215	#endif
216	/*-----------------------------------------------------------------------
217	* Cache Configuration
218	*/
219	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
220	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
221	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
222	#endif
223
224	/*-----------------------------------------------------------------------
225	* SYPCR - System Protection Control 11-9
226	* SYPCR can only be written once after reset!
227	*-----------------------------------------------------------------------
228	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
229	*/
230	#if defined(CONFIG_WATCHDOG)
231	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
232	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
233	#else
234	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
235	#endif
236
237	/*-----------------------------------------------------------------------
238	* SIUMCR - SIU Module Configuration 11-6
239	*-----------------------------------------------------------------------
240	* PCMCIA config., multi-function pin tri-state
241	*/
242	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC00)
243
244	/*-----------------------------------------------------------------------
245	* TBSCR - Time Base Status and Control 11-26
246	*-----------------------------------------------------------------------
247	* Clear Reference Interrupt Status, Timebase freezing enabled
248	*/
249	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
250
251
252	/*-----------------------------------------------------------------------
253	* PISCR - Periodic Interrupt Status and Control 11-31
254	*-----------------------------------------------------------------------
255	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
256	*/
257	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
258
259
260	/*-----------------------------------------------------------------------
261	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
262	*-----------------------------------------------------------------------
263	* set the PLL, the low-power modes and the reset control (15-29)
264	*/
265	#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) \| \
266	PLPRCR_SPLSS \| PLPRCR_TEXPS)
267
268
269	/*-----------------------------------------------------------------------
270	* SCCR - System Clock and reset Control Register 15-27
271	*-----------------------------------------------------------------------
272	* Set clock output, timebase and RTC source and divider,
273	* power management and some other internal clocks
274	*/
275	#define SCCR_MASK SCCR_EBDF00
276	#define CFG_SCCR (SCCR_TBS \| SCCR_EBDF01 \| \
277	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
278	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
279	SCCR_DFALCD00)
280
281	/*-----------------------------------------------------------------------
282	* PCMCIA stuff
283	*-----------------------------------------------------------------------
284	*
285	*/
286
287	/* KUP4K use both slots, SLOT_A as "primary". */
288	#define CONFIG_PCMCIA_SLOT_A 1
289
290	#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
291	#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
292	#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
293	#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
294	#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
295	#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
296	#define CFG_PCMCIA_IO_ADDR (0xEC000000)
297	#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
298
299	#define PCMCIA_SOCKETS_NO 1
300	#define PCMCIA_MEM_WIN_NO 8
301	/*-----------------------------------------------------------------------
302	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
303	*-----------------------------------------------------------------------
304	*/
305
306	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
307
308	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
309	#define CONFIG_IDE_LED 1 /* LED for ide supported */
310	#undef CONFIG_IDE_RESET /* reset for ide not supported */
311
312	#define CFG_IDE_MAXBUS 1
313	#define CFG_IDE_MAXDEVICE 2
314
315	#define CFG_ATA_IDE0_OFFSET 0x0000
316
317	#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE)
318
319	#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
320
321	/* Offset for data I/O */
322	#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
323
324	/* Offset for normal register accesses */
325	#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
326
327	/* Offset for alternate registers */
328	#define CFG_ATA_ALT_OFFSET 0x0100
329
330
331	/*-----------------------------------------------------------------------
332	*
333	*-----------------------------------------------------------------------
334	*
335	*/
336	#define CFG_DER 0
337
338	/*
339	* Init Memory Controller:
340	*
341	* BR0/1 and OR0/1 (FLASH)
342	*/
343	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
344
345	/* used to re-map FLASH both when starting from SRAM or FLASH:
346	* restrict access enough to keep SRAM working (if any)
347	* but not too much to meddle with FLASH accesses
348	*/
349	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
350	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
351
352	/*
353	* FLASH timing:
354	*/
355	#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
356	OR_SCY_2_CLK \| OR_EHTR \| OR_BI)
357
358	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
359	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
360	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
361
362
363	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
364	#define CFG_OR_TIMING_SDRAM 0x00000A00
365
366
367	#define CFG_MPTPR 0x400
368
369	/*
370	* MAMR settings for SDRAM
371	*/
372	#define CFG_MAMR 0x80802114
373
374
375	/*
376	* Internal Definitions
377	*
378	* Boot Flags
379	*/
380	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
381	#define BOOTFLAG_WARM 0x02 /* Software reboot */
382
383
384	#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
385	#if 0
386	#define CONFIG_AUTOBOOT_PROMPT "Boote in %d Sekunden - stop mit \"2\"\n"
387	#endif
388	#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
389	#define CONFIG_SILENT_CONSOLE 1
390
5cf91d6b WD	391	#define CONFIG_USB_STORAGE 1
	392	#define CONFIG_USB_SL811HS 1
	393
0608e04d	394	#endif /* __CONFIG_H */