[people/ms/u-boot.git] / include / configs / M52277EVB.h

/*
 * Configuation settings for the Freescale MCF52277 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M52277EVB_H
#define _M52277EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF5227x		/* define processor family */
#define CONFIG_M52277		/* define processor type */
#define CONFIG_M52277EVB	/* M52277EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_BMP
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF

#define CONFIG_HOSTNAME			M52277EVB
#define CONFIG_SYS_UBOOT_END		0x3FFFF
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate};"	\
	"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE)	\
	" " MK_STR(CONFIG_SYS_UBOOT_END) ";"		\
	"era " MK_STR(CONFIG_SYS_FLASH_BASE) " "	\
	MK_STR(CONFIG_SYS_UBOOT_END) ";"		\
	"cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	"updsbf=run loadsbf; run progsbf\0"	\
	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
	"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"progsbf=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	""
#endif

#define CONFIG_BOOTDELAY		3	/* autoboot after 3 seconds */
/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_LCD_LOGO
#define CONFIG_SHARP_LQ035Q7DH06
#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_SYS_USB_EHCI_REGS_BASE	0xFC0B0000
#define CONFIG_SYS_USB_EHCI_CPU_INIT
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address  */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SER_FLASH_BASE	0x01000000
#define CONFIG_SYS_SBFHDR_SIZE		0x7
#ifdef CONFIG_CMD_SPI
#	define CONFIG_SYS_DSPI_CS2
#	define CONFIG_SPI_FLASH
#	define CONFIG_SPI_FLASH_STMICRO

#	define CONFIG_SYS_DSPI_DCTAR0	(DSPI_DCTAR_TRSZ(7) | \
					 DSPI_DCTAR_CPOL | \
					 DSPI_DCTAR_CPHA | \
					 DSPI_DCTAR_PCSSCK_1CLK | \
					 DSPI_DCTAR_PASC(0) | \
					 DSPI_DCTAR_PDT(0) | \
					 DSPI_DCTAR_CSSCK(0) | \
					 DSPI_DCTAR_ASC(0) | \
					 DSPI_DCTAR_PBR(0) | \
					 DSPI_DCTAR_DT(1) | \
					 DSPI_DCTAR_BR(1))
#endif

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_SYS_INPUT_CLKSRC	16000000

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_PROMPT	"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_HZ		1000

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_END		0x8000	/* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x81810000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*
 * Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_IS_IN_SPI_FLASH
#	define CONFIG_ENV_SPI_CS	2
#else
#	define CONFIG_ENV_IS_IN_FLASH	1
#endif
#define CONFIG_ENV_OVERWRITE		1
#undef CONFIG_ENV_IS_EMBEDDED

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_SER_FLASH_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_SER_FLASH_BASE
#	define CONFIG_SYS_FLASH1_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_OFFSET	0x30000
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x8000)
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x8000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x40000)
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

#ifdef CONFIG_CF_SBF
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#else
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#endif

#endif				/* _M52277EVB_H */
Commit	Line	Data
1552af70 TL	1	/*
	2	* Configuation settings for the Freescale MCF52277 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
	30	#ifndef _M52277EVB_H
	31	#define _M52277EVB_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_MCF5227x /* define processor family */
	38	#define CONFIG_M52277 /* define processor type */
	39	#define CONFIG_M52277EVB /* M52277EVB board */
	40
1552af70	41	#define CONFIG_MCFUART
6d0f6bcf	42	#define CONFIG_SYS_UART_PORT (0)
a21d0c2c	43	#define CONFIG_BAUDRATE 115200
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
1552af70 TL	45
	46	#undef CONFIG_WATCHDOG
	47
	48	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	49
	50	/*
	51	* BOOTP options
	52	*/
	53	#define CONFIG_BOOTP_BOOTFILESIZE
	54	#define CONFIG_BOOTP_BOOTPATH
	55	#define CONFIG_BOOTP_GATEWAY
	56	#define CONFIG_BOOTP_HOSTNAME
	57
	58	/* Command line configuration */
	59	#include <config_cmd_default.h>
	60
	61	#define CONFIG_CMD_CACHE
	62	#define CONFIG_CMD_DATE
	63	#define CONFIG_CMD_ELF
	64	#define CONFIG_CMD_FLASH
	65	#define CONFIG_CMD_I2C
	66	#define CONFIG_CMD_JFFS2
	67	#define CONFIG_CMD_LOADB
	68	#define CONFIG_CMD_LOADS
	69	#define CONFIG_CMD_MEMORY
	70	#define CONFIG_CMD_MISC
	71	#undef CONFIG_CMD_NET
	72	#define CONFIG_CMD_REGINFO
	73	#undef CONFIG_CMD_USB
	74	#undef CONFIG_CMD_BMP
a21d0c2c TL	75	#define CONFIG_CMD_SPI
	76	#define CONFIG_CMD_SF
	77
	78	#define CONFIG_HOSTNAME M52277EVB
	79	#define CONFIG_SYS_UBOOT_END 0x3FFFF
	80	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
	81	#ifdef CONFIG_SYS_STMICRO_BOOT
	82	/* ST Micro serial flash */
1552af70	83	#define CONFIG_EXTRA_ENV_SETTINGS \
6d0f6bcf	84	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	85	"loadaddr=0x40010000\0" \
	86	"uboot=u-boot.bin\0" \
	87	"load=loadb ${loadaddr} ${baudrate};" \
	88	"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
1552af70	89	"upd=run load; run prog\0" \
a21d0c2c TL	90	"prog=sf probe 0:2 10000 1;" \
	91	"sf erase 0 30000;" \
	92	"sf write ${loadaddr} 0 30000;" \
1552af70 TL	93	"save\0" \
1552af70 TL	94	""
a21d0c2c TL	95	#endif
	96	#ifdef CONFIG_SYS_SPANSION_BOOT
	97	#define CONFIG_EXTRA_ENV_SETTINGS \
	98	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
	99	"loadaddr=0x40010000\0" \
	100	"uboot=u-boot.bin\0" \
	101	"load=loadb ${loadaddr} ${baudrate}\0" \
	102	"upd=run load; run prog\0" \
	103	"prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \
	104	" " MK_STR(CONFIG_SYS_UBOOT_END) ";" \
	105	"era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \
	106	MK_STR(CONFIG_SYS_UBOOT_END) ";" \
	107	"cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \
	108	" ${filesize}; save\0" \
	109	"updsbf=run loadsbf; run progsbf\0" \
	110	"loadsbf=loadb ${loadaddr} ${baudrate};" \
	111	"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
	112	"progsbf=sf probe 0:2 10000 1;" \
	113	"sf erase 0 30000;" \
	114	"sf write ${loadaddr} 0 30000;" \
	115	""
	116	#endif
1552af70	117
a21d0c2c	118	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
1552af70 TL	119	/* LCD */
	120	#ifdef CONFIG_CMD_BMP
	121	#define CONFIG_LCD
	122	#define CONFIG_SPLASH_SCREEN
	123	#define CONFIG_LCD_LOGO
	124	#define CONFIG_SHARP_LQ035Q7DH06
	125	#endif
	126
	127	/* USB */
	128	#ifdef CONFIG_CMD_USB
	129	#define CONFIG_USB_EHCI
	130	#define CONFIG_USB_STORAGE
	131	#define CONFIG_DOS_PARTITION
	132	#define CONFIG_MAC_PARTITION
	133	#define CONFIG_ISO_PARTITION
a21d0c2c	134	#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
6d0f6bcf	135	#define CONFIG_SYS_USB_EHCI_CPU_INIT
1552af70 TL	136	#endif
	137
	138	/* Realtime clock */
	139	#define CONFIG_MCFRTC
	140	#undef RTC_DEBUG
6d0f6bcf	141	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
1552af70 TL	142
	143	/* Timer */
	144	#define CONFIG_MCFTMR
	145	#undef CONFIG_MCFPIT
	146
	147	/* I2c */
	148	#define CONFIG_FSL_I2C
	149	#define CONFIG_HARD_I2C /* I2C with hardware support */
	150	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	151	#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
	152	#define CONFIG_SYS_I2C_SLAVE 0x7F
	153	#define CONFIG_SYS_I2C_OFFSET 0x58000
a21d0c2c TL	154	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	155
	156	/* DSPI and Serial Flash */
	157	#define CONFIG_CF_DSPI
	158	#define CONFIG_HARD_SPI
	159	#define CONFIG_SYS_SER_FLASH_BASE 0x01000000
	160	#define CONFIG_SYS_SBFHDR_SIZE 0x7
	161	#ifdef CONFIG_CMD_SPI
	162	# define CONFIG_SYS_DSPI_CS2
	163	# define CONFIG_SPI_FLASH
	164	# define CONFIG_SPI_FLASH_STMICRO
	165
	166	# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) \| \
	167	DSPI_DCTAR_CPOL \| \
	168	DSPI_DCTAR_CPHA \| \
	169	DSPI_DCTAR_PCSSCK_1CLK \| \
	170	DSPI_DCTAR_PASC(0) \| \
	171	DSPI_DCTAR_PDT(0) \| \
	172	DSPI_DCTAR_CSSCK(0) \| \
	173	DSPI_DCTAR_ASC(0) \| \
	174	DSPI_DCTAR_PBR(0) \| \
	175	DSPI_DCTAR_DT(1) \| \
	176	DSPI_DCTAR_BR(1))
	177	#endif
1552af70 TL	178
	179	/* Input, PCI, Flexbus, and VCO */
	180	#define CONFIG_EXTRA_CLOCK
	181
6d0f6bcf	182	#define CONFIG_SYS_INPUT_CLKSRC 16000000
1552af70	183
a21d0c2c	184	#define CONFIG_PRAM 2048 /* 2048 KB */
1552af70	185
a21d0c2c	186	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf	187	#define CONFIG_SYS_LONGHELP /* undef to save memory */
1552af70 TL	188
1552af70 TL	189	#if defined(CONFIG_CMD_KGDB)
a21d0c2c	190	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
1552af70	191	#else
a21d0c2c	192	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1552af70	193	#endif
a21d0c2c TL	194	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	195	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	196	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
1552af70	197
a21d0c2c	198	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
1552af70	199
a21d0c2c	200	#define CONFIG_SYS_HZ 1000
1552af70	201
6d0f6bcf	202	#define CONFIG_SYS_MBAR 0xFC000000
1552af70 TL	203
	204	/*
	205	* Low Level Configuration Settings
	206	* (address mappings, register initial values, etc.)
	207	* You should know what you are doing if you make changes here.
	208	*/
	209
a21d0c2c	210	/*
1552af70 TL	211	* Definitions for initial stack pointer and data area (in DPRAM)
1552af70 TL	212	*/
6d0f6bcf	213	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
a21d0c2c TL	214	#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
a21d0c2c TL	215	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
6d0f6bcf	216	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
a21d0c2c TL	217	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
	218	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
	219	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
1552af70	220
a21d0c2c	221	/*
1552af70 TL	222	* Start addresses for the final memory configuration
1552af70 TL	223	* (Set up by the startup code)
6d0f6bcf	224	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
1552af70	225	*/
6d0f6bcf JCPV	226	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	227	#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
	228	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	229	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	230	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
	231	#define CONFIG_SYS_SDRAM_EMOD 0x81810000
	232	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
a21d0c2c	233	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
6d0f6bcf JCPV	234
	235	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	236	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	237
a21d0c2c TL	238	#ifdef CONFIG_CF_SBF
	239	# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
	240	#else
	241	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	242	#endif
6d0f6bcf JCPV	243	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	244	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	245	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
1552af70 TL	246
1552af70 TL	247	/* Initial Memory map for Linux */
6d0f6bcf	248	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	249	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
1552af70	250
a21d0c2c TL	251	/*
a21d0c2c TL	252	* Configuration for environment
1552af70 TL	253	* Environment is embedded in u-boot in the second sector of the flash
1552af70 TL	254	*/
a21d0c2c TL	255	#ifdef CONFIG_CF_SBF
	256	# define CONFIG_ENV_IS_IN_SPI_FLASH
	257	# define CONFIG_ENV_SPI_CS 2
	258	#else
	259	# define CONFIG_ENV_IS_IN_FLASH 1
	260	#endif
	261	#define CONFIG_ENV_OVERWRITE 1
0e8d1586	262	#undef CONFIG_ENV_IS_EMBEDDED
1552af70 TL	263
	264	/*-----------------------------------------------------------------------
	265	* FLASH organization
	266	*/
a21d0c2c TL	267	#ifdef CONFIG_SYS_STMICRO_BOOT
	268	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE
	269	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE
	270	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE
	271	# define CONFIG_ENV_OFFSET 0x30000
	272	# define CONFIG_ENV_SIZE 0x1000
	273	# define CONFIG_ENV_SECT_SIZE 0x10000
	274	#endif
	275	#ifdef CONFIG_SYS_SPANSION_BOOT
	276	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	277	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	278	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
	279	# define CONFIG_ENV_SIZE 0x1000
	280	# define CONFIG_ENV_SECT_SIZE 0x8000
	281	#endif
1552af70	282
6d0f6bcf JCPV	283	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	284	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	285	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	286	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	287	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	288	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	289	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	290	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	291	# define CONFIG_SYS_FLASH_CHECKSUM
a21d0c2c	292	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
1552af70 TL	293	#endif
	294
	295	/*
	296	* This is setting for JFFS2 support in u-boot.
	297	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	298	*/
	299	#ifdef CONFIG_CMD_JFFS2
	300	# define CONFIG_JFFS2_DEV "nor0"
	301	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
6d0f6bcf	302	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
1552af70 TL	303	#endif
	304
	305	/*-----------------------------------------------------------------------
	306	* Cache Configuration
	307	*/
a21d0c2c	308	#define CONFIG_SYS_CACHELINE_SIZE 16
1552af70 TL	309
	310	/*-----------------------------------------------------------------------
	311	* Memory bank definitions
	312	*/
	313	/*
	314	* CS0 - NOR Flash
	315	* CS1 - Available
	316	* CS2 - Available
	317	* CS3 - Available
	318	* CS4 - Available
	319	* CS5 - Available
	320	*/
	321
a21d0c2c TL	322	#ifdef CONFIG_CF_SBF
	323	#define CONFIG_SYS_CS0_BASE 0x04000000
	324	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	325	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	326	#else
6d0f6bcf JCPV	327	#define CONFIG_SYS_CS0_BASE 0x00000000
	328	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	329	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
a21d0c2c	330	#endif
1552af70 TL	331
1552af70 TL	332	#endif /* _M52277EVB_H */