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a605aacd TL |
1 | /* |
2 | * Configuation settings for the esd TASREG board. | |
3 | * | |
4 | * (C) Copyright 2004 | |
5 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
a605aacd TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M5249EVB_H | |
15 | #define _M5249EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
a605aacd TL |
21 | #define CONFIG_MCFTMR |
22 | ||
23 | #define CONFIG_MCFUART | |
6d0f6bcf | 24 | #define CONFIG_SYS_UART_PORT (0) |
a605aacd TL |
25 | |
26 | #undef CONFIG_WATCHDOG | |
27 | ||
28 | #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ | |
29 | ||
30 | /* | |
31 | * BOOTP options | |
32 | */ | |
33 | #undef CONFIG_BOOTP_BOOTFILESIZE | |
34 | #undef CONFIG_BOOTP_BOOTPATH | |
35 | #undef CONFIG_BOOTP_GATEWAY | |
36 | #undef CONFIG_BOOTP_HOSTNAME | |
37 | ||
38 | /* | |
39 | * Command line configuration. | |
40 | */ | |
a605aacd | 41 | |
6d0f6bcf | 42 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
a605aacd | 43 | |
6d0f6bcf | 44 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
a605aacd | 45 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
a605aacd TL |
46 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
47 | ||
6d0f6bcf | 48 | #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ |
a605aacd | 49 | |
6d0f6bcf JCPV |
50 | #define CONFIG_SYS_MEMTEST_START 0x400 |
51 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
a605aacd | 52 | |
a605aacd TL |
53 | /* |
54 | * Clock configuration: enable only one of the following options | |
55 | */ | |
56 | ||
6d0f6bcf JCPV |
57 | #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ |
58 | #define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ | |
59 | #define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ | |
a605aacd TL |
60 | |
61 | /* | |
62 | * Low Level Configuration Settings | |
63 | * (address mappings, register initial values, etc.) | |
64 | * You should know what you are doing if you make changes here. | |
65 | */ | |
66 | ||
6d0f6bcf JCPV |
67 | #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ |
68 | #define CONFIG_SYS_MBAR2 0x80000000 | |
a605aacd TL |
69 | |
70 | /*----------------------------------------------------------------------- | |
71 | * Definitions for initial stack pointer and data area (in DPRAM) | |
72 | */ | |
6d0f6bcf | 73 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 74 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
25ddd1fb | 75 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 76 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
a605aacd | 77 | |
5296cb1d | 78 | #define LDS_BOARD_TEXT \ |
0649cd0d SG |
79 | . = DEFINED(env_offset) ? env_offset : .; \ |
80 | env/embedded.o(.text); | |
5296cb1d | 81 | |
0e8d1586 JCPV |
82 | #define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ |
83 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ | |
84 | #define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ | |
a605aacd TL |
85 | |
86 | /*----------------------------------------------------------------------- | |
87 | * Start addresses for the final memory configuration | |
88 | * (Set up by the startup code) | |
6d0f6bcf | 89 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
a605aacd | 90 | */ |
6d0f6bcf JCPV |
91 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
92 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
012522fe | 93 | #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) |
a605aacd TL |
94 | |
95 | #if 0 /* test-only */ | |
96 | #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ | |
97 | #endif | |
98 | ||
6d0f6bcf | 99 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
a605aacd | 100 | |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
102 | #define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ | |
103 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
a605aacd TL |
104 | |
105 | /* | |
106 | * For booting Linux, the board info and command line data | |
107 | * have to be in the first 8 MB of memory, since this is | |
108 | * the maximum mapped by the Linux kernel during initialization ?? | |
109 | */ | |
6d0f6bcf | 110 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
a605aacd TL |
111 | |
112 | /*----------------------------------------------------------------------- | |
113 | * FLASH organization | |
114 | */ | |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_FLASH_CFI |
116 | #ifdef CONFIG_SYS_FLASH_CFI | |
a605aacd | 117 | |
00b1883a | 118 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
119 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
120 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
121 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
122 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
123 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
124 | # define CONFIG_SYS_FLASH_CHECKSUM | |
125 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
a605aacd TL |
126 | #endif |
127 | ||
128 | /*----------------------------------------------------------------------- | |
129 | * Cache Configuration | |
130 | */ | |
6d0f6bcf | 131 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
a605aacd | 132 | |
dd9f054e | 133 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 134 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 135 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 136 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
137 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) |
138 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ | |
139 | CF_ADDRMASK(2) | \ | |
140 | CF_ACR_EN | CF_ACR_SM_ALL) | |
141 | #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ | |
142 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
143 | CF_ACR_EN | CF_ACR_SM_ALL) | |
144 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ | |
145 | CF_CACR_DBWE) | |
146 | ||
a605aacd TL |
147 | /*----------------------------------------------------------------------- |
148 | * Memory bank definitions | |
149 | */ | |
150 | ||
151 | /* CS0 - AMD Flash, address 0xffc00000 */ | |
012522fe TL |
152 | #define CONFIG_SYS_CS0_BASE 0xffe00000 |
153 | #define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ | |
a605aacd | 154 | /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ |
012522fe | 155 | #define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ |
a605aacd TL |
156 | |
157 | /* CS1 - FPGA, address 0xe0000000 */ | |
012522fe TL |
158 | #define CONFIG_SYS_CS1_BASE 0xe0000000 |
159 | #define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ | |
160 | #define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ | |
a605aacd TL |
161 | |
162 | /*----------------------------------------------------------------------- | |
163 | * Port configuration | |
164 | */ | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ |
166 | #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ | |
167 | #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ | |
168 | #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ | |
169 | #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ | |
170 | #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ | |
171 | #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ | |
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172 | |
173 | #endif /* M5249 */ |