[people/ms/u-boot.git] / include / configs / M5271EVB.h

/*
 * Configuation settings for the Freescale M5271EVB
 *
 * Based on MC5272C3 and r5200 board configs
 * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5271EVB_H
#define _M5271EVB_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_MCF52x2		/* define processor family */
#define CONFIG_M5271		/* define processor type */
#define CONFIG_M5271EVB		/* define board type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#undef CONFIG_WATCHDOG		/* disable watchdog */

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#else
#define CONFIG_ENV_ADDR		0xffe04000
#endif
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC

#undef CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMDLINE_EDITING	1 /* enables command line history */
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds */
#define CONFIG_BOOTFILE		"u-boot.bin"
#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_RETRY_COUNT	5
#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M5271EVB
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"uboot=u-boot.bin\0"		\
	"load=tftp $loadaddr $uboot\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b $loadaddr ffe00000 $filesize;"	\
	"save\0"				\
	""

#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#define CONFIG_SYS_HZ			1000000

/* Clock configuration
 * The external oscillator is a 25.000 MHz
 * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
 * bus_clk = (cpu_clk/2) (fixed ratio)
 *
 * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
 * match the new clock speed. Max cpu_clk is 150 MHz.
 */
#define CONFIG_SYS_CLK			100000000
#define CONFIG_SYS_MCF_SYNCR 	(MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x40000000	/* Register Base Addrs */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		0xffe00000

#ifdef	CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/* FLASH organization */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks           */
#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip    */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_SIZE		0x200000

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/* Chip Select 0  : Boot Flash */
#define CONFIG_SYS_CS0_BASE	0xFFE00000
#define CONFIG_SYS_CS0_MASK	0x001F0001
#define CONFIG_SYS_CS0_CTRL	0x00001980

/* Chip Select 1 : External SRAM */
#define CONFIG_SYS_CS1_BASE	0x30000000
#define CONFIG_SYS_CS1_MASK	0x00070001
#define CONFIG_SYS_CS1_CTRL	0x00001900

#endif				/* _M5271EVB_H */
Commit	Line	Data
78b123cd MB	1	/*
	2	* Configuation settings for the Freescale M5271EVB
	3	*
	4	* Based on MC5272C3 and r5200 board configs
	5	* (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com>
	6	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
78b123cd MB	9	*/
	10
	11	/*
	12	* board/config.h - configuration options, board specific
	13	*/
	14
	15	#ifndef _M5271EVB_H
	16	#define _M5271EVB_H
	17
78b123cd MB	18	/*
	19	* High Level Configuration Options (easy to change)
	20	*/
	21	#define CONFIG_MCF52x2 /* define processor family */
	22	#define CONFIG_M5271 /* define processor type */
	23	#define CONFIG_M5271EVB /* define board type */
	24
f28e1bd9	25	#define CONFIG_MCFTMR
78b123cd	26
f28e1bd9	27	#define CONFIG_MCFUART
6d0f6bcf	28	#define CONFIG_SYS_UART_PORT (0)
79e0799c	29	#define CONFIG_BAUDRATE 115200
78b123cd MB	30
	31	#undef CONFIG_WATCHDOG /* disable watchdog */
	32
	33	/* Configuration for environment
	34	* Environment is embedded in u-boot in the second sector of the flash
	35	*/
	36	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586	37	#define CONFIG_ENV_OFFSET 0x4000
78b123cd	38	#else
0e8d1586	39	#define CONFIG_ENV_ADDR 0xffe04000
67c31036	40	#endif
0e8d1586	41	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	42	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	43	#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
78b123cd	44
659e2f67 JL	45	/*
	46	* BOOTP options
	47	*/
	48	#define CONFIG_BOOTP_BOOTFILESIZE
	49	#define CONFIG_BOOTP_BOOTPATH
	50	#define CONFIG_BOOTP_GATEWAY
	51	#define CONFIG_BOOTP_HOSTNAME
	52
8353e139 JL	53	/*
	54	* Command line configuration.
	55	*/
	56	#include <config_cmd_default.h>
	57
dd9f054e	58	#define CONFIG_CMD_CACHE
8353e139 JL	59	#define CONFIG_CMD_PING
8353e139 JL	60	#define CONFIG_CMD_NET
f28e1bd9 TL	61	#define CONFIG_CMD_MII
	62	#define CONFIG_CMD_ELF
	63	#define CONFIG_CMD_FLASH
	64	#define CONFIG_CMD_I2C
	65	#define CONFIG_CMD_MEMORY
	66	#define CONFIG_CMD_MISC
8353e139 JL	67
8353e139 JL	68	#undef CONFIG_CMD_LOADS
8706ef37 RR	69	#define CONFIG_CMD_LOADB
	70	#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
	71	#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
78b123cd	72
f28e1bd9 TL	73	#define CONFIG_MCFFEC
f28e1bd9 TL	74	#ifdef CONFIG_MCFFEC
f28e1bd9	75	# define CONFIG_MII 1
0f3ba7e9	76	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	77	# define CONFIG_SYS_DISCOVER_PHY
	78	# define CONFIG_SYS_RX_ETH_BUFFER 8
	79	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	80
6d0f6bcf JCPV	81	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	82	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	83	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	84	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	85	# ifndef CONFIG_SYS_DISCOVER_PHY
f28e1bd9 TL	86	# define FECDUPLEX FULL
	87	# define FECSPEED _100BASET
	88	# else
6d0f6bcf JCPV	89	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	90	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	91	# endif
6d0f6bcf	92	# endif /* CONFIG_SYS_DISCOVER_PHY */
f28e1bd9 TL	93	#endif
	94
	95	/* I2C */
00f792e0 HS	96	#define CONFIG_SYS_I2C
	97	#define CONFIG_SYS_I2C_FSL
	98	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	99	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	100	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
6d0f6bcf	101	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
f28e1bd9	102
8706ef37	103	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
f28e1bd9 TL	104	#define CONFIG_BOOTFILE "u-boot.bin"
	105	#ifdef CONFIG_MCFFEC
	106	# define CONFIG_NET_RETRY_COUNT 5
	107	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	108	# define CONFIG_IPADDR 192.162.1.2
	109	# define CONFIG_NETMASK 255.255.255.0
	110	# define CONFIG_SERVERIP 192.162.1.1
	111	# define CONFIG_GATEWAYIP 192.162.1.1
	112	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	113	#endif /* FEC_ENET */
	114
8706ef37	115	#define CONFIG_HOSTNAME M5271EVB
f28e1bd9 TL	116	#define CONFIG_EXTRA_ENV_SETTINGS \
	117	"netdev=eth0\0" \
	118	"loadaddr=10000\0" \
8706ef37 RR	119	"uboot=u-boot.bin\0" \
8706ef37 RR	120	"load=tftp $loadaddr $uboot\0" \
f28e1bd9	121	"upd=run load; run prog\0" \
8706ef37 RR	122	"prog=prot off ffe00000 ffe3ffff;" \
	123	"era ffe00000 ffe3ffff;" \
	124	"cp.b $loadaddr ffe00000 $filesize;" \
f28e1bd9 TL	125	"save\0" \
f28e1bd9 TL	126	""
78b123cd	127
6d0f6bcf JCPV	128	#define CONFIG_SYS_PROMPT "=> "
6d0f6bcf JCPV	129	#define CONFIG_SYS_LONGHELP /* undef to save memory */
78b123cd	130
8353e139	131	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	132	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
78b123cd	133	#else
6d0f6bcf	134	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
78b123cd	135	#endif
6d0f6bcf JCPV	136	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	137	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	138	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
78b123cd	139
6d0f6bcf	140	#define CONFIG_SYS_LOAD_ADDR 0x00100000
78b123cd	141
6d0f6bcf JCPV	142	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	143	#define CONFIG_SYS_MEMTEST_END 0x380000
78b123cd	144
6d0f6bcf	145	#define CONFIG_SYS_HZ 1000000
8706ef37 RR	146
	147	/* Clock configuration
	148	* The external oscillator is a 25.000 MHz
	149	* CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
	150	* bus_clk = (cpu_clk/2) (fixed ratio)
	151	*
	152	* If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
	153	* match the new clock speed. Max cpu_clk is 150 MHz.
	154	*/
6d0f6bcf	155	#define CONFIG_SYS_CLK 100000000
8706ef37	156	#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X \| MCF_SYNCR_RFD_DIV1)
78b123cd MB	157
	158	/*
	159	* Low Level Configuration Settings
	160	* (address mappings, register initial values, etc.)
	161	* You should know what you are doing if you make changes here.
	162	*/
	163
6d0f6bcf	164	#define CONFIG_SYS_MBAR 0x40000000 /* Register Base Addrs */
78b123cd	165
78b123cd MB	166	/*
	167	* Definitions for initial stack pointer and data area (in DPRAM)
	168	*/
6d0f6bcf	169	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	170	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb	171	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	172	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
78b123cd MB	173
	174	/*
	175	* Start addresses for the final memory configuration
	176	* (Set up by the startup code)
6d0f6bcf	177	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
78b123cd	178	*/
6d0f6bcf JCPV	179	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	180	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
	181	#define CONFIG_SYS_FLASH_BASE 0xffe00000
78b123cd MB	182
78b123cd MB	183	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	184	#define CONFIG_SYS_MONITOR_BASE 0x20000
78b123cd	185	#else
6d0f6bcf	186	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
78b123cd MB	187	#endif
78b123cd MB	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_MONITOR_LEN 0x40000
	190	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	191	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
78b123cd MB	192
	193	/*
	194	* For booting Linux, the board info and command line data
	195	* have to be in the first 8 MB of memory, since this is
	196	* the maximum mapped by the Linux kernel during initialization ??
	197	*/
6d0f6bcf	198	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
78b123cd MB	199
78b123cd MB	200	/* FLASH organization */
6d0f6bcf JCPV	201	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	202	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
	203	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
78b123cd	204
6d0f6bcf	205	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	206	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf	207	#define CONFIG_SYS_FLASH_SIZE 0x200000
78b123cd MB	208
78b123cd MB	209	/* Cache Configuration */
6d0f6bcf	210	#define CONFIG_SYS_CACHELINE_SIZE 16
78b123cd	211
dd9f054e	212	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	213	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	214	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	215	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	216	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	217	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	218	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	219	CF_ACR_EN \| CF_ACR_SM_ALL)
	220	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	221	CF_CACR_DISD \| CF_CACR_INVI \| \
	222	CF_CACR_CEIB \| CF_CACR_DCM \| \
	223	CF_CACR_EUSP)
	224
8706ef37 RR	225	/* Chip Select 0 : Boot Flash */
	226	#define CONFIG_SYS_CS0_BASE 0xFFE00000
	227	#define CONFIG_SYS_CS0_MASK 0x001F0001
	228	#define CONFIG_SYS_CS0_CTRL 0x00001980
	229
	230	/* Chip Select 1 : External SRAM */
	231	#define CONFIG_SYS_CS1_BASE 0x30000000
	232	#define CONFIG_SYS_CS1_MASK 0x00070001
	233	#define CONFIG_SYS_CS1_CTRL 0x00001900
78b123cd	234
f28e1bd9	235	#endif /* _M5271EVB_H */