[people/ms/u-boot.git] / include / configs / M5275EVB.h

/*
 * Configuation settings for the Motorola MC5275EVB board.
 *
 * By Arthur Shipkowski <art@videon-central.com>
 * Copyright (C) 2005 Videon Central, Inc.
 *
 * Based off of M5272C3 board code by Josef Baumgartner
 * <josef.baumgartner@telex.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5275EVB_H
#define _M5275EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF52x2			/* define processor family */
#define CONFIG_M5275			/* define processor type */
#define CONFIG_M5275EVB			/* define board type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Available command configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_DHCP

#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1
#define CONFIG_MII_INIT		1
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_RX_ETH_BUFFER	8
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#define CONFIG_SYS_FEC0_PINMUX		0
#define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#define CONFIG_SYS_FEC1_PINMUX		0
#define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
#define MCFFEC_TOUT_LOOP	50000
#define CONFIG_HAS_ETH1
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#ifndef CONFIG_SYS_DISCOVER_PHY
#define FECDUPLEX		FULL
#define FECSPEED		_100BASET
#else
#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#endif
#endif
#endif

/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hw support */
#undef CONFIG_SOFT_I2C
#define CONFIG_SYS_I2C_SPEED		80000
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x00000300
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(gpio_reg->par_feci2c)
#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFF0)
#define CONFIG_SYS_I2C_PINMUX_SET	(0x000F)

#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/

#if (CONFIG_CMD_KGDB)
#	define CONFIG_SYS_CBSIZE	1024
#else
#	define CONFIG_SYS_CBSIZE	256
#endif
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_LOAD_ADDR		0x800000

#define CONFIG_BOOTDELAY	5
#define CONFIG_BOOTCOMMAND	"bootm ffe40000"
#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_RETRY_COUNT	5
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* FEC_ENET */

#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${uboot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CLK			150000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x40000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_SIZE		0x200000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
#define CONFIG_SYS_CS0_BASE		0xffe00000
#define CONFIG_SYS_CS0_CTRL		0x00001980
#define CONFIG_SYS_CS0_MASK		0x001F0001

#define CONFIG_SYS_CS1_BASE		0x30000000
#define CONFIG_SYS_CS1_CTRL		0x00001900
#define CONFIG_SYS_CS1_MASK		0x00070001

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_FECI2C		0x0FA0

#endif	/* _M5275EVB_H */
Commit	Line	Data
545c8e0a MF	1	/*
	2	* Configuation settings for the Motorola MC5275EVB board.
	3	*
	4	* By Arthur Shipkowski <art@videon-central.com>
	5	* Copyright (C) 2005 Videon Central, Inc.
	6	*
	7	* Based off of M5272C3 board code by Josef Baumgartner
	8	* <josef.baumgartner@telex.de>
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	/*
	30	* board/config.h - configuration options, board specific
	31	*/
	32
	33	#ifndef _M5275EVB_H
	34	#define _M5275EVB_H
	35
	36	/*
	37	* High Level Configuration Options
	38	* (easy to change)
	39	*/
	40	#define CONFIG_MCF52x2 /* define processor family */
	41	#define CONFIG_M5275 /* define processor type */
	42	#define CONFIG_M5275EVB /* define board type */
	43
	44	#define CONFIG_MCFTMR
	45
	46	#define CONFIG_MCFUART
6d0f6bcf	47	#define CONFIG_SYS_UART_PORT (0)
79e0799c	48	#define CONFIG_BAUDRATE 115200
6d0f6bcf	49	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
545c8e0a MF	50
	51	/* Configuration for environment
	52	* Environment is embedded in u-boot in the second sector of the flash
	53	*/
	54	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	55	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	56	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	57	#define CONFIG_ENV_IS_IN_FLASH 1
545c8e0a	58	#else
0e8d1586 JCPV	59	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	60	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	61	#define CONFIG_ENV_IS_IN_FLASH 1
545c8e0a MF	62	#endif
	63
	64	/*
	65	* BOOTP options
	66	*/
	67	#define CONFIG_BOOTP_BOOTFILESIZE
	68	#define CONFIG_BOOTP_BOOTPATH
	69	#define CONFIG_BOOTP_GATEWAY
	70	#define CONFIG_BOOTP_HOSTNAME
	71
	72	/* Available command configuration */
	73	#include <config_cmd_default.h>
	74
dd9f054e	75	#define CONFIG_CMD_CACHE
545c8e0a MF	76	#define CONFIG_CMD_PING
	77	#define CONFIG_CMD_MII
	78	#define CONFIG_CMD_NET
	79	#define CONFIG_CMD_ELF
	80	#define CONFIG_CMD_FLASH
	81	#define CONFIG_CMD_I2C
	82	#define CONFIG_CMD_MEMORY
	83	#define CONFIG_CMD_DHCP
	84
	85	#undef CONFIG_CMD_LOADS
	86	#undef CONFIG_CMD_LOADB
	87
	88	#define CONFIG_MCFFEC
	89	#ifdef CONFIG_MCFFEC
	90	#define CONFIG_NET_MULTI 1
	91	#define CONFIG_MII 1
0f3ba7e9	92	#define CONFIG_MII_INIT 1
6d0f6bcf JCPV	93	#define CONFIG_SYS_DISCOVER_PHY
	94	#define CONFIG_SYS_RX_ETH_BUFFER 8
	95	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	96	#define CONFIG_SYS_FEC0_PINMUX 0
	97	#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	98	#define CONFIG_SYS_FEC1_PINMUX 0
	99	#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
545c8e0a MF	100	#define MCFFEC_TOUT_LOOP 50000
545c8e0a MF	101	#define CONFIG_HAS_ETH1
6d0f6bcf JCPV	102	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	103	#ifndef CONFIG_SYS_DISCOVER_PHY
545c8e0a MF	104	#define FECDUPLEX FULL
	105	#define FECSPEED _100BASET
	106	#else
6d0f6bcf JCPV	107	#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	108	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
545c8e0a MF	109	#endif
	110	#endif
	111	#endif
	112
	113	/* I2C */
	114	#define CONFIG_FSL_I2C
	115	#define CONFIG_HARD_I2C /* I2C with hw support */
	116	#undef CONFIG_SOFT_I2C
6d0f6bcf JCPV	117	#define CONFIG_SYS_I2C_SPEED 80000
	118	#define CONFIG_SYS_I2C_SLAVE 0x7F
	119	#define CONFIG_SYS_I2C_OFFSET 0x00000300
	120	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	121	#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
	122	#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
	123	#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
545c8e0a	124
6d0f6bcf JCPV	125	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	126	#define CONFIG_SYS_LONGHELP /* undef to save memory */
545c8e0a MF	127
545c8e0a MF	128	#if (CONFIG_CMD_KGDB)
6d0f6bcf	129	# define CONFIG_SYS_CBSIZE 1024
545c8e0a	130	#else
6d0f6bcf	131	# define CONFIG_SYS_CBSIZE 256
545c8e0a	132	#endif
6d0f6bcf JCPV	133	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	134	#define CONFIG_SYS_MAXARGS 16
	135	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
545c8e0a	136
6d0f6bcf	137	#define CONFIG_SYS_LOAD_ADDR 0x800000
545c8e0a MF	138
	139	#define CONFIG_BOOTDELAY 5
	140	#define CONFIG_BOOTCOMMAND "bootm ffe40000"
6d0f6bcf JCPV	141	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	142	#define CONFIG_SYS_MEMTEST_END 0x380000
545c8e0a	143
0e8a7555 TL	144	#ifdef CONFIG_MCFFEC
	145	# define CONFIG_NET_RETRY_COUNT 5
	146	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	147	#endif /* FEC_ENET */
	148
	149	#define CONFIG_EXTRA_ENV_SETTINGS \
	150	"netdev=eth0\0" \
	151	"loadaddr=10000\0" \
	152	"uboot=u-boot.bin\0" \
	153	"load=tftp ${loadaddr} ${uboot}\0" \
	154	"upd=run load; run prog\0" \
	155	"prog=prot off ffe00000 ffe3ffff;" \
	156	"era ffe00000 ffe3ffff;" \
	157	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	158	"save\0" \
	159	""
	160
6d0f6bcf JCPV	161	#define CONFIG_SYS_HZ 1000
6d0f6bcf JCPV	162	#define CONFIG_SYS_CLK 150000000
545c8e0a MF	163
	164	/*
	165	* Low Level Configuration Settings
	166	* (address mappings, register initial values, etc.)
	167	* You should know what you are doing if you make changes here.
	168	*/
	169
6d0f6bcf	170	#define CONFIG_SYS_MBAR 0x40000000
545c8e0a MF	171
	172	/*-----------------------------------------------------------------------
	173	* Definitions for initial stack pointer and data area (in DPRAM)
	174	*/
6d0f6bcf	175	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	176	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	177	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	178	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
545c8e0a MF	179
	180	/*-----------------------------------------------------------------------
	181	* Start addresses for the final memory configuration
	182	* (Set up by the startup code)
6d0f6bcf	183	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
545c8e0a	184	*/
6d0f6bcf JCPV	185	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	186	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
012522fe	187	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
545c8e0a MF	188
545c8e0a MF	189	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	190	#define CONFIG_SYS_MONITOR_BASE 0x20000
545c8e0a	191	#else
6d0f6bcf	192	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
545c8e0a MF	193	#endif
545c8e0a MF	194
6d0f6bcf JCPV	195	#define CONFIG_SYS_MONITOR_LEN 0x20000
	196	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	197	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
545c8e0a MF	198
	199	/*
	200	* For booting Linux, the board info and command line data
	201	* have to be in the first 8 MB of memory, since this is
	202	* the maximum mapped by the Linux kernel during initialization ??
	203	*/
d6e4baf4 TL	204	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4 TL	205	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
545c8e0a MF	206
	207	/*-----------------------------------------------------------------------
	208	* FLASH organization
	209	*/
6d0f6bcf JCPV	210	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	211	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
	212	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
545c8e0a	213
6d0f6bcf	214	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	215	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf	216	#define CONFIG_SYS_FLASH_SIZE 0x200000
545c8e0a MF	217
	218	/*-----------------------------------------------------------------------
	219	* Cache Configuration
	220	*/
6d0f6bcf	221	#define CONFIG_SYS_CACHELINE_SIZE 16
545c8e0a	222
dd9f054e	223	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	224	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	225	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	226	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	227	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	228	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	229	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	230	CF_ACR_EN \| CF_ACR_SM_ALL)
	231	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	232	CF_CACR_DISD \| CF_CACR_INVI \| \
	233	CF_CACR_CEIB \| CF_CACR_DCM \| \
	234	CF_CACR_EUSP)
	235
545c8e0a MF	236	/*-----------------------------------------------------------------------
	237	* Memory bank definitions
	238	*/
012522fe TL	239	#define CONFIG_SYS_CS0_BASE 0xffe00000
	240	#define CONFIG_SYS_CS0_CTRL 0x00001980
	241	#define CONFIG_SYS_CS0_MASK 0x001F0001
545c8e0a	242
012522fe TL	243	#define CONFIG_SYS_CS1_BASE 0x30000000
	244	#define CONFIG_SYS_CS1_CTRL 0x00001900
	245	#define CONFIG_SYS_CS1_MASK 0x00070001
545c8e0a MF	246
	247	/*-----------------------------------------------------------------------
	248	* Port configuration
	249	*/
6d0f6bcf	250	#define CONFIG_SYS_FECI2C 0x0FA0
545c8e0a MF	251
545c8e0a MF	252	#endif /* _M5275EVB_H */