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bf9e3b38 WD |
1 | /* |
2 | * Configuation settings for the Motorola MC5282EVB board. | |
3 | * | |
4 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
bf9e3b38 WD |
7 | */ |
8 | ||
9 | /* | |
10 | * board/config.h - configuration options, board specific | |
11 | */ | |
12 | ||
4e5ca3eb WD |
13 | #ifndef _CONFIG_M5282EVB_H |
14 | #define _CONFIG_M5282EVB_H | |
15 | ||
bf9e3b38 WD |
16 | /* |
17 | * High Level Configuration Options | |
18 | * (easy to change) | |
19 | */ | |
f28e1bd9 | 20 | #define CONFIG_MCFTMR |
bf9e3b38 | 21 | |
f28e1bd9 | 22 | #define CONFIG_MCFUART |
6d0f6bcf | 23 | #define CONFIG_SYS_UART_PORT (0) |
4e5ca3eb | 24 | |
f28e1bd9 | 25 | #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ |
bf9e3b38 WD |
26 | |
27 | /* Configuration for environment | |
28 | * Environment is embedded in u-boot in the second sector of the flash | |
29 | */ | |
0e8d1586 JCPV |
30 | #define CONFIG_ENV_ADDR 0xffe04000 |
31 | #define CONFIG_ENV_SIZE 0x2000 | |
bf9e3b38 | 32 | |
5296cb1d | 33 | #define LDS_BOARD_TEXT \ |
34 | . = DEFINED(env_offset) ? env_offset : .; \ | |
0649cd0d | 35 | env/embedded.o(.text*); |
5296cb1d | 36 | |
659e2f67 JL |
37 | /* |
38 | * BOOTP options | |
39 | */ | |
40 | #define CONFIG_BOOTP_BOOTFILESIZE | |
41 | #define CONFIG_BOOTP_BOOTPATH | |
42 | #define CONFIG_BOOTP_GATEWAY | |
43 | #define CONFIG_BOOTP_HOSTNAME | |
44 | ||
8353e139 JL |
45 | /* |
46 | * Command line configuration. | |
47 | */ | |
8353e139 | 48 | |
f28e1bd9 TL |
49 | #define CONFIG_MCFFEC |
50 | #ifdef CONFIG_MCFFEC | |
f28e1bd9 | 51 | # define CONFIG_MII 1 |
0f3ba7e9 | 52 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
53 | # define CONFIG_SYS_DISCOVER_PHY |
54 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
55 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
f28e1bd9 | 56 | |
6d0f6bcf JCPV |
57 | # define CONFIG_SYS_FEC0_PINMUX 0 |
58 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 59 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
60 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
61 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
f28e1bd9 TL |
62 | # define FECDUPLEX FULL |
63 | # define FECSPEED _100BASET | |
64 | # else | |
6d0f6bcf JCPV |
65 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
66 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
f28e1bd9 | 67 | # endif |
6d0f6bcf | 68 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
f28e1bd9 | 69 | #endif |
bf9e3b38 | 70 | |
f28e1bd9 | 71 | #ifdef CONFIG_MCFFEC |
f28e1bd9 TL |
72 | # define CONFIG_IPADDR 192.162.1.2 |
73 | # define CONFIG_NETMASK 255.255.255.0 | |
74 | # define CONFIG_SERVERIP 192.162.1.1 | |
75 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
f28e1bd9 TL |
76 | #endif /* CONFIG_MCFFEC */ |
77 | ||
4cb4e654 | 78 | #define CONFIG_HOSTNAME M5282EVB |
f28e1bd9 TL |
79 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
80 | "netdev=eth0\0" \ | |
81 | "loadaddr=10000\0" \ | |
82 | "u-boot=u-boot.bin\0" \ | |
83 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
84 | "upd=run load; run prog\0" \ | |
85 | "prog=prot off ffe00000 ffe3ffff;" \ | |
86 | "era ffe00000 ffe3ffff;" \ | |
87 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
88 | "save\0" \ | |
89 | "" | |
bf9e3b38 | 90 | |
6d0f6bcf | 91 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
bf9e3b38 | 92 | |
6d0f6bcf | 93 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
bf9e3b38 | 94 | |
6d0f6bcf | 95 | #define CONFIG_SYS_LOAD_ADDR 0x20000 |
bf9e3b38 | 96 | |
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_MEMTEST_START 0x400 |
98 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
bf9e3b38 | 99 | |
6d0f6bcf | 100 | #define CONFIG_SYS_CLK 64000000 |
bf9e3b38 | 101 | |
f28e1bd9 TL |
102 | /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ |
103 | ||
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ |
105 | #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ | |
bf9e3b38 WD |
106 | |
107 | /* | |
108 | * Low Level Configuration Settings | |
109 | * (address mappings, register initial values, etc.) | |
110 | * You should know what you are doing if you make changes here. | |
111 | */ | |
6d0f6bcf | 112 | #define CONFIG_SYS_MBAR 0x40000000 |
bf9e3b38 | 113 | |
bf9e3b38 WD |
114 | /*----------------------------------------------------------------------- |
115 | * Definitions for initial stack pointer and data area (in DPRAM) | |
116 | */ | |
6d0f6bcf | 117 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 118 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 119 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 120 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
bf9e3b38 WD |
121 | |
122 | /*----------------------------------------------------------------------- | |
123 | * Start addresses for the final memory configuration | |
124 | * (Set up by the startup code) | |
6d0f6bcf | 125 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
bf9e3b38 | 126 | */ |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
128 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
012522fe | 129 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
6d0f6bcf JCPV |
130 | #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 |
131 | #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 | |
bf9e3b38 WD |
132 | |
133 | /* If M5282 port is fully implemented the monitor base will be behind | |
134 | * the vector table. */ | |
14d0a02a | 135 | #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) |
6d0f6bcf | 136 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
f28e1bd9 | 137 | #else |
14d0a02a | 138 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ |
f28e1bd9 | 139 | #endif |
bf9e3b38 | 140 | |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
142 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
143 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
bf9e3b38 | 144 | |
bf9e3b38 WD |
145 | /* |
146 | * For booting Linux, the board info and command line data | |
147 | * have to be in the first 8 MB of memory, since this is | |
148 | * the maximum mapped by the Linux kernel during initialization ?? | |
149 | */ | |
6d0f6bcf | 150 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
bf9e3b38 WD |
151 | |
152 | /*----------------------------------------------------------------------- | |
153 | * FLASH organization | |
154 | */ | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_FLASH_CFI |
156 | #ifdef CONFIG_SYS_FLASH_CFI | |
f28e1bd9 | 157 | |
00b1883a | 158 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
159 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
160 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
161 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
162 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
163 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
164 | # define CONFIG_SYS_FLASH_CHECKSUM | |
165 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
f28e1bd9 | 166 | #endif |
bf9e3b38 WD |
167 | |
168 | /*----------------------------------------------------------------------- | |
169 | * Cache Configuration | |
170 | */ | |
6d0f6bcf | 171 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
bf9e3b38 | 172 | |
dd9f054e | 173 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 174 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 175 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 176 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
177 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) |
178 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
179 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
180 | CF_ACR_EN | CF_ACR_SM_ALL) | |
181 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ | |
182 | CF_CACR_CEIB | CF_CACR_DBWE | \ | |
183 | CF_CACR_EUSP) | |
184 | ||
bf9e3b38 WD |
185 | /*----------------------------------------------------------------------- |
186 | * Memory bank definitions | |
187 | */ | |
012522fe TL |
188 | #define CONFIG_SYS_CS0_BASE 0xFFE00000 |
189 | #define CONFIG_SYS_CS0_CTRL 0x00001980 | |
190 | #define CONFIG_SYS_CS0_MASK 0x001F0001 | |
191 | ||
bf9e3b38 WD |
192 | /*----------------------------------------------------------------------- |
193 | * Port configuration | |
194 | */ | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ |
196 | #define CONFIG_SYS_PADDR 0x0000000 | |
197 | #define CONFIG_SYS_PADAT 0x0000000 | |
198 | ||
199 | #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ | |
200 | #define CONFIG_SYS_PBDDR 0x0000000 | |
201 | #define CONFIG_SYS_PBDAT 0x0000000 | |
202 | ||
203 | #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ | |
204 | #define CONFIG_SYS_PCDDR 0x0000000 | |
205 | #define CONFIG_SYS_PCDAT 0x0000000 | |
206 | ||
207 | #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ | |
208 | #define CONFIG_SYS_PCDDR 0x0000000 | |
209 | #define CONFIG_SYS_PCDAT 0x0000000 | |
210 | ||
211 | #define CONFIG_SYS_PEHLPAR 0xC0 | |
212 | #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ | |
213 | #define CONFIG_SYS_DDRUA 0x05 | |
214 | #define CONFIG_SYS_PJPAR 0xFF | |
4e5ca3eb | 215 | |
f28e1bd9 | 216 | #endif /* _CONFIG_M5282EVB_H */ |