[people/ms/u-boot.git] / include / configs / M53017EVB.h

/*
 * Configuation settings for the Freescale MCF53017EVB.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M53017EVB_H
#define _M53017EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE			115200

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT		5000

/* Command line configuration */
#define CONFIG_CMD_DATE
#define CONFIG_CMD_REGINFO

#define CONFIG_SYS_UNIFY_CACHE

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_TX_ETH_BUFFER	8
#	define CONFIG_SYS_FEC_BUF_USE_SRAM
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#	define CONFIG_HAS_ETH1

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_PINMUX	0
#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
#	define MCFFEC_TOUT_LOOP		50000

#	define CONFIG_BOOTARGS		"root=/dev/mtdblock3 rw rootfstype=jffs2"

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_CNT		(0x8000)
#define CONFIG_SYS_RTC_SETUP		(RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

#define CONFIG_BOOTDELAY		1	/* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM

#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M53017
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 3ffff;"		\
	"era 0 3ffff;"				\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */

#ifdef CONFIG_CMD_KGDB
#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Arg Buf Sz */
#define CONFIG_SYS_LOAD_ADDR	0x40010000

#define CONFIG_SYS_CLK		80000000
#define CONFIG_SYS_CPU_CLK	CONFIG_SYS_CLK * 3

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x20000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x80010000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER		1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_FLASH_SPANSION_S29WS_N	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_BASE + 0x40000)
#define CONFIG_ENV_SIZE			0x1000
#define CONFIG_ENV_SECT_SIZE		0x8000
#define CONFIG_ENV_IS_IN_FLASH		1

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o       (.text*)

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
					 CF_CACR_DCM_P)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash
 * CS1 - Ext SRAM
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0

#define CONFIG_SYS_CS1_BASE		0xC0000000
#define CONFIG_SYS_CS1_MASK		0x00070001
#define CONFIG_SYS_CS1_CTRL		0x00001FA0

#endif				/* _M53017EVB_H */
Commit	Line	Data
536e7dac TL	1	/*
	2	* Configuation settings for the Freescale MCF53017EVB.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
536e7dac TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M53017EVB_H
	15	#define _M53017EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
536e7dac TL	21
	22	#define CONFIG_MCFUART
	23	#define CONFIG_SYS_UART_PORT (0)
	24	#define CONFIG_BAUDRATE 115200
536e7dac TL	25
	26	#undef CONFIG_WATCHDOG
	27	#define CONFIG_WATCHDOG_TIMEOUT 5000
	28
	29	/* Command line configuration */
536e7dac	30	#define CONFIG_CMD_DATE
536e7dac TL	31	#define CONFIG_CMD_REGINFO
	32
	33	#define CONFIG_SYS_UNIFY_CACHE
	34
	35	#define CONFIG_MCFFEC
	36	#ifdef CONFIG_MCFFEC
536e7dac TL	37	# define CONFIG_MII 1
	38	# define CONFIG_MII_INIT 1
	39	# define CONFIG_SYS_DISCOVER_PHY
	40	# define CONFIG_SYS_RX_ETH_BUFFER 8
9e8e9270 TL	41	# define CONFIG_SYS_TX_ETH_BUFFER 8
9e8e9270 TL	42	# define CONFIG_SYS_FEC_BUF_USE_SRAM
536e7dac TL	43	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	44	# define CONFIG_HAS_ETH1
	45
	46	# define CONFIG_SYS_FEC0_PINMUX 0
	47	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	48	# define CONFIG_SYS_FEC1_PINMUX 0
	49	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
	50	# define MCFFEC_TOUT_LOOP 50000
052c0891 TL	51
	52	# define CONFIG_BOOTARGS "root=/dev/mtdblock3 rw rootfstype=jffs2"
	53
536e7dac TL	54	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
	55	# ifndef CONFIG_SYS_DISCOVER_PHY
	56	# define FECDUPLEX FULL
	57	# define FECSPEED _100BASET
	58	# else
	59	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	60	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	61	# endif
	62	# endif /* CONFIG_SYS_DISCOVER_PHY */
	63	#endif
	64
	65	#define CONFIG_MCFRTC
	66	#undef RTC_DEBUG
	67	#define CONFIG_SYS_RTC_CNT (0x8000)
	68	#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP \| RTC_OCEN_CLKEN)
	69
	70	/* Timer */
	71	#define CONFIG_MCFTMR
	72	#undef CONFIG_MCFPIT
	73
	74	/* I2C */
00f792e0 HS	75	#define CONFIG_SYS_I2C
	76	#define CONFIG_SYS_I2C_FSL
	77	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	78	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	79	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
536e7dac TL	80	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	81
	82	#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	83	#define CONFIG_UDP_CHECKSUM
	84
	85	#ifdef CONFIG_MCFFEC
536e7dac TL	86	# define CONFIG_IPADDR 192.162.1.2
	87	# define CONFIG_NETMASK 255.255.255.0
	88	# define CONFIG_SERVERIP 192.162.1.1
	89	# define CONFIG_GATEWAYIP 192.162.1.1
536e7dac TL	90	#endif /* FEC_ENET */
	91
	92	#define CONFIG_HOSTNAME M53017
	93	#define CONFIG_EXTRA_ENV_SETTINGS \
	94	"netdev=eth0\0" \
	95	"loadaddr=40010000\0" \
	96	"u-boot=u-boot.bin\0" \
	97	"load=tftp ${loadaddr) ${u-boot}\0" \
	98	"upd=run load; run prog\0" \
	99	"prog=prot off 0 3ffff;" \
	100	"era 0 3ffff;" \
	101	"cp.b ${loadaddr} 0 ${filesize};" \
	102	"save\0" \
	103	""
	104
	105	#define CONFIG_PRAM 512 /* 512 KB */
536e7dac TL	106	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	107
	108	#ifdef CONFIG_CMD_KGDB
	109	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	110	#else
	111	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	112	#endif
	113
	114	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	115	#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
	116	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
	117	#define CONFIG_SYS_LOAD_ADDR 0x40010000
	118
536e7dac TL	119	#define CONFIG_SYS_CLK 80000000
	120	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
	121
	122	#define CONFIG_SYS_MBAR 0xFC000000
	123
	124	/*
	125	* Low Level Configuration Settings
	126	* (address mappings, register initial values, etc.)
	127	* You should know what you are doing if you make changes here.
	128	*/
	129	/*
	130	* Definitions for initial stack pointer and data area (in DPRAM)
	131	*/
	132	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	133	#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
9e8e9270	134	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	135	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
536e7dac TL	136	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	137
	138	/*
	139	* Start addresses for the final memory configuration
	140	* (Set up by the startup code)
	141	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
	142	*/
	143	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	144	#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
	145	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	146	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
9e8e9270	147	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
536e7dac TL	148	#define CONFIG_SYS_SDRAM_EMOD 0x80010000
	149	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
	150
	151	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	152	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	153
	154	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	155	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	156
	157	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	158	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	159
	160	/*
	161	* For booting Linux, the board info and command line data
	162	* have to be in the first 8 MB of memory, since this is
	163	* the maximum mapped by the Linux kernel during initialization ??
	164	*/
	165	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	166	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
536e7dac TL	167
	168	/*-----------------------------------------------------------------------
	169	* FLASH organization
	170	*/
	171	#define CONFIG_SYS_FLASH_CFI
	172	#ifdef CONFIG_SYS_FLASH_CFI
	173	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff TL	174	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
bbf6bbff TL	175	# define CONFIG_FLASH_SPANSION_S29WS_N 1
4567c7bf	176	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
536e7dac TL	177	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	178	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	179	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	180	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	181	#endif
	182
	183	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	184
	185	/* Configuration for environment
	186	* Environment is embedded in u-boot in the second sector of the flash
	187	*/
944ab340	188	#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000)
536e7dac TL	189	#define CONFIG_ENV_SIZE 0x1000
	190	#define CONFIG_ENV_SECT_SIZE 0x8000
	191	#define CONFIG_ENV_IS_IN_FLASH 1
	192
5296cb1d	193	#define LDS_BOARD_TEXT \
	194	. = DEFINED(env_offset) ? env_offset : .; \
	195	common/env_embedded.o (.text*)
	196
536e7dac TL	197	/*-----------------------------------------------------------------------
	198	* Cache Configuration
	199	*/
	200	#define CONFIG_SYS_CACHELINE_SIZE 16
	201
dd9f054e	202	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	203	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	204	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	205	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	206	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
	207	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	208	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	209	CF_ACR_EN \| CF_ACR_SM_ALL)
	210	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC \| CF_CACR_CINVA \| \
	211	CF_CACR_DCM_P)
	212
536e7dac TL	213	/*-----------------------------------------------------------------------
	214	* Chipselect bank definitions
	215	*/
	216	/*
	217	* CS0 - NOR Flash
	218	* CS1 - Ext SRAM
	219	* CS2 - Available
	220	* CS3 - Available
	221	* CS4 - Available
	222	* CS5 - Available
	223	*/
	224	#define CONFIG_SYS_CS0_BASE 0
	225	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	226	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	227
	228	#define CONFIG_SYS_CS1_BASE 0xC0000000
	229	#define CONFIG_SYS_CS1_MASK 0x00070001
	230	#define CONFIG_SYS_CS1_CTRL 0x00001FA0
	231
	232	#endif /* _M53017EVB_H */