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aa5f1f9d TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF5373 FireEngine board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /* | |
27 | * board/config.h - configuration options, board specific | |
28 | */ | |
29 | ||
30 | #ifndef _M5373EVB_H | |
31 | #define _M5373EVB_H | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | #define CONFIG_MCF532x /* define processor family */ | |
38 | #define CONFIG_M5373 /* define processor type */ | |
39 | ||
aa5f1f9d | 40 | #define CONFIG_MCFUART |
6d0f6bcf | 41 | #define CONFIG_SYS_UART_PORT (0) |
aa5f1f9d | 42 | #define CONFIG_BAUDRATE 115200 |
6d0f6bcf | 43 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
aa5f1f9d TL |
44 | |
45 | #undef CONFIG_WATCHDOG | |
46 | #define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ | |
47 | ||
48 | /* Command line configuration */ | |
49 | #include <config_cmd_default.h> | |
50 | ||
51 | #define CONFIG_CMD_CACHE | |
52 | #define CONFIG_CMD_DATE | |
53 | #define CONFIG_CMD_ELF | |
54 | #define CONFIG_CMD_FLASH | |
55 | #define CONFIG_CMD_I2C | |
56 | #define CONFIG_CMD_MEMORY | |
57 | #define CONFIG_CMD_MISC | |
58 | #define CONFIG_CMD_MII | |
59 | #define CONFIG_CMD_NET | |
60 | #define CONFIG_CMD_PING | |
61 | #define CONFIG_CMD_REGINFO | |
62 | ||
63 | #ifdef NANDFLASH_SIZE | |
64 | # define CONFIG_CMD_NAND | |
65 | #endif | |
66 | ||
6d0f6bcf | 67 | #define CONFIG_SYS_UNIFY_CACHE |
aa5f1f9d TL |
68 | |
69 | #define CONFIG_MCFFEC | |
70 | #ifdef CONFIG_MCFFEC | |
71 | # define CONFIG_NET_MULTI 1 | |
72 | # define CONFIG_MII 1 | |
0f3ba7e9 | 73 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
74 | # define CONFIG_SYS_DISCOVER_PHY |
75 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
76 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
aa5f1f9d | 77 | |
6d0f6bcf JCPV |
78 | # define CONFIG_SYS_FEC0_PINMUX 0 |
79 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 80 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
81 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
82 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
aa5f1f9d TL |
83 | # define FECDUPLEX FULL |
84 | # define FECSPEED _100BASET | |
85 | # else | |
6d0f6bcf JCPV |
86 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
87 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
aa5f1f9d | 88 | # endif |
6d0f6bcf | 89 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
aa5f1f9d TL |
90 | #endif |
91 | ||
92 | #define CONFIG_MCFRTC | |
93 | #undef RTC_DEBUG | |
94 | ||
95 | /* Timer */ | |
96 | #define CONFIG_MCFTMR | |
97 | #undef CONFIG_MCFPIT | |
98 | ||
99 | /* I2C */ | |
100 | #define CONFIG_FSL_I2C | |
101 | #define CONFIG_HARD_I2C /* I2C with hw support */ | |
102 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
6d0f6bcf JCPV |
103 | #define CONFIG_SYS_I2C_SPEED 80000 |
104 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
105 | #define CONFIG_SYS_I2C_OFFSET 0x58000 | |
106 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR | |
aa5f1f9d TL |
107 | |
108 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
109 | #define CONFIG_UDP_CHECKSUM | |
110 | ||
111 | #ifdef CONFIG_MCFFEC | |
112 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 | |
113 | # define CONFIG_IPADDR 192.162.1.2 | |
114 | # define CONFIG_NETMASK 255.255.255.0 | |
115 | # define CONFIG_SERVERIP 192.162.1.1 | |
116 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
117 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
118 | #endif /* FEC_ENET */ | |
119 | ||
120 | #define CONFIG_HOSTNAME M5373EVB | |
121 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
122 | "netdev=eth0\0" \ | |
6d0f6bcf | 123 | "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ |
aa5f1f9d TL |
124 | "u-boot=u-boot.bin\0" \ |
125 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
126 | "upd=run load; run prog\0" \ | |
127 | "prog=prot off 0 2ffff;" \ | |
128 | "era 0 2ffff;" \ | |
129 | "cp.b ${loadaddr} 0 ${filesize};" \ | |
130 | "save\0" \ | |
131 | "" | |
132 | ||
133 | #define CONFIG_PRAM 512 /* 512 KB */ | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_PROMPT "-> " |
135 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
aa5f1f9d TL |
136 | |
137 | #ifdef CONFIG_CMD_KGDB | |
6d0f6bcf | 138 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
aa5f1f9d | 139 | #else |
6d0f6bcf | 140 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
aa5f1f9d TL |
141 | #endif |
142 | ||
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
144 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
145 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
146 | #define CONFIG_SYS_LOAD_ADDR 0x40010000 | |
aa5f1f9d | 147 | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_HZ 1000 |
149 | #define CONFIG_SYS_CLK 80000000 | |
150 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 | |
aa5f1f9d | 151 | |
6d0f6bcf | 152 | #define CONFIG_SYS_MBAR 0xFC000000 |
aa5f1f9d | 153 | |
6d0f6bcf | 154 | #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) |
aa5f1f9d TL |
155 | |
156 | /* | |
157 | * Low Level Configuration Settings | |
158 | * (address mappings, register initial values, etc.) | |
159 | * You should know what you are doing if you make changes here. | |
160 | */ | |
161 | /*----------------------------------------------------------------------- | |
162 | * Definitions for initial stack pointer and data area (in DPRAM) | |
163 | */ | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
165 | #define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ | |
166 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 | |
167 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
168 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10) | |
169 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
aa5f1f9d TL |
170 | |
171 | /*----------------------------------------------------------------------- | |
172 | * Start addresses for the final memory configuration | |
173 | * (Set up by the startup code) | |
6d0f6bcf | 174 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
aa5f1f9d | 175 | */ |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
177 | #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ | |
178 | #define CONFIG_SYS_SDRAM_CFG1 0x53722730 | |
179 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
180 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 | |
181 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
182 | #define CONFIG_SYS_SDRAM_MODE 0x018D0000 | |
aa5f1f9d | 183 | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
185 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
aa5f1f9d | 186 | |
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
188 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
aa5f1f9d | 189 | |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
191 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
aa5f1f9d TL |
192 | |
193 | /* | |
194 | * For booting Linux, the board info and command line data | |
195 | * have to be in the first 8 MB of memory, since this is | |
196 | * the maximum mapped by the Linux kernel during initialization ?? | |
197 | */ | |
6d0f6bcf | 198 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
aa5f1f9d TL |
199 | |
200 | /*----------------------------------------------------------------------- | |
201 | * FLASH organization | |
202 | */ | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_FLASH_CFI |
204 | #ifdef CONFIG_SYS_FLASH_CFI | |
00b1883a | 205 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
206 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
207 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
208 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
209 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
210 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
aa5f1f9d TL |
211 | #endif |
212 | ||
213 | #ifdef NANDFLASH_SIZE | |
6d0f6bcf JCPV |
214 | # define CONFIG_SYS_MAX_NAND_DEVICE 1 |
215 | # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE | |
216 | # define CONFIG_SYS_NAND_SIZE 1 | |
217 | # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
aa5f1f9d TL |
218 | # define NAND_MAX_CHIPS 1 |
219 | # define NAND_ALLOW_ERASE_ALL 1 | |
220 | # define CONFIG_JFFS2_NAND 1 | |
221 | # define CONFIG_JFFS2_DEV "nand0" | |
6d0f6bcf | 222 | # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) |
aa5f1f9d TL |
223 | # define CONFIG_JFFS2_PART_OFFSET 0x00000000 |
224 | #endif | |
225 | ||
6d0f6bcf | 226 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
aa5f1f9d TL |
227 | |
228 | /* Configuration for environment | |
229 | * Environment is embedded in u-boot in the second sector of the flash | |
230 | */ | |
0e8d1586 JCPV |
231 | #define CONFIG_ENV_OFFSET 0x4000 |
232 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 233 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 234 | #define CONFIG_ENV_IS_EMBEDDED 1 |
aa5f1f9d TL |
235 | |
236 | /*----------------------------------------------------------------------- | |
237 | * Cache Configuration | |
238 | */ | |
6d0f6bcf | 239 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
aa5f1f9d TL |
240 | |
241 | /*----------------------------------------------------------------------- | |
242 | * Chipselect bank definitions | |
243 | */ | |
244 | /* | |
245 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
246 | * CS1 - CompactFlash and registers | |
247 | * CS2 - NAND Flash 16, 32, or 64MB | |
248 | * CS3 - Available | |
249 | * CS4 - Available | |
250 | * CS5 - Available | |
251 | */ | |
6d0f6bcf JCPV |
252 | #define CONFIG_SYS_CS0_BASE 0 |
253 | #define CONFIG_SYS_CS0_MASK 0x007f0001 | |
254 | #define CONFIG_SYS_CS0_CTRL 0x00001fa0 | |
aa5f1f9d | 255 | |
6d0f6bcf JCPV |
256 | #define CONFIG_SYS_CS1_BASE 0x10000000 |
257 | #define CONFIG_SYS_CS1_MASK 0x001f0001 | |
258 | #define CONFIG_SYS_CS1_CTRL 0x002A3780 | |
aa5f1f9d TL |
259 | |
260 | #ifdef NANDFLASH_SIZE | |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_CS2_BASE 0x20000000 |
262 | #define CONFIG_SYS_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) | |
263 | #define CONFIG_SYS_CS2_CTRL 0x00001f60 | |
aa5f1f9d TL |
264 | #endif |
265 | ||
266 | #endif /* _M5373EVB_H */ |