projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 05316f8e TL |
1 | /* |
| 2 | * Configuation settings for the Freescale MCF54451 EVB board. | |
| 3 | * | |
| 4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. | |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
| 6 | * | |
| 7 | * See file CREDITS for list of people who contributed to this | |
| 8 | * project. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License as | |
| 12 | * published by the Free Software Foundation; either version 2 of | |
| 13 | * the License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This program is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 20 | * You should have received a copy of the GNU General Public License | |
| 21 | * along with this program; if not, write to the Free Software | |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 23 | * MA 02111-1307 USA | |
| 24 | */ | |
| 25 | ||
| 26 | /* | |
| 27 | * board/config.h - configuration options, board specific | |
| 28 | */ | |
| 29 | ||
| 30 | #ifndef _M54451EVB_H | |
| 31 | #define _M54451EVB_H | |
| 32 | ||
| 33 | /* | |
| 34 | * High Level Configuration Options | |
| 35 | * (easy to change) | |
| 36 | */ | |
| 37 | #define CONFIG_MCF5445x /* define processor family */ | |
| 38 | #define CONFIG_M54451 /* define processor type */ | |
| 39 | #define CONFIG_M54451EVB /* M54451EVB board */ | |
| 40 | ||
| 41 | #define CONFIG_MCFUART | |
| 42 | #define CFG_UART_PORT (0) | |
| 43 | #define CONFIG_BAUDRATE 115200 | |
| 44 | #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } | |
| 45 | ||
| 46 | #undef CONFIG_WATCHDOG | |
| 47 | ||
| 48 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
| 49 | ||
| 50 | /* | |
| 51 | * BOOTP options | |
| 52 | */ | |
| 53 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 54 | #define CONFIG_BOOTP_BOOTPATH | |
| 55 | #define CONFIG_BOOTP_GATEWAY | |
| 56 | #define CONFIG_BOOTP_HOSTNAME | |
| 57 | ||
| 58 | /* Command line configuration */ | |
| 59 | #include <config_cmd_default.h> | |
| 60 | ||
| 61 | #define CONFIG_CMD_BOOTD | |
| 62 | #define CONFIG_CMD_CACHE | |
| 63 | #define CONFIG_CMD_DATE | |
| 64 | #define CONFIG_CMD_DHCP | |
| 65 | #define CONFIG_CMD_ELF | |
| 66 | #define CONFIG_CMD_FLASH | |
| 67 | #define CONFIG_CMD_I2C | |
| 68 | #undef CONFIG_CMD_JFFS2 | |
| 69 | #define CONFIG_CMD_MEMORY | |
| 70 | #define CONFIG_CMD_MISC | |
| 71 | #define CONFIG_CMD_MII | |
| 72 | #define CONFIG_CMD_NET | |
| 73 | #define CONFIG_CMD_PING | |
| 74 | #define CONFIG_CMD_REGINFO | |
| 75 | #define CONFIG_CMD_SPI | |
| 76 | #define CONFIG_CMD_SF | |
| 77 | ||
| 78 | #undef CONFIG_CMD_LOADB | |
| 79 | #undef CONFIG_CMD_LOADS | |
| 80 | ||
| 81 | /* Network configuration */ | |
| 82 | #define CONFIG_MCFFEC | |
| 83 | #ifdef CONFIG_MCFFEC | |
| 84 | # define CONFIG_NET_MULTI 1 | |
| 85 | # define CONFIG_MII 1 | |
| 86 | # define CONFIG_MII_INIT 1 | |
| 87 | # define CFG_DISCOVER_PHY | |
| 88 | # define CFG_RX_ETH_BUFFER 8 | |
| 89 | # define CFG_FAULT_ECHO_LINK_DOWN | |
| 90 | ||
| 91 | # define CFG_FEC0_PINMUX 0 | |
| 92 | # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE | |
| 93 | # define MCFFEC_TOUT_LOOP 50000 | |
| 94 | ||
| 95 | # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
| 96 | # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" | |
| 97 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 | |
| 98 | # define CONFIG_ETHPRIME "FEC0" | |
| 99 | # define CONFIG_IPADDR 192.162.1.2 | |
| 100 | # define CONFIG_NETMASK 255.255.255.0 | |
| 101 | # define CONFIG_SERVERIP 192.162.1.1 | |
| 102 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
| 103 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
| 104 | ||
| 105 | /* If CFG_DISCOVER_PHY is not defined - hardcoded */ | |
| 106 | # ifndef CFG_DISCOVER_PHY | |
| 107 | # define FECDUPLEX FULL | |
| 108 | # define FECSPEED _100BASET | |
| 109 | # else | |
| 110 | # ifndef CFG_FAULT_ECHO_LINK_DOWN | |
| 111 | # define CFG_FAULT_ECHO_LINK_DOWN | |
| 112 | # endif | |
| 113 | # endif /* CFG_DISCOVER_PHY */ | |
| 114 | #endif | |
| 115 | ||
| 116 | #define CONFIG_HOSTNAME M54451EVB | |
| 117 | #ifdef CFG_STMICRO_BOOT | |
| 118 | /* ST Micro serial flash */ | |
| 119 | #define CFG_LOAD_ADDR2 0x40010007 | |
| 120 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 121 | "netdev=eth0\0" \ | |
| 122 | "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ | |
| 123 | "loadaddr=0x40010000\0" \ | |
| 124 | "sbfhdr=sbfhdr.bin\0" \ | |
| 125 | "uboot=u-boot.bin\0" \ | |
| 126 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
| 127 | "tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \ | |
| 128 | "upd=run load; run prog\0" \ | |
| 129 | "prog=sf probe 0:1 10000 1;" \ | |
| 130 | "sf erase 0 30000;" \ | |
| 131 | "sf write ${loadaddr} 0 30000;" \ | |
| 132 | "save\0" \ | |
| 133 | "" | |
| 134 | #else | |
| 135 | #define CFG_UBOOT_END 0x3FFFF | |
| 136 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 137 | "netdev=eth0\0" \ | |
| 138 | "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ | |
| 139 | "loadaddr=40010000\0" \ | |
| 140 | "u-boot=u-boot.bin\0" \ | |
| 141 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
| 142 | "upd=run load; run prog\0" \ | |
| f78ced30 TL |
143 | "prog=prot off 0 " MK_STR(CFG_UBOOT_END) \ |
| 144 | "; era 0 " MK_STR(CFG_UBOOT_END) " ;" \ | |
| 05316f8e TL |
145 | "cp.b ${loadaddr} 0 ${filesize};" \ |
| 146 | "save\0" \ | |
| 147 | "" | |
| 148 | #endif | |
| 149 | ||
| 150 | /* Realtime clock */ | |
| 151 | #define CONFIG_MCFRTC | |
| 152 | #undef RTC_DEBUG | |
| 153 | #define CFG_RTC_OSCILLATOR (32 * CFG_HZ) | |
| 154 | ||
| 155 | /* Timer */ | |
| 156 | #define CONFIG_MCFTMR | |
| 157 | #undef CONFIG_MCFPIT | |
| 158 | ||
| 159 | /* I2c */ | |
| 160 | #define CONFIG_FSL_I2C | |
| 161 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 162 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 163 | #define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ | |
| 164 | #define CFG_I2C_SLAVE 0x7F | |
| 165 | #define CFG_I2C_OFFSET 0x58000 | |
| 166 | #define CFG_IMMR CFG_MBAR | |
| 167 | ||
| 168 | /* DSPI and Serial Flash */ | |
| 169 | #define CONFIG_CF_DSPI | |
| 170 | #define CONFIG_SERIAL_FLASH | |
| 171 | #define CONFIG_HARD_SPI | |
| 172 | #define CFG_SER_FLASH_BASE 0x01000000 | |
| 173 | #define CFG_SBFHDR_SIZE 0x7 | |
| 174 | #ifdef CONFIG_CMD_SPI | |
| 175 | # define CONFIG_SPI_FLASH | |
| 176 | # define CONFIG_SPI_FLASH_STMICRO | |
| 177 | ||
| 178 | # define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ | |
| 179 | DSPI_DCTAR_CPOL | \ | |
| 180 | DSPI_DCTAR_CPHA | \ | |
| 181 | DSPI_DCTAR_PCSSCK_1CLK | \ | |
| 182 | DSPI_DCTAR_PASC(0) | \ | |
| 183 | DSPI_DCTAR_PDT(0) | \ | |
| 184 | DSPI_DCTAR_CSSCK(0) | \ | |
| 185 | DSPI_DCTAR_ASC(0) | \ | |
| 186 | DSPI_DCTAR_PBR(0) | \ | |
| 187 | DSPI_DCTAR_DT(1) | \ | |
| 188 | DSPI_DCTAR_BR(1)) | |
| 189 | #endif | |
| 190 | ||
| 191 | /* Input, PCI, Flexbus, and VCO */ | |
| 192 | #define CONFIG_EXTRA_CLOCK | |
| 193 | ||
| 194 | #define CONFIG_PRAM 2048 /* 2048 KB */ | |
| 195 | ||
| 196 | #define CFG_PROMPT "-> " | |
| 197 | #define CFG_LONGHELP /* undef to save memory */ | |
| 198 | ||
| 199 | #if defined(CONFIG_CMD_KGDB) | |
| 200 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 201 | #else | |
| 202 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 203 | #endif | |
| 204 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 205 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 206 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 207 | ||
| 208 | #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) | |
| 209 | ||
| 210 | #define CFG_HZ 1000 | |
| 211 | ||
| 212 | #define CFG_MBAR 0xFC000000 | |
| 213 | ||
| 214 | /* | |
| 215 | * Low Level Configuration Settings | |
| 216 | * (address mappings, register initial values, etc.) | |
| 217 | * You should know what you are doing if you make changes here. | |
| 218 | */ | |
| 219 | ||
| 220 | /*----------------------------------------------------------------------- | |
| 221 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 222 | */ | |
| 223 | #define CFG_INIT_RAM_ADDR 0x80000000 | |
| 224 | #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ | |
| 225 | #define CFG_INIT_RAM_CTRL 0x221 | |
| 226 | #define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */ | |
| 227 | #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32) | |
| 228 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 229 | #define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32) | |
| 230 | ||
| 231 | /*----------------------------------------------------------------------- | |
| 232 | * Start addresses for the final memory configuration | |
| 233 | * (Set up by the startup code) | |
| 234 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
| 235 | */ | |
| 236 | #define CFG_SDRAM_BASE 0x40000000 | |
| 237 | #define CFG_SDRAM_SIZE 128 /* SDRAM size in MB */ | |
| 238 | #define CFG_SDRAM_CFG1 0x33633F30 | |
| 239 | #define CFG_SDRAM_CFG2 0x57670000 | |
| 240 | #define CFG_SDRAM_CTRL 0xE20D2C00 | |
| 241 | #define CFG_SDRAM_EMOD 0x80810000 | |
| 242 | #define CFG_SDRAM_MODE 0x008D0000 | |
| 243 | #define CFG_SDRAM_DRV_STRENGTH 0x44 | |
| 244 | ||
| 245 | #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 | |
| 246 | #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) | |
| 247 | ||
| 248 | #ifdef CONFIG_CF_SBF | |
| 249 | # define CFG_MONITOR_BASE (TEXT_BASE + 0x400) | |
| 250 | #else | |
| 251 | # define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) | |
| 252 | #endif | |
| 253 | #define CFG_BOOTPARAMS_LEN 64*1024 | |
| 254 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 255 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
| 256 | ||
| 257 | /* | |
| 258 | * For booting Linux, the board info and command line data | |
| 259 | * have to be in the first 8 MB of memory, since this is | |
| 260 | * the maximum mapped by the Linux kernel during initialization ?? | |
| 261 | */ | |
| 262 | /* Initial Memory map for Linux */ | |
| 263 | #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) | |
| 264 | ||
| 265 | /* Configuration for environment | |
| 266 | * Environment is embedded in u-boot in the second sector of the flash | |
| 267 | */ | |
| 268 | #if defined(CONFIG_CF_SBF) | |
| 0b5099a8 | 269 | # define CONFIG_ENV_IS_IN_SPI_FLASH 1 |
| 05316f8e TL |
270 | # define CFG_ENV_SPI_CS 1 |
| 271 | # define CFG_ENV_OFFSET 0x20000 | |
| 272 | # define CFG_ENV_SIZE 0x2000 | |
| 273 | # define CFG_ENV_SECT_SIZE 0x10000 | |
| 274 | #else | |
| 5a1aceb0 | 275 | # define CONFIG_ENV_IS_IN_FLASH 1 |
| 05316f8e TL |
276 | # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) |
| 277 | # define CFG_ENV_SECT_SIZE 0x2000 | |
| 278 | #endif | |
| 279 | #undef CONFIG_ENV_OVERWRITE | |
| 280 | #undef CFG_ENV_IS_EMBEDDED | |
| 281 | ||
| 282 | /*----------------------------------------------------------------------- | |
| 283 | * FLASH organization | |
| 284 | */ | |
| 285 | #ifdef CFG_STMICRO_BOOT | |
| 286 | # define CFG_FLASH_BASE CFG_SER_FLASH_BASE | |
| 287 | # define CFG_FLASH0_BASE CFG_SER_FLASH_BASE | |
| 288 | # define CFG_FLASH1_BASE CFG_CS0_BASE | |
| 289 | #endif | |
| 290 | #ifdef CFG_SPANSION_BOOT | |
| 291 | # define CFG_FLASH_BASE CFG_CS0_BASE | |
| 292 | # define CFG_FLASH0_BASE CFG_CS0_BASE | |
| 293 | # define CFG_FLASH1_BASE CFG_SER_FLASH_BASE | |
| 294 | #endif | |
| 295 | ||
| 296 | #define CFG_FLASH_CFI | |
| 297 | #ifdef CFG_FLASH_CFI | |
| 298 | ||
| 299 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
| 300 | # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ | |
| 301 | # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
| 302 | # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
| 303 | # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
| 304 | # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
| 305 | # define CFG_FLASH_CHECKSUM | |
| 306 | # define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE } | |
| 307 | ||
| 308 | #endif | |
| 309 | ||
| 310 | /* | |
| 311 | * This is setting for JFFS2 support in u-boot. | |
| 312 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
| 313 | */ | |
| 314 | #ifdef CFG_SPANSION_BOOT | |
| 315 | # define CONFIG_JFFS2_DEV "nor0" | |
| 316 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 | |
| 317 | # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) | |
| 318 | #endif | |
| 319 | #ifdef CFG_STMICRO_BOOT | |
| 320 | # define CONFIG_JFFS2_DEV "nor0" | |
| 321 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 | |
| 322 | # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) | |
| 323 | #endif | |
| 324 | ||
| 325 | /*----------------------------------------------------------------------- | |
| 326 | * Cache Configuration | |
| 327 | */ | |
| 328 | #define CFG_CACHELINE_SIZE 16 | |
| 329 | ||
| 330 | /*----------------------------------------------------------------------- | |
| 331 | * Memory bank definitions | |
| 332 | */ | |
| 333 | /* | |
| 334 | * CS0 - NOR Flash 8MB | |
| 335 | * CS1 - Available | |
| 336 | * CS2 - Available | |
| 337 | * CS3 - Available | |
| 338 | * CS4 - Available | |
| 339 | * CS5 - Available | |
| 340 | */ | |
| 341 | ||
| 342 | /* SPANSION Flash */ | |
| 343 | #define CFG_CS0_BASE 0x00000000 | |
| 344 | #define CFG_CS0_MASK 0x007F0001 | |
| 345 | #define CFG_CS0_CTRL 0x00001180 | |
| 346 | ||
| 347 | #define CFG_SPANSION_BASE CFG_CS0_BASE | |
| 348 | ||
| 349 | #endif /* _M54451EVB_H */ |