[people/ms/u-boot.git] / include / configs / M54451EVB.h

/*
 * Configuation settings for the Freescale MCF54451 EVB board.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54451EVB_H
#define _M54451EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF5445x		/* define processor family */
#define CONFIG_M54451		/* define processor type */
#define CONFIG_M54451EVB	/* M54451EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_JFFS2
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF

#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS

/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_MULTI		1
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP 50000

#	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
#	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
#	define CONFIG_ETHPRIME		"FEC0"
#	define CONFIG_IPADDR		192.162.1.2
#	define CONFIG_NETMASK		255.255.255.0
#	define CONFIG_SERVERIP		192.162.1.1
#	define CONFIG_GATEWAYIP		192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		M54451EVB
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#else
#define CONFIG_SYS_UBOOT_END	0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END)	\
	"; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;"	\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address  */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x58000
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SER_FLASH_BASE	0x01000000
#define CONFIG_SYS_SBFHDR_SIZE		0x7
#ifdef CONFIG_CMD_SPI
#	define CONFIG_SPI_FLASH
#	define CONFIG_SPI_FLASH_STMICRO

#	define CONFIG_SYS_DSPI_DCTAR0		(DSPI_DCTAR_TRSZ(7) | \
					 DSPI_DCTAR_CPOL | \
					 DSPI_DCTAR_CPHA | \
					 DSPI_DCTAR_PCSSCK_1CLK | \
					 DSPI_DCTAR_PASC(0) | \
					 DSPI_DCTAR_PDT(0) | \
					 DSPI_DCTAR_CSSCK(0) | \
					 DSPI_DCTAR_ASC(0) | \
					 DSPI_DCTAR_PBR(0) | \
					 DSPI_DCTAR_DT(1) | \
					 DSPI_DCTAR_BR(1))
#endif

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE			1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE			256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_HZ			1000

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_SIZE	256	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x33633F30
#define CONFIG_SYS_SDRAM_CFG2		0x57670000
#define CONFIG_SYS_SDRAM_CTRL		0xE20D2C00
#define CONFIG_SYS_SDRAM_EMOD		0x80810000
#define CONFIG_SYS_SDRAM_MODE		0x008D0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x44

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#if defined(CONFIG_CF_SBF)
#	define CONFIG_ENV_IS_IN_SPI_FLASH	1
#	define CONFIG_ENV_SPI_CS		1
#	define CONFIG_ENV_OFFSET		0x20000
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#else
#	define CONFIG_ENV_IS_IN_FLASH	1
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
#	define CONFIG_ENV_SECT_SIZE	0x2000
#endif
#undef CONFIG_ENV_OVERWRITE
#undef CONFIG_ENV_IS_EMBEDDED

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_SER_FLASH_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_SER_FLASH_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS0_BASE
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_SER_FLASH_BASE
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }

#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_SYS_SPANSION_BOOT
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE		16

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 8MB
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

 /* SPANSION Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x007F0001
#define CONFIG_SYS_CS0_CTRL		0x00001180

#define CONFIG_SYS_SPANSION_BASE	CONFIG_SYS_CS0_BASE

#endif				/* _M54451EVB_H */
Commit	Line	Data
05316f8e TL	1	/*
	2	* Configuation settings for the Freescale MCF54451 EVB board.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
	30	#ifndef _M54451EVB_H
	31	#define _M54451EVB_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_MCF5445x /* define processor family */
	38	#define CONFIG_M54451 /* define processor type */
	39	#define CONFIG_M54451EVB /* M54451EVB board */
	40
	41	#define CONFIG_MCFUART
6d0f6bcf	42	#define CONFIG_SYS_UART_PORT (0)
05316f8e	43	#define CONFIG_BAUDRATE 115200
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
05316f8e TL	45
	46	#undef CONFIG_WATCHDOG
	47
	48	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	49
	50	/*
	51	* BOOTP options
	52	*/
	53	#define CONFIG_BOOTP_BOOTFILESIZE
	54	#define CONFIG_BOOTP_BOOTPATH
	55	#define CONFIG_BOOTP_GATEWAY
	56	#define CONFIG_BOOTP_HOSTNAME
	57
	58	/* Command line configuration */
	59	#include <config_cmd_default.h>
	60
	61	#define CONFIG_CMD_BOOTD
	62	#define CONFIG_CMD_CACHE
	63	#define CONFIG_CMD_DATE
	64	#define CONFIG_CMD_DHCP
	65	#define CONFIG_CMD_ELF
	66	#define CONFIG_CMD_FLASH
	67	#define CONFIG_CMD_I2C
	68	#undef CONFIG_CMD_JFFS2
	69	#define CONFIG_CMD_MEMORY
	70	#define CONFIG_CMD_MISC
	71	#define CONFIG_CMD_MII
	72	#define CONFIG_CMD_NET
	73	#define CONFIG_CMD_PING
	74	#define CONFIG_CMD_REGINFO
	75	#define CONFIG_CMD_SPI
	76	#define CONFIG_CMD_SF
	77
	78	#undef CONFIG_CMD_LOADB
	79	#undef CONFIG_CMD_LOADS
	80
	81	/* Network configuration */
	82	#define CONFIG_MCFFEC
	83	#ifdef CONFIG_MCFFEC
	84	# define CONFIG_NET_MULTI 1
	85	# define CONFIG_MII 1
	86	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	87	# define CONFIG_SYS_DISCOVER_PHY
	88	# define CONFIG_SYS_RX_ETH_BUFFER 8
	89	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
05316f8e	90
6d0f6bcf JCPV	91	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	92	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
05316f8e TL	93	# define MCFFEC_TOUT_LOOP 50000
	94
	95	# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	96	# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
	97	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	98	# define CONFIG_ETHPRIME "FEC0"
	99	# define CONFIG_IPADDR 192.162.1.2
	100	# define CONFIG_NETMASK 255.255.255.0
	101	# define CONFIG_SERVERIP 192.162.1.1
	102	# define CONFIG_GATEWAYIP 192.162.1.1
	103	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	104
6d0f6bcf JCPV	105	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	106	# ifndef CONFIG_SYS_DISCOVER_PHY
05316f8e TL	107	# define FECDUPLEX FULL
	108	# define FECSPEED _100BASET
	109	# else
6d0f6bcf JCPV	110	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	111	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
05316f8e	112	# endif
6d0f6bcf	113	# endif /* CONFIG_SYS_DISCOVER_PHY */
05316f8e TL	114	#endif
	115
	116	#define CONFIG_HOSTNAME M54451EVB
6d0f6bcf	117	#ifdef CONFIG_SYS_STMICRO_BOOT
05316f8e	118	/* ST Micro serial flash */
6d0f6bcf	119	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
05316f8e TL	120	#define CONFIG_EXTRA_ENV_SETTINGS \
05316f8e TL	121	"netdev=eth0\0" \
6d0f6bcf	122	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
05316f8e TL	123	"loadaddr=0x40010000\0" \
	124	"sbfhdr=sbfhdr.bin\0" \
	125	"uboot=u-boot.bin\0" \
	126	"load=tftp ${loadaddr} ${sbfhdr};" \
6d0f6bcf	127	"tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
05316f8e TL	128	"upd=run load; run prog\0" \
	129	"prog=sf probe 0:1 10000 1;" \
	130	"sf erase 0 30000;" \
	131	"sf write ${loadaddr} 0 30000;" \
	132	"save\0" \
	133	""
	134	#else
6d0f6bcf	135	#define CONFIG_SYS_UBOOT_END 0x3FFFF
05316f8e TL	136	#define CONFIG_EXTRA_ENV_SETTINGS \
05316f8e TL	137	"netdev=eth0\0" \
6d0f6bcf	138	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
05316f8e TL	139	"loadaddr=40010000\0" \
	140	"u-boot=u-boot.bin\0" \
	141	"load=tftp ${loadaddr) ${u-boot}\0" \
	142	"upd=run load; run prog\0" \
6d0f6bcf JCPV	143	"prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END) \
6d0f6bcf JCPV	144	"; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;" \
05316f8e TL	145	"cp.b ${loadaddr} 0 ${filesize};" \
	146	"save\0" \
	147	""
	148	#endif
	149
	150	/* Realtime clock */
	151	#define CONFIG_MCFRTC
	152	#undef RTC_DEBUG
6d0f6bcf	153	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
05316f8e TL	154
	155	/* Timer */
	156	#define CONFIG_MCFTMR
	157	#undef CONFIG_MCFPIT
	158
	159	/* I2c */
	160	#define CONFIG_FSL_I2C
	161	#define CONFIG_HARD_I2C /* I2C with hardware support */
	162	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	163	#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
	164	#define CONFIG_SYS_I2C_SLAVE 0x7F
	165	#define CONFIG_SYS_I2C_OFFSET 0x58000
	166	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
05316f8e TL	167
	168	/* DSPI and Serial Flash */
	169	#define CONFIG_CF_DSPI
	170	#define CONFIG_SERIAL_FLASH
	171	#define CONFIG_HARD_SPI
6d0f6bcf JCPV	172	#define CONFIG_SYS_SER_FLASH_BASE 0x01000000
6d0f6bcf JCPV	173	#define CONFIG_SYS_SBFHDR_SIZE 0x7
05316f8e TL	174	#ifdef CONFIG_CMD_SPI
	175	# define CONFIG_SPI_FLASH
	176	# define CONFIG_SPI_FLASH_STMICRO
	177
6d0f6bcf	178	# define CONFIG_SYS_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) \| \
05316f8e TL	179	DSPI_DCTAR_CPOL \| \
	180	DSPI_DCTAR_CPHA \| \
	181	DSPI_DCTAR_PCSSCK_1CLK \| \
	182	DSPI_DCTAR_PASC(0) \| \
	183	DSPI_DCTAR_PDT(0) \| \
	184	DSPI_DCTAR_CSSCK(0) \| \
	185	DSPI_DCTAR_ASC(0) \| \
	186	DSPI_DCTAR_PBR(0) \| \
	187	DSPI_DCTAR_DT(1) \| \
	188	DSPI_DCTAR_BR(1))
	189	#endif
	190
	191	/* Input, PCI, Flexbus, and VCO */
	192	#define CONFIG_EXTRA_CLOCK
	193
	194	#define CONFIG_PRAM 2048 /* 2048 KB */
	195
6d0f6bcf JCPV	196	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	197	#define CONFIG_SYS_LONGHELP /* undef to save memory */
05316f8e TL	198
05316f8e TL	199	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	200	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
05316f8e	201	#else
6d0f6bcf	202	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
05316f8e	203	#endif
6d0f6bcf JCPV	204	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	205	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	206	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
05316f8e	207
6d0f6bcf	208	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
05316f8e	209
6d0f6bcf	210	#define CONFIG_SYS_HZ 1000
05316f8e	211
6d0f6bcf	212	#define CONFIG_SYS_MBAR 0xFC000000
05316f8e TL	213
	214	/*
	215	* Low Level Configuration Settings
	216	* (address mappings, register initial values, etc.)
	217	* You should know what you are doing if you make changes here.
	218	*/
	219
	220	/*-----------------------------------------------------------------------
	221	* Definitions for initial stack pointer and data area (in DPRAM)
	222	*/
6d0f6bcf JCPV	223	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
	224	#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
	225	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
	226	#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
	227	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
	228	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	229	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
05316f8e TL	230
	231	/*-----------------------------------------------------------------------
	232	* Start addresses for the final memory configuration
	233	* (Set up by the startup code)
6d0f6bcf	234	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
05316f8e	235	*/
6d0f6bcf JCPV	236	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	237	#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
	238	#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
	239	#define CONFIG_SYS_SDRAM_CFG2 0x57670000
	240	#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
	241	#define CONFIG_SYS_SDRAM_EMOD 0x80810000
	242	#define CONFIG_SYS_SDRAM_MODE 0x008D0000
	243	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
	244
	245	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	246	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
05316f8e TL	247
05316f8e TL	248	#ifdef CONFIG_CF_SBF
6d0f6bcf	249	# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
05316f8e	250	#else
6d0f6bcf	251	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
05316f8e	252	#endif
6d0f6bcf JCPV	253	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	254	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	255	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
05316f8e TL	256
	257	/*
	258	* For booting Linux, the board info and command line data
	259	* have to be in the first 8 MB of memory, since this is
	260	* the maximum mapped by the Linux kernel during initialization ??
	261	*/
	262	/* Initial Memory map for Linux */
6d0f6bcf	263	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
05316f8e TL	264
	265	/* Configuration for environment
	266	* Environment is embedded in u-boot in the second sector of the flash
	267	*/
	268	#if defined(CONFIG_CF_SBF)
0b5099a8	269	# define CONFIG_ENV_IS_IN_SPI_FLASH 1
0e8d1586 JCPV	270	# define CONFIG_ENV_SPI_CS 1
	271	# define CONFIG_ENV_OFFSET 0x20000
	272	# define CONFIG_ENV_SIZE 0x2000
	273	# define CONFIG_ENV_SECT_SIZE 0x10000
05316f8e	274	#else
5a1aceb0	275	# define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	276	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
0e8d1586	277	# define CONFIG_ENV_SECT_SIZE 0x2000
05316f8e TL	278	#endif
05316f8e TL	279	#undef CONFIG_ENV_OVERWRITE
0e8d1586	280	#undef CONFIG_ENV_IS_EMBEDDED
05316f8e TL	281
	282	/*-----------------------------------------------------------------------
	283	* FLASH organization
	284	*/
6d0f6bcf JCPV	285	#ifdef CONFIG_SYS_STMICRO_BOOT
	286	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_SER_FLASH_BASE
	287	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_SER_FLASH_BASE
	288	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS0_BASE
05316f8e	289	#endif
6d0f6bcf JCPV	290	#ifdef CONFIG_SYS_SPANSION_BOOT
	291	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	292	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	293	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_SER_FLASH_BASE
05316f8e TL	294	#endif
05316f8e TL	295
6d0f6bcf JCPV	296	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	297	#ifdef CONFIG_SYS_FLASH_CFI
05316f8e TL	298
05316f8e TL	299	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	300	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	301	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	302	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	303	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	304	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	305	# define CONFIG_SYS_FLASH_CHECKSUM
	306	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
05316f8e TL	307
	308	#endif
	309
	310	/*
	311	* This is setting for JFFS2 support in u-boot.
	312	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	313	*/
6d0f6bcf	314	#ifdef CONFIG_SYS_SPANSION_BOOT
05316f8e TL	315	# define CONFIG_JFFS2_DEV "nor0"
05316f8e TL	316	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	317	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
05316f8e	318	#endif
6d0f6bcf	319	#ifdef CONFIG_SYS_STMICRO_BOOT
05316f8e TL	320	# define CONFIG_JFFS2_DEV "nor0"
05316f8e TL	321	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	322	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
05316f8e TL	323	#endif
	324
	325	/*-----------------------------------------------------------------------
	326	* Cache Configuration
	327	*/
6d0f6bcf	328	#define CONFIG_SYS_CACHELINE_SIZE 16
05316f8e TL	329
	330	/*-----------------------------------------------------------------------
	331	* Memory bank definitions
	332	*/
	333	/*
	334	* CS0 - NOR Flash 8MB
	335	* CS1 - Available
	336	* CS2 - Available
	337	* CS3 - Available
	338	* CS4 - Available
	339	* CS5 - Available
	340	*/
	341
	342	/* SPANSION Flash */
6d0f6bcf JCPV	343	#define CONFIG_SYS_CS0_BASE 0x00000000
	344	#define CONFIG_SYS_CS0_MASK 0x007F0001
	345	#define CONFIG_SYS_CS0_CTRL 0x00001180
05316f8e	346
6d0f6bcf	347	#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
05316f8e TL	348
05316f8e TL	349	#endif /* _M54451EVB_H */