[people/ms/u-boot.git] / include / configs / M54455EVB.h

/*
 * Configuation settings for the Freescale MCF54455 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54455EVB_H
#define _M54455EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF5445x		/* define processor family */
#define CONFIG_M54455		/* define processor type */
#define CONFIG_M54455EVB	/* M54455EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#undef CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF

#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS

/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_MULTI		1
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC1_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP 50000
#	define CONFIG_HAS_ETH1

#	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
#	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
#	define CONFIG_ETH1ADDR		00:e0:0c:bc:e5:61
#	define CONFIG_ETHPRIME		"FEC0"
#	define CONFIG_IPADDR		192.162.1.2
#	define CONFIG_NETMASK		255.255.255.0
#	define CONFIG_SERVERIP		192.162.1.1
#	define CONFIG_GATEWAYIP		192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		M54455EVB
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010013
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 0x30000;"	\
	"save\0"				\
	""
#else
/* Atmel and Intel */
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_SYS_UBOOT_END	0x0403FFFF
#elif defined(CONFIG_SYS_INTEL_BOOT)
#	define CONFIG_SYS_UBOOT_END	0x3FFFF
#endif
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${uboot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE)	\
	" " MK_STR(CONFIG_SYS_UBOOT_END) ";"		\
	"era " MK_STR(CONFIG_SYS_FLASH_BASE) " "	\
	MK_STR(CONFIG_SYS_UBOOT_END) ";"		\
	"cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	""
#endif

/* ATA configuration */
#define CONFIG_ISO_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT	1
#define CONFIG_ATAPI
#undef CONFIG_LBA48

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2

#define CONFIG_SYS_ATA_BASE_ADDR	0x90000000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0

#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O                            */
#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers           */
#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers                 */

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address  */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x58000
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x13
#ifdef CONFIG_CMD_SPI
#	define CONFIG_SPI_FLASH
#	define CONFIG_SPI_FLASH_STMICRO

#	define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#endif

/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	4

#define CONFIG_SYS_PCI_MEM_BUS		0xA0000000
#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000

#define CONFIG_SYS_PCI_IO_BUS		0xB1000000
#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE		0x01000000

#define CONFIG_SYS_PCI_CFG_BUS		0xB0000000
#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
#endif

/* FPGA - Spartan 2 */
/* experiment
#define CONFIG_FPGA		CONFIG_SYS_SPARTAN3
#define CONFIG_FPGA_COUNT	1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
*/

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE			1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE			256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_HZ			1000

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_BASE1		0x48000000
#define CONFIG_SYS_SDRAM_SIZE		256	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x65311610
#define CONFIG_SYS_SDRAM_CFG2		0x59670000
#define CONFIG_SYS_SDRAM_CTRL		0xEA0B2000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x00010033
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0xAA

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*
 * Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_IS_IN_SPI_FLASH
#	define CONFIG_ENV_SPI_CS		1
#else
#	define CONFIG_ENV_IS_IN_FLASH	1
#endif
#undef CONFIG_ENV_OVERWRITE

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_OFFSET		0x30000
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
#	define CONFIG_ENV_SECT_SIZE	0x2000
#endif
#ifdef CONFIG_SYS_INTEL_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x20000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#	define CONFIG_FLASH_CFI_LEGACY

#ifdef CONFIG_FLASH_CFI_LEGACY
#	define CONFIG_SYS_ATMEL_REGION		4
#	define CONFIG_SYS_ATMEL_TOTALSECT	11
#	define CONFIG_SYS_ATMEL_SECT		{1, 2, 1, 7}
#	define CONFIG_SYS_ATMEL_SECTSZ		{0x4000, 0x2000, 0x8000, 0x10000}
#endif
#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#ifdef CF_STMICRO_BOOT
#	define CONFIG_JFFS2_DEV		"nor1"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH2_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_JFFS2_DEV		"nor1"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH1_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_INTEL_BOOT
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x500000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE		16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
					 CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - CompactFlash and registers
 * CS2 - CPLD
 * CS3 - FPGA
 * CS4 - Available
 * CS5 - Available
 */

#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 /* Atmel Flash */
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00070001
#define CONFIG_SYS_CS0_CTRL		0x00001140
/* Intel Flash */
#define CONFIG_SYS_CS1_BASE		0x00000000
#define CONFIG_SYS_CS1_MASK		0x01FF0001
#define CONFIG_SYS_CS1_CTRL		0x00000D60

#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS0_BASE
#else
/* Intel Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x01FF0001
#define CONFIG_SYS_CS0_CTRL		0x00000D60
 /* Atmel Flash */
#define CONFIG_SYS_CS1_BASE		0x04000000
#define CONFIG_SYS_CS1_MASK		0x00070001
#define CONFIG_SYS_CS1_CTRL		0x00001140

#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS1_BASE
#endif

/* CPLD */
#define CONFIG_SYS_CS2_BASE		0x08000000
#define CONFIG_SYS_CS2_MASK		0x00070001
#define CONFIG_SYS_CS2_CTRL		0x003f1140

/* FPGA */
#define CONFIG_SYS_CS3_BASE		0x09000000
#define CONFIG_SYS_CS3_MASK		0x00070001
#define CONFIG_SYS_CS3_CTRL		0x00000020

#endif				/* _M54455EVB_H */
Commit	Line	Data
8ae158cd TL	1	/*
	2	* Configuation settings for the Freescale MCF54455 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
e8ee8f3a TL	30	#ifndef _M54455EVB_H
e8ee8f3a TL	31	#define _M54455EVB_H
8ae158cd TL	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_MCF5445x /* define processor family */
	38	#define CONFIG_M54455 /* define processor type */
	39	#define CONFIG_M54455EVB /* M54455EVB board */
	40
8ae158cd	41	#define CONFIG_MCFUART
6d0f6bcf	42	#define CONFIG_SYS_UART_PORT (0)
8ae158cd	43	#define CONFIG_BAUDRATE 115200
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
8ae158cd TL	45
	46	#undef CONFIG_WATCHDOG
	47
	48	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	49
	50	/*
	51	* BOOTP options
	52	*/
	53	#define CONFIG_BOOTP_BOOTFILESIZE
	54	#define CONFIG_BOOTP_BOOTPATH
	55	#define CONFIG_BOOTP_GATEWAY
	56	#define CONFIG_BOOTP_HOSTNAME
	57
	58	/* Command line configuration */
	59	#include <config_cmd_default.h>
	60
	61	#define CONFIG_CMD_BOOTD
	62	#define CONFIG_CMD_CACHE
	63	#define CONFIG_CMD_DATE
	64	#define CONFIG_CMD_DHCP
	65	#define CONFIG_CMD_ELF
	66	#define CONFIG_CMD_EXT2
	67	#define CONFIG_CMD_FAT
	68	#define CONFIG_CMD_FLASH
	69	#define CONFIG_CMD_I2C
	70	#define CONFIG_CMD_IDE
	71	#define CONFIG_CMD_JFFS2
	72	#define CONFIG_CMD_MEMORY
	73	#define CONFIG_CMD_MISC
	74	#define CONFIG_CMD_MII
	75	#define CONFIG_CMD_NET
e8ee8f3a	76	#undef CONFIG_CMD_PCI
8ae158cd TL	77	#define CONFIG_CMD_PING
8ae158cd TL	78	#define CONFIG_CMD_REGINFO
a7323bba	79	#define CONFIG_CMD_SPI
922cd751	80	#define CONFIG_CMD_SF
8ae158cd TL	81
	82	#undef CONFIG_CMD_LOADB
	83	#undef CONFIG_CMD_LOADS
	84
	85	/* Network configuration */
	86	#define CONFIG_MCFFEC
	87	#ifdef CONFIG_MCFFEC
0f3ba7e9	88	# define CONFIG_NET_MULTI 1
8ae158cd	89	# define CONFIG_MII 1
0f3ba7e9	90	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	91	# define CONFIG_SYS_DISCOVER_PHY
	92	# define CONFIG_SYS_RX_ETH_BUFFER 8
	93	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	94
	95	# define CONFIG_SYS_FEC0_PINMUX 0
	96	# define CONFIG_SYS_FEC1_PINMUX 0
	97	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	98	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
8ae158cd TL	99	# define MCFFEC_TOUT_LOOP 50000
	100	# define CONFIG_HAS_ETH1
	101
	102	# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	103	# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
	104	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	105	# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
	106	# define CONFIG_ETHPRIME "FEC0"
	107	# define CONFIG_IPADDR 192.162.1.2
	108	# define CONFIG_NETMASK 255.255.255.0
	109	# define CONFIG_SERVERIP 192.162.1.1
	110	# define CONFIG_GATEWAYIP 192.162.1.1
	111	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	112
6d0f6bcf JCPV	113	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	114	# ifndef CONFIG_SYS_DISCOVER_PHY
8ae158cd TL	115	# define FECDUPLEX FULL
	116	# define FECSPEED _100BASET
	117	# else
6d0f6bcf JCPV	118	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	119	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
8ae158cd	120	# endif
6d0f6bcf	121	# endif /* CONFIG_SYS_DISCOVER_PHY */
8ae158cd TL	122	#endif
	123
	124	#define CONFIG_HOSTNAME M54455EVB
6d0f6bcf	125	#ifdef CONFIG_SYS_STMICRO_BOOT
9f751551	126	/* ST Micro serial flash */
6d0f6bcf	127	#define CONFIG_SYS_LOAD_ADDR2 0x40010013
8ae158cd TL	128	#define CONFIG_EXTRA_ENV_SETTINGS \
8ae158cd TL	129	"netdev=eth0\0" \
6d0f6bcf	130	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
9f751551 TL	131	"loadaddr=0x40010000\0" \
	132	"sbfhdr=sbfhdr.bin\0" \
	133	"uboot=u-boot.bin\0" \
	134	"load=tftp ${loadaddr} ${sbfhdr};" \
6d0f6bcf	135	"tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
8ae158cd	136	"upd=run load; run prog\0" \
9f751551 TL	137	"prog=sf probe 0:1 10000 1;" \
	138	"sf erase 0 30000;" \
	139	"sf write ${loadaddr} 0 0x30000;" \
8ae158cd TL	140	"save\0" \
8ae158cd TL	141	""
9f751551 TL	142	#else
9f751551 TL	143	/* Atmel and Intel */
6d0f6bcf JCPV	144	#ifdef CONFIG_SYS_ATMEL_BOOT
	145	# define CONFIG_SYS_UBOOT_END 0x0403FFFF
	146	#elif defined(CONFIG_SYS_INTEL_BOOT)
	147	# define CONFIG_SYS_UBOOT_END 0x3FFFF
9f751551 TL	148	#endif
	149	#define CONFIG_EXTRA_ENV_SETTINGS \
	150	"netdev=eth0\0" \
6d0f6bcf	151	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
9f751551 TL	152	"loadaddr=0x40010000\0" \
	153	"uboot=u-boot.bin\0" \
	154	"load=tftp ${loadaddr} ${uboot}\0" \
	155	"upd=run load; run prog\0" \
6d0f6bcf JCPV	156	"prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \
	157	" " MK_STR(CONFIG_SYS_UBOOT_END) ";" \
	158	"era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \
	159	MK_STR(CONFIG_SYS_UBOOT_END) ";" \
	160	"cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \
9f751551 TL	161	" ${filesize}; save\0" \
	162	""
	163	#endif
8ae158cd TL	164
	165	/* ATA configuration */
	166	#define CONFIG_ISO_PARTITION
	167	#define CONFIG_DOS_PARTITION
	168	#define CONFIG_IDE_RESET 1
	169	#define CONFIG_IDE_PREINIT 1
	170	#define CONFIG_ATAPI
	171	#undef CONFIG_LBA48
	172
6d0f6bcf JCPV	173	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	174	#define CONFIG_SYS_IDE_MAXDEVICE 2
8ae158cd	175
6d0f6bcf JCPV	176	#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
6d0f6bcf JCPV	177	#define CONFIG_SYS_ATA_IDE0_OFFSET 0
8ae158cd	178
6d0f6bcf JCPV	179	#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	180	#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	181	#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	182	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
8ae158cd TL	183
	184	/* Realtime clock */
	185	#define CONFIG_MCFRTC
	186	#undef RTC_DEBUG
6d0f6bcf	187	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
8ae158cd TL	188
	189	/* Timer */
	190	#define CONFIG_MCFTMR
	191	#undef CONFIG_MCFPIT
	192
	193	/* I2c */
	194	#define CONFIG_FSL_I2C
	195	#define CONFIG_HARD_I2C /* I2C with hardware support */
	196	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	197	#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
	198	#define CONFIG_SYS_I2C_SLAVE 0x7F
	199	#define CONFIG_SYS_I2C_OFFSET 0x58000
	200	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
8ae158cd	201
bae61eef	202	/* DSPI and Serial Flash */
ee0a8462	203	#define CONFIG_CF_SPI
bae61eef	204	#define CONFIG_CF_DSPI
a7323bba	205	#define CONFIG_HARD_SPI
6d0f6bcf	206	#define CONFIG_SYS_SBFHDR_SIZE 0x13
a7323bba	207	#ifdef CONFIG_CMD_SPI
922cd751 TL	208	# define CONFIG_SPI_FLASH
	209	# define CONFIG_SPI_FLASH_STMICRO
	210
ee0a8462 TL	211	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	212	DSPI_CTAR_PCSSCK_1CLK \| \
	213	DSPI_CTAR_PASC(0) \| \
	214	DSPI_CTAR_PDT(0) \| \
	215	DSPI_CTAR_CSSCK(0) \| \
	216	DSPI_CTAR_ASC(0) \| \
	217	DSPI_CTAR_DT(1))
a7323bba	218	#endif
bae61eef	219
8ae158cd	220	/* PCI */
e8ee8f3a	221	#ifdef CONFIG_CMD_PCI
8ae158cd	222	#define CONFIG_PCI 1
2e72ad06	223	#define CONFIG_PCI_PNP 1
f33fca22	224	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
2e72ad06	225
6d0f6bcf	226	#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
8ae158cd	227
6d0f6bcf JCPV	228	#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
	229	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
	230	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
8ae158cd	231
6d0f6bcf JCPV	232	#define CONFIG_SYS_PCI_IO_BUS 0xB1000000
	233	#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
	234	#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
8ae158cd	235
6d0f6bcf JCPV	236	#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
	237	#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
	238	#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
e8ee8f3a	239	#endif
8ae158cd TL	240
	241	/* FPGA - Spartan 2 */
	242	/* experiment
6d0f6bcf	243	#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
8ae158cd	244	#define CONFIG_FPGA_COUNT 1
6d0f6bcf JCPV	245	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
6d0f6bcf JCPV	246	#define CONFIG_SYS_FPGA_CHECK_CTRLC
8ae158cd TL	247	*/
	248
	249	/* Input, PCI, Flexbus, and VCO */
	250	#define CONFIG_EXTRA_CLOCK
	251
9f751551	252	#define CONFIG_PRAM 2048 /* 2048 KB */
8ae158cd	253
6d0f6bcf JCPV	254	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	255	#define CONFIG_SYS_LONGHELP /* undef to save memory */
8ae158cd TL	256
8ae158cd TL	257	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	258	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
8ae158cd	259	#else
6d0f6bcf	260	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
8ae158cd	261	#endif
6d0f6bcf JCPV	262	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	263	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	264	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
8ae158cd	265
6d0f6bcf	266	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
8ae158cd	267
6d0f6bcf	268	#define CONFIG_SYS_HZ 1000
8ae158cd	269
6d0f6bcf	270	#define CONFIG_SYS_MBAR 0xFC000000
8ae158cd TL	271
	272	/*
	273	* Low Level Configuration Settings
	274	* (address mappings, register initial values, etc.)
	275	* You should know what you are doing if you make changes here.
	276	*/
	277
	278	/*-----------------------------------------------------------------------
	279	* Definitions for initial stack pointer and data area (in DPRAM)
	280	*/
6d0f6bcf	281	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	282	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf	283	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	284	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
6d0f6bcf	285	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
553f0982	286	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
8ae158cd TL	287
	288	/*-----------------------------------------------------------------------
	289	* Start addresses for the final memory configuration
	290	* (Set up by the startup code)
6d0f6bcf	291	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
8ae158cd	292	*/
6d0f6bcf JCPV	293	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	294	#define CONFIG_SYS_SDRAM_BASE1 0x48000000
	295	#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
	296	#define CONFIG_SYS_SDRAM_CFG1 0x65311610
	297	#define CONFIG_SYS_SDRAM_CFG2 0x59670000
	298	#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
	299	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	300	#define CONFIG_SYS_SDRAM_MODE 0x00010033
	301	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
	302
	303	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	304	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
8ae158cd	305
9f751551	306	#ifdef CONFIG_CF_SBF
14d0a02a	307	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
9f751551	308	#else
6d0f6bcf	309	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
9f751551	310	#endif
6d0f6bcf JCPV	311	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	312	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	313	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
8ae158cd TL	314
	315	/*
	316	* For booting Linux, the board info and command line data
	317	* have to be in the first 8 MB of memory, since this is
	318	* the maximum mapped by the Linux kernel during initialization ??
	319	*/
	320	/* Initial Memory map for Linux */
6d0f6bcf	321	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
8ae158cd	322
9f751551 TL	323	/*
9f751551 TL	324	* Configuration for environment
8ae158cd TL	325	* Environment is embedded in u-boot in the second sector of the flash
8ae158cd TL	326	*/
9f751551	327	#ifdef CONFIG_CF_SBF
0b5099a8	328	# define CONFIG_ENV_IS_IN_SPI_FLASH
0e8d1586	329	# define CONFIG_ENV_SPI_CS 1
9f751551	330	#else
5a1aceb0	331	# define CONFIG_ENV_IS_IN_FLASH 1
9f751551 TL	332	#endif
9f751551 TL	333	#undef CONFIG_ENV_OVERWRITE
8ae158cd TL	334
	335	/*-----------------------------------------------------------------------
	336	* FLASH organization
	337	*/
6d0f6bcf	338	#ifdef CONFIG_SYS_STMICRO_BOOT
ee0a8462 TL	339	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
ee0a8462 TL	340	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
0e8d1586 JCPV	341	# define CONFIG_ENV_OFFSET 0x30000
	342	# define CONFIG_ENV_SIZE 0x2000
	343	# define CONFIG_ENV_SECT_SIZE 0x10000
9f751551	344	#endif
6d0f6bcf JCPV	345	#ifdef CONFIG_SYS_ATMEL_BOOT
	346	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	347	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	348	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
	349	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
0e8d1586	350	# define CONFIG_ENV_SECT_SIZE 0x2000
9f751551	351	#endif
6d0f6bcf JCPV	352	#ifdef CONFIG_SYS_INTEL_BOOT
	353	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	354	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	355	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
	356	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
0e8d1586 JCPV	357	# define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	358	# define CONFIG_ENV_SECT_SIZE 0x20000
8ae158cd TL	359	#endif
8ae158cd TL	360
6d0f6bcf JCPV	361	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	362	#ifdef CONFIG_SYS_FLASH_CFI
8ae158cd	363
00b1883a	364	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff	365	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
6d0f6bcf JCPV	366	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	367	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
	368	# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	369	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	370	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	371	# define CONFIG_SYS_FLASH_CHECKSUM
	372	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
b2d022d1	373	# define CONFIG_FLASH_CFI_LEGACY
8ae158cd	374
b2d022d1	375	#ifdef CONFIG_FLASH_CFI_LEGACY
6d0f6bcf JCPV	376	# define CONFIG_SYS_ATMEL_REGION 4
	377	# define CONFIG_SYS_ATMEL_TOTALSECT 11
	378	# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
	379	# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
bae61eef	380	#endif
8ae158cd TL	381	#endif
	382
	383	/*
	384	* This is setting for JFFS2 support in u-boot.
	385	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	386	*/
9f751551 TL	387	#ifdef CONFIG_CMD_JFFS2
	388	#ifdef CF_STMICRO_BOOT
	389	# define CONFIG_JFFS2_DEV "nor1"
	390	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	391	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
9f751551	392	#endif
6d0f6bcf	393	#ifdef CONFIG_SYS_ATMEL_BOOT
e8ee8f3a	394	# define CONFIG_JFFS2_DEV "nor1"
8ae158cd	395	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	396	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
9f751551	397	#endif
6d0f6bcf	398	#ifdef CONFIG_SYS_INTEL_BOOT
8ae158cd TL	399	# define CONFIG_JFFS2_DEV "nor0"
8ae158cd TL	400	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
6d0f6bcf	401	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
8ae158cd	402	#endif
9f751551	403	#endif
8ae158cd TL	404
	405	/*-----------------------------------------------------------------------
	406	* Cache Configuration
	407	*/
6d0f6bcf	408	#define CONFIG_SYS_CACHELINE_SIZE 16
8ae158cd	409
dd9f054e	410	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	411	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	412	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	413	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	414	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
	415	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	416	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	417	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	418	CF_ACR_EN \| CF_ACR_SM_ALL)
	419	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_IEC \| \
	420	CF_CACR_ICINVA \| CF_CACR_EUSP)
	421	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	422	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	423	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	424
8ae158cd TL	425	/*-----------------------------------------------------------------------
	426	* Memory bank definitions
	427	*/
	428	/*
	429	* CS0 - NOR Flash 1, 2, 4, or 8MB
	430	* CS1 - CompactFlash and registers
	431	* CS2 - CPLD
	432	* CS3 - FPGA
	433	* CS4 - Available
	434	* CS5 - Available
	435	*/
	436
6d0f6bcf	437	#if defined(CONFIG_SYS_ATMEL_BOOT) \|\| defined(CONFIG_SYS_STMICRO_BOOT)
8ae158cd	438	/* Atmel Flash */
6d0f6bcf JCPV	439	#define CONFIG_SYS_CS0_BASE 0x04000000
	440	#define CONFIG_SYS_CS0_MASK 0x00070001
	441	#define CONFIG_SYS_CS0_CTRL 0x00001140
8ae158cd	442	/* Intel Flash */
6d0f6bcf JCPV	443	#define CONFIG_SYS_CS1_BASE 0x00000000
	444	#define CONFIG_SYS_CS1_MASK 0x01FF0001
	445	#define CONFIG_SYS_CS1_CTRL 0x00000D60
8ae158cd	446
6d0f6bcf	447	#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
8ae158cd TL	448	#else
8ae158cd TL	449	/* Intel Flash */
6d0f6bcf JCPV	450	#define CONFIG_SYS_CS0_BASE 0x00000000
	451	#define CONFIG_SYS_CS0_MASK 0x01FF0001
	452	#define CONFIG_SYS_CS0_CTRL 0x00000D60
8ae158cd	453	/* Atmel Flash */
6d0f6bcf JCPV	454	#define CONFIG_SYS_CS1_BASE 0x04000000
	455	#define CONFIG_SYS_CS1_MASK 0x00070001
	456	#define CONFIG_SYS_CS1_CTRL 0x00001140
8ae158cd	457
6d0f6bcf	458	#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
8ae158cd TL	459	#endif
	460
	461	/* CPLD */
6d0f6bcf JCPV	462	#define CONFIG_SYS_CS2_BASE 0x08000000
	463	#define CONFIG_SYS_CS2_MASK 0x00070001
	464	#define CONFIG_SYS_CS2_CTRL 0x003f1140
8ae158cd TL	465
8ae158cd TL	466	/* FPGA */
6d0f6bcf JCPV	467	#define CONFIG_SYS_CS3_BASE 0x09000000
	468	#define CONFIG_SYS_CS3_MASK 0x00070001
	469	#define CONFIG_SYS_CS3_CTRL 0x00000020
8ae158cd	470
e8ee8f3a	471	#endif /* _M54455EVB_H */