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Commit | Line | Data |
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7d393aed WD |
1 | /* |
2 | * (C) Copyright 2001, 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
7d393aed WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /*********************************************************** | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | ***********************************************************/ | |
19 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
2ae18241 WD |
20 | |
21 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 | |
22 | ||
f3e0de60 WD |
23 | /*********************************************************** |
24 | * Note that it may also be a MIP405T board which is a subset of the | |
25 | * MIP405 | |
26 | ***********************************************************/ | |
27 | /*********************************************************** | |
28 | * WARNING: | |
29 | * CONFIG_BOOT_PCI is only used for first boot-up and should | |
30 | * NOT be enabled for production bootloader | |
31 | ***********************************************************/ | |
8bde7f77 | 32 | /*#define CONFIG_BOOT_PCI 1*/ |
7d393aed WD |
33 | /*********************************************************** |
34 | * Clock | |
35 | ***********************************************************/ | |
36 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ | |
37 | ||
659e2f67 JL |
38 | /* |
39 | * BOOTP options | |
40 | */ | |
41 | #define CONFIG_BOOTP_BOOTFILESIZE | |
42 | #define CONFIG_BOOTP_BOOTPATH | |
43 | #define CONFIG_BOOTP_GATEWAY | |
44 | #define CONFIG_BOOTP_HOSTNAME | |
45 | ||
8353e139 JL |
46 | /* |
47 | * Command line configuration. | |
48 | */ | |
8353e139 | 49 | #define CONFIG_CMD_DATE |
8353e139 | 50 | #define CONFIG_CMD_EEPROM |
8353e139 JL |
51 | #define CONFIG_CMD_IDE |
52 | #define CONFIG_CMD_IRQ | |
53 | #define CONFIG_CMD_JFFS2 | |
8353e139 | 54 | #define CONFIG_CMD_PCI |
8353e139 JL |
55 | #define CONFIG_CMD_REGINFO |
56 | #define CONFIG_CMD_SAVES | |
57 | #define CONFIG_CMD_BSP | |
f3e0de60 | 58 | |
7d393aed WD |
59 | /************************************************************** |
60 | * I2C Stuff: | |
61 | * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address | |
62 | * 0x53. | |
63 | * The Atmel EEPROM uses 16Bit addressing. | |
64 | ***************************************************************/ | |
65 | ||
880540de DE |
66 | #define CONFIG_SYS_I2C |
67 | #define CONFIG_SYS_I2C_PPC4XX | |
68 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
69 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 50000 | |
70 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
7d393aed | 71 | |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ |
73 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ | |
7d393aed | 74 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
75 | #undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
76 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ | |
7d393aed WD |
77 | /* 64 byte page write mode using*/ |
78 | /* last 6 bits of the address */ | |
6d0f6bcf | 79 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
7d393aed | 80 | |
bb1f8b4f | 81 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
82 | #define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ |
83 | #define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ | |
7d393aed WD |
84 | |
85 | /*************************************************************** | |
86 | * Definitions for Serial Presence Detect EEPROM address | |
87 | * (to get SDRAM settings) | |
88 | ***************************************************************/ | |
f3e0de60 | 89 | /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 |
53677ef1 | 90 | #define SDRAM_EEPROM_READ_ADDRESS 0xA1 |
f3e0de60 | 91 | */ |
7d393aed WD |
92 | /************************************************************** |
93 | * Environment definitions | |
94 | **************************************************************/ | |
95 | #define CONFIG_BAUDRATE 9600 /* STD Baudrate */ | |
7d393aed | 96 | /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ |
2afbe4ed | 97 | /* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ |
7d393aed | 98 | |
3e38691e | 99 | #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ |
7d393aed WD |
100 | #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ |
101 | ||
102 | #define CONFIG_IPADDR 10.0.0.100 | |
103 | #define CONFIG_SERVERIP 10.0.0.1 | |
104 | #define CONFIG_PREBOOT | |
7d393aed WD |
105 | /*************************************************************** |
106 | * defines if an overwrite_console function exists | |
107 | *************************************************************/ | |
7d393aed WD |
108 | /*************************************************************** |
109 | * defines if the overwrite_console should be stored in the | |
110 | * environment | |
111 | **************************************************************/ | |
7d393aed WD |
112 | |
113 | /************************************************************** | |
114 | * loads config | |
115 | *************************************************************/ | |
116 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 117 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
7d393aed WD |
118 | |
119 | #define CONFIG_MISC_INIT_R | |
120 | /*********************************************************** | |
121 | * Miscellaneous configurable options | |
122 | **********************************************************/ | |
6d0f6bcf | 123 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
8353e139 | 124 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 125 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
7d393aed | 126 | #else |
6d0f6bcf | 127 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
7d393aed | 128 | #endif |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
130 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
131 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
7d393aed | 132 | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ |
134 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ | |
7d393aed | 135 | |
550650dd | 136 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
550650dd SR |
137 | #define CONFIG_SYS_NS16550_SERIAL |
138 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
139 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
140 | ||
6d0f6bcf JCPV |
141 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
142 | #define CONFIG_SYS_BASE_BAUD 916667 | |
7d393aed WD |
143 | |
144 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 145 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
7d393aed WD |
146 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
147 | 57600, 115200, 230400, 460800, 921600 } | |
148 | ||
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ |
150 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
7d393aed | 151 | |
7d393aed WD |
152 | /*----------------------------------------------------------------------- |
153 | * PCI stuff | |
154 | *----------------------------------------------------------------------- | |
155 | */ | |
156 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ | |
157 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
158 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
159 | ||
842033e6 | 160 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
7d393aed WD |
161 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ |
162 | #define CONFIG_PCI_PNP /* pci plug-and-play */ | |
163 | /* resource configuration */ | |
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
165 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ | |
166 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
167 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
168 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
169 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
170 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
171 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ | |
7d393aed WD |
172 | |
173 | /*----------------------------------------------------------------------- | |
174 | * Start addresses for the final memory configuration | |
175 | * (Set up by the startup code) | |
6d0f6bcf | 176 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
7d393aed | 177 | */ |
6d0f6bcf JCPV |
178 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
179 | #define CONFIG_SYS_FLASH_BASE 0xFFF80000 | |
180 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
181 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ | |
182 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ | |
7d393aed WD |
183 | |
184 | /* | |
185 | * For booting Linux, the board info and command line data | |
186 | * have to be in the first 8 MB of memory, since this is | |
187 | * the maximum mapped by the Linux kernel during initialization. | |
188 | */ | |
6d0f6bcf | 189 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
7d393aed WD |
190 | /*----------------------------------------------------------------------- |
191 | * FLASH organization | |
192 | */ | |
39441b35 DM |
193 | #define CONFIG_SYS_UPDATE_FLASH_SIZE |
194 | #define CONFIG_SYS_FLASH_PROTECTION | |
195 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
7d393aed | 196 | |
39441b35 DM |
197 | #define CONFIG_SYS_FLASH_CFI |
198 | #define CONFIG_FLASH_CFI_DRIVER | |
199 | ||
200 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
201 | ||
202 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
203 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
7d393aed | 204 | |
700a0c64 WD |
205 | /* |
206 | * JFFS2 partitions | |
207 | * | |
208 | */ | |
209 | /* No command line, one static partition, whole device */ | |
68d7d651 | 210 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
211 | #define CONFIG_JFFS2_DEV "nor0" |
212 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
213 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
214 | ||
215 | /* mtdparts command line support */ | |
216 | /* Note: fake mtd_id used, no linux mtd map file */ | |
217 | /* | |
68d7d651 | 218 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
219 | #define MTDIDS_DEFAULT "nor0=mip405-0" |
220 | #define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" | |
221 | */ | |
7d393aed | 222 | |
63e73c9a WD |
223 | /*----------------------------------------------------------------------- |
224 | * Logbuffer Configuration | |
225 | */ | |
53677ef1 | 226 | #undef CONFIG_LOGBUFFER /* supported but not enabled */ |
63e73c9a WD |
227 | /*----------------------------------------------------------------------- |
228 | * Bootcountlimit Configuration | |
229 | */ | |
230 | #undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */ | |
231 | ||
232 | /*----------------------------------------------------------------------- | |
233 | * POST Configuration | |
234 | */ | |
235 | #if 0 /* enable this if POST is desired (is supported but not enabled) */ | |
6d0f6bcf JCPV |
236 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
237 | CONFIG_SYS_POST_CPU | \ | |
238 | CONFIG_SYS_POST_RTC | \ | |
239 | CONFIG_SYS_POST_I2C) | |
63e73c9a WD |
240 | |
241 | #endif | |
7d393aed WD |
242 | /* |
243 | * Init Memory Controller: | |
244 | */ | |
7205e407 WD |
245 | #define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ |
246 | #define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ | |
247 | /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ | |
248 | #define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ | |
7d393aed | 249 | |
c837dcb1 | 250 | #define CONFIG_BOARD_EARLY_INIT_F 1 |
39441b35 | 251 | #define CONFIG_BOARD_EARLY_INIT_R |
7d393aed WD |
252 | |
253 | /* Peripheral Bus Mapping */ | |
254 | #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ | |
255 | #define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/ | |
256 | #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ | |
257 | ||
258 | #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 | |
53677ef1 | 259 | #define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 |
7d393aed | 260 | |
7d393aed WD |
261 | /*----------------------------------------------------------------------- |
262 | * Definitions for initial stack pointer and data area (in On Chip SRAM) | |
263 | */ | |
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
265 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 | |
266 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
267 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ | |
553f0982 | 268 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */ |
25ddd1fb | 269 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
63e73c9a | 270 | /* reserve some memory for POST and BOOT limit info */ |
6d0f6bcf | 271 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) |
63e73c9a | 272 | |
63e73c9a | 273 | #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ |
6d0f6bcf | 274 | #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12) |
63e73c9a | 275 | #endif |
7d393aed | 276 | |
7d393aed WD |
277 | /*********************************************************************** |
278 | * External peripheral base address | |
279 | ***********************************************************************/ | |
6d0f6bcf | 280 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 |
7d393aed WD |
281 | |
282 | /*********************************************************************** | |
283 | * Last Stage Init | |
284 | ***********************************************************************/ | |
285 | #define CONFIG_LAST_STAGE_INIT | |
286 | /************************************************************ | |
287 | * Ethernet Stuff | |
288 | ***********************************************************/ | |
96e21f86 | 289 | #define CONFIG_PPC4xx_EMAC |
7d393aed WD |
290 | #define CONFIG_MII 1 /* MII PHY management */ |
291 | #define CONFIG_PHY_ADDR 1 /* PHY address */ | |
63e73c9a WD |
292 | #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ |
293 | #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ | |
7d393aed WD |
294 | /************************************************************ |
295 | * RTC | |
296 | ***********************************************************/ | |
297 | #define CONFIG_RTC_MC146818 | |
298 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
299 | ||
300 | /************************************************************ | |
301 | * IDE/ATA stuff | |
302 | ************************************************************/ | |
adf32adb | 303 | #if defined(CONFIG_TARGET_MIP405T) |
6d0f6bcf | 304 | #define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ |
f3e0de60 | 305 | #else |
6d0f6bcf | 306 | #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ |
f3e0de60 WD |
307 | #endif |
308 | ||
6d0f6bcf | 309 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ |
7d393aed | 310 | |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */ |
312 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ | |
313 | #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ | |
314 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ | |
315 | #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ | |
316 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ | |
7d393aed WD |
317 | |
318 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ | |
319 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
320 | #define CONFIG_IDE_RESET /* reset for ide supported... */ | |
321 | #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ | |
7205e407 | 322 | #define CONFIG_SUPPORT_VFAT |
7d393aed WD |
323 | /************************************************************ |
324 | * ATAPI support (experimental) | |
325 | ************************************************************/ | |
326 | #define CONFIG_ATAPI /* enable ATAPI Support */ | |
327 | ||
7d393aed WD |
328 | /************************************************************ |
329 | * DISK Partition support | |
330 | ************************************************************/ | |
331 | #define CONFIG_DOS_PARTITION | |
332 | #define CONFIG_MAC_PARTITION | |
333 | #define CONFIG_ISO_PARTITION /* Experimental */ | |
334 | ||
7d393aed WD |
335 | /************************************************************ |
336 | * Video support | |
337 | ************************************************************/ | |
7d393aed | 338 | #define CONFIG_VIDEO_LOGO |
7d393aed WD |
339 | #undef CONFIG_VIDEO_ONBOARD |
340 | /************************************************************ | |
341 | * USB support EXPERIMENTAL | |
342 | ************************************************************/ | |
adf32adb | 343 | #if !defined(CONFIG_TARGET_MIP405T) |
7d393aed | 344 | #define CONFIG_USB_UHCI |
7d393aed WD |
345 | |
346 | /* Enable needed helper functions */ | |
f3e0de60 | 347 | #endif |
7d393aed WD |
348 | /************************************************************ |
349 | * Debug support | |
350 | ************************************************************/ | |
8353e139 | 351 | #if defined(CONFIG_CMD_KGDB) |
7d393aed | 352 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
7d393aed WD |
353 | #endif |
354 | ||
a2663ea4 WD |
355 | /************************************************************ |
356 | * support BZIP2 compression | |
357 | ************************************************************/ | |
358 | #define CONFIG_BZIP2 1 | |
359 | ||
7d393aed | 360 | #endif /* __CONFIG_H */ |