[people/ms/u-boot.git] / include / configs / MOUSSE.h

/*
 * (C) Copyright 2000, 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2001
 * James F. Dougherty (jfd@cs.stanford.edu)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 *
 * Configuration settings for the MOUSSE board.
 * See also: http://www.vooha.com/
 *
 */

/* ------------------------------------------------------------------------- */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC824X      1
#define CONFIG_MPC8240      1
#define CONFIG_MOUSSE       1
#define CONFIG_SYS_ADDR_MAP_B      1
#define CONFIG_CONS_INDEX   1
#define CONFIG_BAUDRATE     9600
#if 1
#define CONFIG_BOOTCOMMAND  "tftp 100000 vmlinux.img;bootm"    /* autoboot command */
#else
#define CONFIG_BOOTCOMMAND  "bootm ffe10000"
#endif
#define CONFIG_BOOTARGS      "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
#define CONFIG_BOOTDELAY     3


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE


#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ETH_ADDR      "00:10:18:10:00:06"

#define CONFIG_DOS_PARTITION  1 /* MSDOS bootable partitiion support */

#include "../board/mousse/mousse.h"

/*
 * Miscellaneous configurable options
 */
#undef CONFIG_SYS_LONGHELP                /* undef to save memory     */
#define CONFIG_SYS_PROMPT      "=>"  /* Monitor Command Prompt   */
#define CONFIG_SYS_CBSIZE      256        /* Console I/O Buffer Size  */
#define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS     8           /* Max number of command args   */

#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size    */
#define CONFIG_SYS_LOAD_ADDR   0x00100000  /* Default load address         */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE      0x00000000

#ifdef DEBUG
#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_SDRAM_BASE
#else
#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_FLASH_BASE
#endif

#ifdef DEBUG
#define CONFIG_SYS_MONITOR_LEN     (4 << 20)	/* lots of mem ... */
#else
#define CONFIG_SYS_MONITOR_LEN     (512 << 10)	/* 512K PLCC bootrom */
#endif
#define CONFIG_SYS_MALLOC_LEN      (2*(4096 << 10))    /* 2*4096kB for malloc()  */

#define CONFIG_SYS_MEMTEST_START   0x00004000	/* memtest works on      */
#define CONFIG_SYS_MEMTEST_END     0x02000000	/* 0 ... 32 MB in DRAM   */


#define CONFIG_SYS_EUMB_ADDR       0xFC000000

#define CONFIG_SYS_ISA_MEM         0xFD000000
#define CONFIG_SYS_ISA_IO          0xFE000000

#define CONFIG_SYS_FLASH_BASE      0xFFF00000
#define CONFIG_SYS_FLASH_SIZE      ((uint)(512 * 1024))
#define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
#define FLASH_BASE0_PRELIM  0xFFF00000  /* 512K PLCC FLASH/AM29F040*/
#define FLASH_BASE0_SIZE    0x80000     /* 512K */
#define FLASH_BASE1_PRELIM  0xFFE10000  /* AMD 29LV160DB
					   1MB - 64K FLASH0 SEG =960K
					   (size=0xf0000)*/

#define CONFIG_SYS_BAUDRATE_TABLE  { 9600, 19200, 38400, 57600, 115200 }

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL

#define CONFIG_SYS_NS16550_REG_SIZE	1

#define CONFIG_SYS_NS16550_CLK		18432000

#define CONFIG_SYS_NS16550_COM1	0xFFE08080

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
#define CONFIG_SYS_INIT_RAM_END   0x2F00  /* End of used area in DPRAM  */
#define CONFIG_SYS_GBL_DATA_SIZE  64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * For the detail description refer to the MPC8240 user's manual.
 */

#define CONFIG_SYS_CLK_FREQ  33000000	/* external frequency to pll */
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER  2
#define CONFIG_SYS_HZ               1000

#define CONFIG_SYS_ETH_DEV_FN       0x00
#define CONFIG_SYS_ETH_IOBASE       0x00104000


	/* Bit-field values for MCCR1.
	 */
#define CONFIG_SYS_ROMNAL          8
#define CONFIG_SYS_ROMFAL          8

	/* Bit-field values for MCCR2.
	 */
#define CONFIG_SYS_REFINT          0xf5     /* Refresh interval               */

	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	 */
#define CONFIG_SYS_BSTOPRE         0x79

#ifdef INCLUDE_ECC
#define USE_ECC				1
#else /* INCLUDE_ECC */
#define USE_ECC				0
#endif /* INCLUDE_ECC */


	/* Bit-field values for MCCR3.
	 */
#define CONFIG_SYS_REFREC          8       /* Refresh to activate interval   */
#define CONFIG_SYS_RDLAT           (4+USE_ECC)   /* Data latancy from read command */

	/* Bit-field values for MCCR4.
	 */
#define CONFIG_SYS_PRETOACT        3       /* Precharge to activate interval */
#define CONFIG_SYS_ACTTOPRE        5       /* Activate to Precharge interval */
#define CONFIG_SYS_SDMODE_CAS_LAT  3       /* SDMODE CAS latancy             */
#define CONFIG_SYS_SDMODE_WRAP     0       /* SDMODE wrap type               */
#define CONFIG_SYS_SDMODE_BURSTLEN 2       /* SDMODE Burst length            */
#define CONFIG_SYS_ACTORW          2
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC)

/* Memory bank settings.
 * Only bits 20-29 are actually used from these vales to set the
 * start/end addresses. The upper two bits will always be 0, and the lower
 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 * address. Refer to the MPC8240 book.
 */
#define CONFIG_SYS_RAM_SIZE        0x04000000  /* 64MB */


#define CONFIG_SYS_BANK0_START     0x00000000
#define CONFIG_SYS_BANK0_END       (CONFIG_SYS_RAM_SIZE - 1)
#define CONFIG_SYS_BANK0_ENABLE    1
#define CONFIG_SYS_BANK1_START     0x3ff00000
#define CONFIG_SYS_BANK1_END       0x3fffffff
#define CONFIG_SYS_BANK1_ENABLE    0
#define CONFIG_SYS_BANK2_START     0x3ff00000
#define CONFIG_SYS_BANK2_END       0x3fffffff
#define CONFIG_SYS_BANK2_ENABLE    0
#define CONFIG_SYS_BANK3_START     0x3ff00000
#define CONFIG_SYS_BANK3_END       0x3fffffff
#define CONFIG_SYS_BANK3_ENABLE    0
#define CONFIG_SYS_BANK4_START     0x3ff00000
#define CONFIG_SYS_BANK4_END       0x3fffffff
#define CONFIG_SYS_BANK4_ENABLE    0
#define CONFIG_SYS_BANK5_START     0x3ff00000
#define CONFIG_SYS_BANK5_END       0x3fffffff
#define CONFIG_SYS_BANK5_ENABLE    0
#define CONFIG_SYS_BANK6_START     0x3ff00000
#define CONFIG_SYS_BANK6_END       0x3fffffff
#define CONFIG_SYS_BANK6_ENABLE    0
#define CONFIG_SYS_BANK7_START     0x3ff00000
#define CONFIG_SYS_BANK7_END       0x3fffffff
#define CONFIG_SYS_BANK7_ENABLE    0

#define CONFIG_SYS_ODCR            0x7f


#define CONFIG_SYS_PGMAX           0x32 /* how long the 8240 reatins the currently accessed page in memory
				    see 8240 book for details*/
#define PCI_MEM_SPACE1_START	0x80000000
#define PCI_MEM_SPACE2_START	0xfd000000

/* IBAT/DBAT Configuration */
/* Ram: 64MB, starts at address-0, r/w instruction/data */
#define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT0L      CONFIG_SYS_IBAT0L

/* MPLD/Port-X I/O Space : data and instruction read/write,  cache-inhibit */
#define CONFIG_SYS_IBAT1U      (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
#if 0
#define CONFIG_SYS_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10  | BATL_MEMCOHERENCE |\
			 BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
#else
#define CONFIG_SYS_IBAT1L      (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
#endif
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L

/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
#define CONFIG_SYS_IBAT2U	(PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT2L	(PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
#define CONFIG_SYS_DBAT2U      CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT2L      CONFIG_SYS_IBAT2L

/* PCI Memory region 2: PCI Devices in 0xFD space */
#define CONFIG_SYS_IBAT3U	(PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT3L	(PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
#define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT3L      CONFIG_SYS_IBAT3L


/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ       (8 << 20)   /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS     3       /* Max number of flash banks         */
#define CONFIG_SYS_MAX_FLASH_SECT      64      /* Max number of sectors in one bank */

#define CONFIG_SYS_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)   */
#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)   */

#if 0
#define	CONFIG_ENV_IS_IN_FLASH	    1
#define CONFIG_ENV_OFFSET          0x8000  /* Offset of the Environment Sector	*/
#define CONFIG_ENV_SIZE            0x4000  /* Size of the Environment Sector    */
#else
#define CONFIG_ENV_IS_IN_NVRAM          1
#define CONFIG_ENV_ADDR            NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
#define CONFIG_ENV_OFFSET          CONFIG_ENV_ADDR
#define CONFIG_ENV_SIZE            NV_U_BOOT_ENV_SIZE /* 2K */
#endif
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE  16


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM           0x02    /* Software reboot                  */

/* Localizations */
#if 0
#define CONFIG_ETHADDR          0:0:0:0:1:d
#define CONFIG_IPADDR           172.16.40.113
#define CONFIG_SERVERIP         172.16.40.111
#else
#define CONFIG_ETHADDR          0:0:0:0:1:d
#define CONFIG_IPADDR           209.128.93.138
#define CONFIG_SERVERIP         209.128.93.133
#endif

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_PCI			/* include pci support			*/
#undef CONFIG_PCI_PNP

#define CONFIG_NET_MULTI		/* Multi ethernet cards support		*/

#define CONFIG_TULIP

#endif  /* __CONFIG_H */
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* (C) Copyright 2000, 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2001
	6	* James F. Dougherty (jfd@cs.stanford.edu)
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	/*
	28	*
	29	* Configuration settings for the MOUSSE board.
	30	* See also: http://www.vooha.com/
	31	*
	32	*/
	33
	34	/* ------------------------------------------------------------------------- */
	35
	36	/*
	37	* board/config.h - configuration options, board specific
	38	*/
	39
	40	#ifndef __CONFIG_H
	41	#define __CONFIG_H
	42
	43	/*
	44	* High Level Configuration Options
	45	* (easy to change)
	46	*/
	47
	48	#define CONFIG_MPC824X 1
	49	#define CONFIG_MPC8240 1
	50	#define CONFIG_MOUSSE 1
6d0f6bcf	51	#define CONFIG_SYS_ADDR_MAP_B 1
fe8c2806 WD	52	#define CONFIG_CONS_INDEX 1
	53	#define CONFIG_BAUDRATE 9600
	54	#if 1
	55	#define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */
	56	#else
	57	#define CONFIG_BOOTCOMMAND "bootm ffe10000"
	58	#endif
	59	#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
	60	#define CONFIG_BOOTDELAY 3
8353e139 JL	61
8353e139 JL	62
659e2f67 JL	63	/*
	64	* BOOTP options
	65	*/
	66	#define CONFIG_BOOTP_BOOTFILESIZE
	67	#define CONFIG_BOOTP_BOOTPATH
	68	#define CONFIG_BOOTP_GATEWAY
	69	#define CONFIG_BOOTP_HOSTNAME
	70
	71
8353e139 JL	72	/*
	73	* Command line configuration.
	74	*/
	75	#include <config_cmd_default.h>
	76
	77	#define CONFIG_CMD_ASKENV
	78	#define CONFIG_CMD_DATE
	79
	80
fe8c2806 WD	81	#define CONFIG_ENV_OVERWRITE 1
	82	#define CONFIG_ETH_ADDR "00:10:18:10:00:06"
	83
	84	#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */
8353e139	85
fe8c2806 WD	86	#include "../board/mousse/mousse.h"
	87
	88	/*
	89	* Miscellaneous configurable options
	90	*/
6d0f6bcf JCPV	91	#undef CONFIG_SYS_LONGHELP /* undef to save memory */
	92	#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
	93	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	94	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	95	#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
fe8c2806	96
6d0f6bcf JCPV	97	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
6d0f6bcf JCPV	98	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
fe8c2806 WD	99
	100	/*-----------------------------------------------------------------------
	101	* Start addresses for the final memory configuration
	102	* (Set up by the startup code)
6d0f6bcf	103	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
fe8c2806	104	*/
6d0f6bcf	105	#define CONFIG_SYS_SDRAM_BASE 0x00000000
fe8c2806 WD	106
fe8c2806 WD	107	#ifdef DEBUG
6d0f6bcf	108	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_SDRAM_BASE
fe8c2806	109	#else
6d0f6bcf	110	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
fe8c2806 WD	111	#endif
	112
	113	#ifdef DEBUG
6d0f6bcf	114	#define CONFIG_SYS_MONITOR_LEN (4 << 20) /* lots of mem ... */
fe8c2806	115	#else
6d0f6bcf	116	#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */
fe8c2806	117	#endif
6d0f6bcf	118	#define CONFIG_SYS_MALLOC_LEN (2(4096 << 10)) / 24096kB for malloc() /
fe8c2806	119
6d0f6bcf JCPV	120	#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
6d0f6bcf JCPV	121	#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
fe8c2806 WD	122
fe8c2806 WD	123
6d0f6bcf	124	#define CONFIG_SYS_EUMB_ADDR 0xFC000000
fe8c2806	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_ISA_MEM 0xFD000000
6d0f6bcf JCPV	127	#define CONFIG_SYS_ISA_IO 0xFE000000
fe8c2806	128
6d0f6bcf JCPV	129	#define CONFIG_SYS_FLASH_BASE 0xFFF00000
	130	#define CONFIG_SYS_FLASH_SIZE ((uint)(512 * 1024))
	131	#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
fe8c2806 WD	132	#define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/
	133	#define FLASH_BASE0_SIZE 0x80000 /* 512K */
	134	#define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB
	135	1MB - 64K FLASH0 SEG =960K
	136	(size=0xf0000)*/
	137
6d0f6bcf	138	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
fe8c2806 WD	139
	140	/*
	141	* NS16550 Configuration
	142	*/
6d0f6bcf JCPV	143	#define CONFIG_SYS_NS16550
6d0f6bcf JCPV	144	#define CONFIG_SYS_NS16550_SERIAL
fe8c2806	145
6d0f6bcf	146	#define CONFIG_SYS_NS16550_REG_SIZE 1
fe8c2806	147
6d0f6bcf	148	#define CONFIG_SYS_NS16550_CLK 18432000
fe8c2806	149
6d0f6bcf	150	#define CONFIG_SYS_NS16550_COM1 0xFFE08080
fe8c2806 WD	151
	152	/*-----------------------------------------------------------------------
	153	* Definitions for initial stack pointer and data area (in DPRAM)
	154	*/
6d0f6bcf JCPV	155	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
	156	#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	157	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	158	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	159	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
fe8c2806 WD	160
	161	/*
	162	* Low Level Configuration Settings
	163	* (address mappings, register initial values, etc.)
	164	* You should know what you are doing if you make changes here.
	165	* For the detail description refer to the MPC8240 user's manual.
	166	*/
	167
	168	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	169	#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
6d0f6bcf	170	#define CONFIG_SYS_HZ 1000
fe8c2806	171
6d0f6bcf JCPV	172	#define CONFIG_SYS_ETH_DEV_FN 0x00
6d0f6bcf JCPV	173	#define CONFIG_SYS_ETH_IOBASE 0x00104000
fe8c2806 WD	174
	175
	176	/* Bit-field values for MCCR1.
	177	*/
6d0f6bcf JCPV	178	#define CONFIG_SYS_ROMNAL 8
6d0f6bcf JCPV	179	#define CONFIG_SYS_ROMFAL 8
fe8c2806 WD	180
	181	/* Bit-field values for MCCR2.
	182	*/
6d0f6bcf	183	#define CONFIG_SYS_REFINT 0xf5 /* Refresh interval */
fe8c2806 WD	184
	185	/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
	186	*/
6d0f6bcf	187	#define CONFIG_SYS_BSTOPRE 0x79
fe8c2806 WD	188
	189	#ifdef INCLUDE_ECC
	190	#define USE_ECC 1
	191	#else /* INCLUDE_ECC */
	192	#define USE_ECC 0
	193	#endif /* INCLUDE_ECC */
	194
	195
	196	/* Bit-field values for MCCR3.
	197	*/
6d0f6bcf JCPV	198	#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
6d0f6bcf JCPV	199	#define CONFIG_SYS_RDLAT (4+USE_ECC) /* Data latancy from read command */
fe8c2806 WD	200
	201	/* Bit-field values for MCCR4.
	202	*/
6d0f6bcf JCPV	203	#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
	204	#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
	205	#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
	206	#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
	207	#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
	208	#define CONFIG_SYS_ACTORW 2
	209	#define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC)
fe8c2806 WD	210
	211	/* Memory bank settings.
	212	* Only bits 20-29 are actually used from these vales to set the
	213	* start/end addresses. The upper two bits will always be 0, and the lower
	214	* 20 bits will be 0x00000 for a start address, or 0xfffff for an end
	215	* address. Refer to the MPC8240 book.
	216	*/
6d0f6bcf JCPV	217	#define CONFIG_SYS_RAM_SIZE 0x04000000 /* 64MB */
	218
	219
	220	#define CONFIG_SYS_BANK0_START 0x00000000
	221	#define CONFIG_SYS_BANK0_END (CONFIG_SYS_RAM_SIZE - 1)
	222	#define CONFIG_SYS_BANK0_ENABLE 1
	223	#define CONFIG_SYS_BANK1_START 0x3ff00000
	224	#define CONFIG_SYS_BANK1_END 0x3fffffff
	225	#define CONFIG_SYS_BANK1_ENABLE 0
	226	#define CONFIG_SYS_BANK2_START 0x3ff00000
	227	#define CONFIG_SYS_BANK2_END 0x3fffffff
	228	#define CONFIG_SYS_BANK2_ENABLE 0
	229	#define CONFIG_SYS_BANK3_START 0x3ff00000
	230	#define CONFIG_SYS_BANK3_END 0x3fffffff
	231	#define CONFIG_SYS_BANK3_ENABLE 0
	232	#define CONFIG_SYS_BANK4_START 0x3ff00000
	233	#define CONFIG_SYS_BANK4_END 0x3fffffff
	234	#define CONFIG_SYS_BANK4_ENABLE 0
	235	#define CONFIG_SYS_BANK5_START 0x3ff00000
	236	#define CONFIG_SYS_BANK5_END 0x3fffffff
	237	#define CONFIG_SYS_BANK5_ENABLE 0
	238	#define CONFIG_SYS_BANK6_START 0x3ff00000
	239	#define CONFIG_SYS_BANK6_END 0x3fffffff
	240	#define CONFIG_SYS_BANK6_ENABLE 0
	241	#define CONFIG_SYS_BANK7_START 0x3ff00000
	242	#define CONFIG_SYS_BANK7_END 0x3fffffff
	243	#define CONFIG_SYS_BANK7_ENABLE 0
	244
	245	#define CONFIG_SYS_ODCR 0x7f
	246
	247
	248	#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory
8bde7f77	249	see 8240 book for details*/
fe8c2806 WD	250	#define PCI_MEM_SPACE1_START 0x80000000
	251	#define PCI_MEM_SPACE2_START 0xfd000000
	252
	253	/* IBAT/DBAT Configuration */
	254	/* Ram: 64MB, starts at address-0, r/w instruction/data */
6d0f6bcf JCPV	255	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_64M \| BATU_VS \| BATU_VP)
	256	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE)
	257	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	258	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
fe8c2806 WD	259
fe8c2806 WD	260	/* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */
6d0f6bcf	261	#define CONFIG_SYS_IBAT1U (PORTX_DEV_BASE \| BATU_BL_128M \| BATU_VS \| BATU_VP)
fe8c2806	262	#if 0
6d0f6bcf	263	#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE \| BATL_PP_10 \| BATL_MEMCOHERENCE \|\
fe8c2806 WD	264	BATL_WRITETHROUGH \| BATL_CACHEINHIBIT)
fe8c2806 WD	265	#else
6d0f6bcf	266	#define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE \| BATL_PP_10 \|BATL_CACHEINHIBIT)
fe8c2806	267	#endif
6d0f6bcf JCPV	268	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
6d0f6bcf JCPV	269	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
fe8c2806 WD	270
fe8c2806 WD	271	/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
6d0f6bcf JCPV	272	#define CONFIG_SYS_IBAT2U (PCI_MEM_SPACE1_START\|BATU_BL_16M \| BATU_VS \| BATU_VP)
	273	#define CONFIG_SYS_IBAT2L (PCI_MEM_SPACE1_START\|BATL_PP_10 \| BATL_GUARDEDSTORAGE\|BATL_CACHEINHIBIT)
	274	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	275	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
fe8c2806 WD	276
fe8c2806 WD	277	/* PCI Memory region 2: PCI Devices in 0xFD space */
6d0f6bcf JCPV	278	#define CONFIG_SYS_IBAT3U (PCI_MEM_SPACE2_START\|BATU_BL_16M \| BATU_VS \| BATU_VP)
	279	#define CONFIG_SYS_IBAT3L (PCI_MEM_SPACE2_START\|BATL_PP_10 \| BATL_GUARDEDSTORAGE \| BATL_CACHEINHIBIT)
	280	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	281	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
fe8c2806 WD	282
	283
	284	/*
	285	* For booting Linux, the board info and command line data
	286	* have to be in the first 8 MB of memory, since this is
	287	* the maximum mapped by the Linux kernel during initialization.
	288	*/
6d0f6bcf	289	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
fe8c2806 WD	290
	291	/*-----------------------------------------------------------------------
	292	* FLASH organization
	293	*/
6d0f6bcf JCPV	294	#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* Max number of flash banks */
6d0f6bcf JCPV	295	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
fe8c2806	296
6d0f6bcf JCPV	297	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	298	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
fe8c2806 WD	299
fe8c2806 WD	300	#if 0
5a1aceb0	301	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	302	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */
0e8d1586 JCPV	303	#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment Sector */
fe8c2806	304	#else
9314cee6	305	#define CONFIG_ENV_IS_IN_NVRAM 1
0e8d1586 JCPV	306	#define CONFIG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
	307	#define CONFIG_ENV_OFFSET CONFIG_ENV_ADDR
	308	#define CONFIG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */
fe8c2806 WD	309	#endif
	310	/*-----------------------------------------------------------------------
	311	* Cache Configuration
	312	*/
6d0f6bcf	313	#define CONFIG_SYS_CACHELINE_SIZE 16
fe8c2806 WD	314
fe8c2806 WD	315
fe8c2806 WD	316	/*
	317	* Internal Definitions
	318	*
	319	* Boot Flags
	320	*/
	321	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	322	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	323
	324	/* Localizations */
	325	#if 0
	326	#define CONFIG_ETHADDR 0:0:0:0:1:d
	327	#define CONFIG_IPADDR 172.16.40.113
	328	#define CONFIG_SERVERIP 172.16.40.111
	329	#else
	330	#define CONFIG_ETHADDR 0:0:0:0:1:d
	331	#define CONFIG_IPADDR 209.128.93.138
	332	#define CONFIG_SERVERIP 209.128.93.133
	333	#endif
	334
	335	/*-----------------------------------------------------------------------
	336	* PCI stuff
	337	*-----------------------------------------------------------------------
	338	*/
	339	#define CONFIG_PCI /* include pci support */
	340	#undef CONFIG_PCI_PNP
	341
53677ef1	342	#define CONFIG_NET_MULTI /* Multi ethernet cards support */
fe8c2806 WD	343
	344	#define CONFIG_TULIP
	345
	346	#endif /* __CONFIG_H */