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db2f721f WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Stuart Hughes <stuarth@lineo.com> | |
4 | * This file is based on similar values for other boards found in other | |
5 | * U-Boot config files, and some that I found in the mpc8260ads manual. | |
6 | * | |
7 | * Note: my board is a PILOT rev. | |
8 | * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /* | |
7a8e9bed WD |
30 | * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm |
31 | */ | |
32 | ||
33 | /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
2b792afc | 34 | !! !! |
7a8e9bed | 35 | !! This configuration requires JP3 to be in position 1-2 to work !! |
2b792afc | 36 | !! To make it work for the default, the TEXT_BASE define in !! |
7a8e9bed WD |
37 | !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !! |
38 | !! 0xfff00000 !! | |
6d0f6bcf | 39 | !! The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !! |
2b792afc | 40 | !! !! |
8bde7f77 | 41 | !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
db2f721f WD |
42 | */ |
43 | ||
44 | #ifndef __CONFIG_H | |
45 | #define __CONFIG_H | |
46 | ||
47 | /* | |
48 | * High Level Configuration Options | |
49 | * (easy to change) | |
50 | */ | |
51 | ||
c837dcb1 WD |
52 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
53 | #define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */ | |
9c4c5ae3 | 54 | #define CONFIG_CPM2 1 /* Has a CPM2 */ |
db2f721f | 55 | |
c837dcb1 | 56 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
004eca0c | 57 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
db2f721f WD |
58 | |
59 | /* allow serial and ethaddr to be overwritten */ | |
60 | #define CONFIG_ENV_OVERWRITE | |
61 | ||
62 | /* | |
63 | * select serial console configuration | |
64 | * | |
65 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then | |
66 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 | |
67 | * for SCC). | |
68 | * | |
69 | * if CONFIG_CONS_NONE is defined, then the serial console routines must | |
70 | * defined elsewhere (for example, on the cogent platform, there are serial | |
71 | * ports on the motherboard which are used for the serial console - see | |
72 | * cogent/cma101/serial.[ch]). | |
73 | */ | |
74 | #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ | |
75 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ | |
76 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
77 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
78 | ||
79 | /* | |
80 | * select ethernet configuration | |
81 | * | |
82 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then | |
83 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 | |
84 | * for FCC) | |
85 | * | |
86 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be | |
639221c7 | 87 | * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. |
db2f721f WD |
88 | */ |
89 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ | |
90 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ | |
91 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
92 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ | |
5d232d0e WD |
93 | #define CONFIG_MII /* MII PHY management */ |
94 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
95 | /* | |
96 | * Port pins used for bit-banged MII communictions (if applicable). | |
97 | */ | |
98 | #define MDIO_PORT 2 /* Port C */ | |
99 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) | |
100 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
101 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
102 | ||
103 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
104 | else iop->pdat &= ~0x00400000 | |
105 | ||
106 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
107 | else iop->pdat &= ~0x00200000 | |
108 | ||
109 | #define MIIDELAY udelay(1) | |
db2f721f WD |
110 | |
111 | #if (CONFIG_ETHER_INDEX == 2) | |
112 | ||
113 | /* | |
114 | * - Rx-CLK is CLK13 | |
115 | * - Tx-CLK is CLK14 | |
116 | * - Select bus for bd/buffers (see 28-13) | |
117 | * - Half duplex | |
118 | */ | |
6d0f6bcf JCPV |
119 | # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
120 | # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
121 | # define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
122 | # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
db2f721f WD |
123 | |
124 | #endif /* CONFIG_ETHER_INDEX */ | |
125 | ||
126 | /* other options */ | |
127 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ | |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
129 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
130 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
db2f721f | 131 | |
5d232d0e WD |
132 | /* PCI */ |
133 | #define CONFIG_PCI | |
134 | #define CONFIG_PCI_PNP | |
135 | #define CONFIG_PCI_BOOTDELAY 0 | |
136 | #undef CONFIG_PCI_SCAN_SHOW | |
137 | ||
db2f721f WD |
138 | /*----------------------------------------------------------------------- |
139 | * Definitions for Serial Presence Detect EEPROM address | |
140 | * (to get SDRAM settings) | |
141 | */ | |
2b792afc | 142 | #define SPD_EEPROM_ADDRESS 0x50 |
db2f721f | 143 | |
5d232d0e | 144 | #define CONFIG_8260_CLKIN 66000000 /* in Hz */ |
db2f721f WD |
145 | #define CONFIG_BAUDRATE 115200 |
146 | ||
1cc4c458 JL |
147 | /* |
148 | * Command line configuration. | |
149 | */ | |
298cd4ca RT |
150 | #include <config_cmd_default.h> |
151 | ||
152 | /* Commands we want, that are not part of default set */ | |
153 | #define CONFIG_CMD_ASKENV /* ask for env variable */ | |
154 | #define CONFIG_CMD_CACHE /* icache, dcache */ | |
155 | #define CONFIG_CMD_DHCP /* DHCP Support */ | |
156 | #define CONFIG_CMD_DIAG /* Diagnostics */ | |
157 | #define CONFIG_CMD_IMMAP /* IMMR dump support */ | |
158 | #define CONFIG_CMD_IRQ /* irqinfo */ | |
159 | #define CONFIG_CMD_MII /* MII support */ | |
160 | #define CONFIG_CMD_PCI /* pciinfo */ | |
161 | #define CONFIG_CMD_PING /* ping support */ | |
162 | #define CONFIG_CMD_PORTIO /* Port I/O */ | |
163 | #define CONFIG_CMD_REGINFO /* Register dump */ | |
164 | #define CONFIG_CMD_SAVES /* save S record dump */ | |
165 | #define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ | |
166 | ||
167 | /* Commands from default set we don't need */ | |
168 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
169 | #undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ | |
db2f721f | 170 | |
5d232d0e WD |
171 | /* Define a command string that is automatically executed when no character |
172 | * is read on the console interface withing "Boot Delay" after reset. | |
173 | */ | |
2b792afc WD |
174 | #undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */ |
175 | #define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */ | |
5d232d0e | 176 | |
42dfe7a1 | 177 | #ifdef CONFIG_BOOT_ROOT_INITRD |
5d232d0e WD |
178 | #define CONFIG_BOOTCOMMAND \ |
179 | "version;" \ | |
180 | "echo;" \ | |
181 | "bootp;" \ | |
182 | "setenv bootargs root=/dev/ram0 rw " \ | |
fe126d8b | 183 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ |
5d232d0e WD |
184 | "bootm" |
185 | #endif /* CONFIG_BOOT_ROOT_INITRD */ | |
186 | ||
42dfe7a1 | 187 | #ifdef CONFIG_BOOT_ROOT_NFS |
5d232d0e WD |
188 | #define CONFIG_BOOTCOMMAND \ |
189 | "version;" \ | |
190 | "echo;" \ | |
191 | "bootp;" \ | |
fe126d8b WD |
192 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
193 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ | |
5d232d0e WD |
194 | "bootm" |
195 | #endif /* CONFIG_BOOT_ROOT_NFS */ | |
196 | ||
7be044e4 JL |
197 | /* |
198 | * BOOTP options | |
5d232d0e | 199 | */ |
7be044e4 JL |
200 | #define CONFIG_BOOTP_SUBNETMASK |
201 | #define CONFIG_BOOTP_GATEWAY | |
202 | #define CONFIG_BOOTP_HOSTNAME | |
203 | #define CONFIG_BOOTP_BOOTPATH | |
204 | #define CONFIG_BOOTP_BOOTFILESIZE | |
205 | #define CONFIG_BOOTP_DNS | |
5d232d0e | 206 | |
db2f721f | 207 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
db2f721f | 208 | |
1cc4c458 | 209 | #if defined(CONFIG_CMD_KGDB) |
db2f721f WD |
210 | #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
211 | #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ | |
212 | #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ | |
213 | #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ | |
214 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ | |
215 | #endif | |
216 | ||
217 | #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ | |
218 | ||
219 | /* | |
220 | * Miscellaneous configurable options | |
221 | */ | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
223 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
1cc4c458 | 224 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 225 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
db2f721f | 226 | #else |
6d0f6bcf | 227 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
db2f721f | 228 | #endif |
6d0f6bcf JCPV |
229 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
230 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
231 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
db2f721f | 232 | |
6d0f6bcf JCPV |
233 | #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ |
234 | #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
db2f721f | 235 | |
5d232d0e | 236 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ |
db2f721f WD |
237 | /* for versions < 2.4.5-pre5 */ |
238 | ||
6d0f6bcf | 239 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
db2f721f | 240 | |
6d0f6bcf | 241 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
db2f721f | 242 | |
6d0f6bcf | 243 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
db2f721f | 244 | |
6d0f6bcf | 245 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
5d232d0e | 246 | #define FLASH_BASE 0xFE000000 |
6d0f6bcf JCPV |
247 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
248 | #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */ | |
249 | #define CONFIG_SYS_FLASH_SIZE 8 | |
250 | #define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ | |
251 | #define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ | |
db2f721f | 252 | |
6d0f6bcf | 253 | #undef CONFIG_SYS_FLASH_CHECKSUM |
db2f721f WD |
254 | |
255 | /* this is stuff came out of the Motorola docs */ | |
256 | /* Only change this if you also change the Hardware configuration Word */ | |
6d0f6bcf | 257 | #define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 |
db2f721f | 258 | |
db2f721f | 259 | /* Set IMMR to 0xF0000000 or above to boot Linux */ |
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_IMMR 0xF0000000 |
261 | #define CONFIG_SYS_BCSR 0xF8000000 | |
262 | #define CONFIG_SYS_PCI_INT 0xF8200000 /* PCI interrupt controller */ | |
db2f721f WD |
263 | |
264 | /* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes | |
265 | */ | |
266 | /*#define CONFIG_VERY_BIG_RAM 1*/ | |
267 | ||
268 | /* What should be the base address of SDRAM DIMM and how big is | |
269 | * it (in Mbytes)? This will normally auto-configure via the SPD. | |
270 | */ | |
6d0f6bcf JCPV |
271 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
272 | #define CONFIG_SYS_SDRAM_SIZE 16 | |
db2f721f WD |
273 | |
274 | #define SDRAM_SPD_ADDR 0x50 | |
275 | ||
db2f721f WD |
276 | /*----------------------------------------------------------------------- |
277 | * BR2,BR3 - Base Register | |
278 | * Ref: Section 10.3.1 on page 10-14 | |
279 | * OR2,OR3 - Option Register | |
280 | * Ref: Section 10.3.2 on page 10-16 | |
281 | *----------------------------------------------------------------------- | |
282 | */ | |
283 | ||
284 | /* Bank 2,3 - SDRAM DIMM | |
285 | */ | |
286 | ||
287 | /* The BR2 is configured as follows: | |
288 | * | |
289 | * - Base address of 0x00000000 | |
290 | * - 64 bit port size (60x bus only) | |
291 | * - Data errors checking is disabled | |
292 | * - Read and write access | |
293 | * - SDRAM 60x bus | |
294 | * - Access are handled by the memory controller according to MSEL | |
295 | * - Not used for atomic operations | |
296 | * - No data pipelining is done | |
297 | * - Valid | |
298 | */ | |
6d0f6bcf | 299 | #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ |
db2f721f WD |
300 | BRx_PS_64 |\ |
301 | BRx_MS_SDRAM_P |\ | |
302 | BRx_V) | |
303 | ||
6d0f6bcf | 304 | #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ |
db2f721f WD |
305 | BRx_PS_64 |\ |
306 | BRx_MS_SDRAM_P |\ | |
307 | BRx_V) | |
308 | ||
309 | /* With a 64 MB DIMM, the OR2 is configured as follows: | |
310 | * | |
311 | * - 64 MB | |
312 | * - 4 internal banks per device | |
313 | * - Row start address bit is A8 with PSDMR[PBI] = 0 | |
314 | * - 12 row address lines | |
315 | * - Back-to-back page mode | |
316 | * - Internal bank interleaving within save device enabled | |
317 | */ | |
6d0f6bcf JCPV |
318 | #if (CONFIG_SYS_SDRAM_SIZE == 64) |
319 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE) |\ | |
db2f721f WD |
320 | ORxS_BPD_4 |\ |
321 | ORxS_ROWST_PBI0_A8 |\ | |
322 | ORxS_NUMR_12) | |
6d0f6bcf JCPV |
323 | #elif (CONFIG_SYS_SDRAM_SIZE == 16) |
324 | #define CONFIG_SYS_OR2_PRELIM (0xFF000C80) | |
db2f721f WD |
325 | #else |
326 | #error "INVALID SDRAM CONFIGURATION" | |
327 | #endif | |
328 | ||
329 | /*----------------------------------------------------------------------- | |
330 | * PSDMR - 60x Bus SDRAM Mode Register | |
331 | * Ref: Section 10.3.3 on page 10-21 | |
332 | *----------------------------------------------------------------------- | |
333 | */ | |
334 | ||
6d0f6bcf | 335 | #if (CONFIG_SYS_SDRAM_SIZE == 64) |
db2f721f WD |
336 | /* With a 64 MB DIMM, the PSDMR is configured as follows: |
337 | * | |
338 | * - Bank Based Interleaving, | |
339 | * - Refresh Enable, | |
340 | * - Address Multiplexing where A5 is output on A14 pin | |
341 | * (A6 on A15, and so on), | |
342 | * - use address pins A14-A16 as bank select, | |
343 | * - A9 is output on SDA10 during an ACTIVATE command, | |
344 | * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks, | |
345 | * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command | |
346 | * is 3 clocks, | |
347 | * - earliest timing for READ/WRITE command after ACTIVATE command is | |
348 | * 2 clocks, | |
349 | * - earliest timing for PRECHARGE after last data was read is 1 clock, | |
350 | * - earliest timing for PRECHARGE after last data was written is 1 clock, | |
351 | * - CAS Latency is 2. | |
352 | */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_PSDMR (PSDMR_RFEN |\ |
db2f721f WD |
354 | PSDMR_SDAM_A14_IS_A5 |\ |
355 | PSDMR_BSMA_A14_A16 |\ | |
356 | PSDMR_SDA10_PBI0_A9 |\ | |
357 | PSDMR_RFRC_7_CLK |\ | |
358 | PSDMR_PRETOACT_3W |\ | |
359 | PSDMR_ACTTORW_2W |\ | |
360 | PSDMR_LDOTOPRE_1C |\ | |
361 | PSDMR_WRC_1C |\ | |
362 | PSDMR_CL_2) | |
6d0f6bcf | 363 | #elif (CONFIG_SYS_SDRAM_SIZE == 16) |
db2f721f WD |
364 | /* With a 16 MB DIMM, the PSDMR is configured as follows: |
365 | * | |
366 | * configuration parameters found in Motorola documentation | |
367 | */ | |
6d0f6bcf | 368 | #define CONFIG_SYS_PSDMR (0x016EB452) |
db2f721f WD |
369 | #else |
370 | #error "INVALID SDRAM CONFIGURATION" | |
371 | #endif | |
372 | ||
db2f721f WD |
373 | #define RS232EN_1 0x02000002 |
374 | #define RS232EN_2 0x01000001 | |
375 | #define FETHIEN 0x08000008 | |
376 | #define FETH_RST 0x04000004 | |
377 | ||
6d0f6bcf JCPV |
378 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
379 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ | |
380 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
381 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
382 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
db2f721f | 383 | |
7a8e9bed | 384 | /* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */ |
5d232d0e | 385 | /* 0x0EB2B645 */ |
6d0f6bcf | 386 | #define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\ |
5d232d0e WD |
387 | ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\ |
388 | ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ | |
389 | ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ | |
db2f721f | 390 | ) |
5d232d0e | 391 | |
7a8e9bed | 392 | /* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */ |
6d0f6bcf | 393 | /* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */ |
db2f721f | 394 | |
8bde7f77 | 395 | /* This value should actually be situated in the first 256 bytes of the FLASH |
db2f721f WD |
396 | which on the standard MPC8266ADS board is at address 0xFF800000 |
397 | The linker script places it at 0xFFF00000 instead. | |
398 | ||
8bde7f77 WD |
399 | It still works, however, as long as the ADS board jumper JP3 is set to |
400 | position 2-3 so the board is using the BCSR as Hardware Configuration Word | |
db2f721f | 401 | |
8bde7f77 WD |
402 | If you want to use the one defined here instead, ust copy the first 256 bytes from |
403 | 0xfff00000 to 0xff800000 (for 8MB flash) | |
db2f721f WD |
404 | |
405 | - Rune | |
406 | ||
7a8e9bed | 407 | */ |
db2f721f WD |
408 | |
409 | /* no slaves */ | |
6d0f6bcf JCPV |
410 | #define CONFIG_SYS_HRCW_SLAVE1 0 |
411 | #define CONFIG_SYS_HRCW_SLAVE2 0 | |
412 | #define CONFIG_SYS_HRCW_SLAVE3 0 | |
413 | #define CONFIG_SYS_HRCW_SLAVE4 0 | |
414 | #define CONFIG_SYS_HRCW_SLAVE5 0 | |
415 | #define CONFIG_SYS_HRCW_SLAVE6 0 | |
416 | #define CONFIG_SYS_HRCW_SLAVE7 0 | |
db2f721f WD |
417 | |
418 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
419 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
420 | ||
6d0f6bcf JCPV |
421 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
422 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) | |
423 | # define CONFIG_SYS_RAMBOOT | |
db2f721f WD |
424 | #endif |
425 | ||
6d0f6bcf JCPV |
426 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
427 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
428 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
db2f721f | 429 | |
6d0f6bcf | 430 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 431 | # define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 432 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 | 433 | # define CONFIG_ENV_SECT_SIZE 0x40000 |
db2f721f | 434 | #else |
9314cee6 | 435 | # define CONFIG_ENV_IS_IN_NVRAM 1 |
6d0f6bcf | 436 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 437 | # define CONFIG_ENV_SIZE 0x200 |
6d0f6bcf | 438 | #endif /* CONFIG_SYS_RAMBOOT */ |
db2f721f | 439 | |
6d0f6bcf | 440 | #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
1cc4c458 | 441 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 442 | # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
db2f721f WD |
443 | #endif |
444 | ||
7a8e9bed | 445 | /*----------------------------------------------------------------------- |
2b792afc | 446 | * HIDx - Hardware Implementation-dependent Registers 2-11 |
7a8e9bed WD |
447 | *----------------------------------------------------------------------- |
448 | * HID0 also contains cache control - initially enable both caches and | |
449 | * invalidate contents, then the final state leaves only the instruction | |
450 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, | |
451 | * but Soft reset does not. | |
452 | * | |
453 | * HID1 has only read-only information - nothing to set. | |
454 | */ | |
6d0f6bcf JCPV |
455 | /*#define CONFIG_SYS_HID0_INIT 0 */ |
456 | #define CONFIG_SYS_HID0_INIT (HID0_ICE |\ | |
7a8e9bed WD |
457 | HID0_DCE |\ |
458 | HID0_ICFI |\ | |
459 | HID0_DCI |\ | |
460 | HID0_IFEM |\ | |
461 | HID0_ABE) | |
462 | ||
6d0f6bcf | 463 | #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) |
db2f721f | 464 | |
6d0f6bcf | 465 | #define CONFIG_SYS_HID2 0 |
db2f721f | 466 | |
6d0f6bcf JCPV |
467 | #define CONFIG_SYS_SYPCR 0xFFFFFFC3 |
468 | #define CONFIG_SYS_BCR 0x004C0000 | |
469 | #define CONFIG_SYS_SIUMCR 0x4E64C000 | |
470 | #define CONFIG_SYS_SCCR 0x00000000 | |
db2f721f | 471 | |
5d232d0e WD |
472 | /* local bus memory map |
473 | * | |
474 | * 0x00000000-0x03FFFFFF 64MB SDRAM | |
475 | * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window | |
476 | * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window | |
477 | * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory | |
2b792afc | 478 | * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window |
5d232d0e WD |
479 | * 0xF8000000-0xF8007FFF 32KB BCSR |
480 | * 0xF8100000-0xF8107FFF 32KB ATM UNI | |
481 | * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller | |
482 | * 0xF8300000-0xF8307FFF 32KB EEPROM | |
483 | * 0xFE000000-0xFFFFFFFF 32MB flash | |
484 | */ | |
6d0f6bcf JCPV |
485 | #define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */ |
486 | #define CONFIG_SYS_OR0_PRELIM 0xFE000836 | |
487 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */ | |
488 | #define CONFIG_SYS_OR1_PRELIM 0xFFFF8010 | |
489 | #define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */ | |
490 | #define CONFIG_SYS_OR4_PRELIM 0xFFFF8846 | |
491 | #define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */ | |
492 | #define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36 | |
493 | #define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */ | |
494 | #define CONFIG_SYS_OR8_PRELIM 0xFFFF8010 | |
495 | ||
496 | #define CONFIG_SYS_RMR 0x0001 | |
497 | #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) | |
498 | #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) | |
499 | #define CONFIG_SYS_RCCR 0 | |
500 | #define CONFIG_SYS_MPTPR 0x00001900 | |
501 | #define CONFIG_SYS_PSRT 0x00000021 | |
db2f721f | 502 | |
65bd0e28 | 503 | /* This address must not exist */ |
6d0f6bcf | 504 | #define CONFIG_SYS_RESET_ADDRESS 0xFCFFFF00 |
db2f721f | 505 | |
5d232d0e | 506 | /* PCI Memory map (if different from default map */ |
6d0f6bcf JCPV |
507 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ |
508 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ | |
509 | #define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ | |
8bde7f77 | 510 | PICMR_PREFETCH_EN) |
5d232d0e | 511 | |
8bde7f77 | 512 | /* |
5d232d0e | 513 | * These are the windows that allow the CPU to access PCI address space. |
8bde7f77 WD |
514 | * All three PCI master windows, which allow the CPU to access PCI |
515 | * prefetch, non prefetch, and IO space (see below), must all fit within | |
5d232d0e WD |
516 | * these windows. |
517 | */ | |
518 | ||
519 | /* PCIBR0 */ | |
6d0f6bcf JCPV |
520 | #define CONFIG_SYS_PCI_MSTR0_LOCAL 0x80000000 /* Local base */ |
521 | #define CONFIG_SYS_PCIMSK0_MASK PCIMSK_1GB /* Size of window */ | |
5d232d0e | 522 | /* PCIBR1 */ |
6d0f6bcf JCPV |
523 | #define CONFIG_SYS_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */ |
524 | #define CONFIG_SYS_PCIMSK1_MASK PCIMSK_64MB /* Size of window */ | |
5d232d0e | 525 | |
8bde7f77 | 526 | /* |
5d232d0e WD |
527 | * Master window that allows the CPU to access PCI Memory (prefetch). |
528 | * This window will be setup with the first set of Outbound ATU registers | |
529 | * in the bridge. | |
530 | */ | |
531 | ||
6d0f6bcf JCPV |
532 | #define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ |
533 | #define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ | |
534 | #define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL | |
535 | #define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ | |
536 | #define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) | |
5d232d0e | 537 | |
8bde7f77 | 538 | /* |
5d232d0e WD |
539 | * Master window that allows the CPU to access PCI Memory (non-prefetch). |
540 | * This window will be setup with the second set of Outbound ATU registers | |
541 | * in the bridge. | |
542 | */ | |
543 | ||
6d0f6bcf JCPV |
544 | #define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ |
545 | #define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ | |
546 | #define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL | |
547 | #define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ | |
548 | #define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) | |
5d232d0e | 549 | |
8bde7f77 | 550 | /* |
5d232d0e WD |
551 | * Master window that allows the CPU to access PCI IO space. |
552 | * This window will be setup with the third set of Outbound ATU registers | |
553 | * in the bridge. | |
554 | */ | |
555 | ||
6d0f6bcf JCPV |
556 | #define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */ |
557 | #define CONFIG_SYS_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */ | |
558 | #define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL | |
559 | #define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */ | |
560 | #define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO) | |
5d232d0e | 561 | |
700a0c64 WD |
562 | /* |
563 | * JFFS2 partitions | |
564 | * | |
565 | */ | |
566 | /* No command line, one static partition, whole device */ | |
68d7d651 | 567 | #undef CONFIG_CMD_MTDPARTS |
700a0c64 WD |
568 | #define CONFIG_JFFS2_DEV "nor0" |
569 | #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF | |
570 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
571 | ||
572 | /* mtdparts command line support */ | |
573 | /* | |
68d7d651 | 574 | #define CONFIG_CMD_MTDPARTS |
700a0c64 WD |
575 | #define MTDIDS_DEFAULT "" |
576 | #define MTDPARTS_DEFAULT "" | |
577 | */ | |
5d232d0e | 578 | |
db2f721f | 579 | #endif /* __CONFIG_H */ |