]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/MPC8266ADS.h
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / include / configs / MPC8266ADS.h
CommitLineData
db2f721f
WD
1/*
2 * (C) Copyright 2001
3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
6 *
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
7a8e9bed
WD
30 * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
31 */
32
33/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
2b792afc 34 !! !!
7a8e9bed 35 !! This configuration requires JP3 to be in position 1-2 to work !!
2b792afc 36 !! To make it work for the default, the TEXT_BASE define in !!
7a8e9bed
WD
37 !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !!
38 !! 0xfff00000 !!
6d0f6bcf 39 !! The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
2b792afc 40 !! !!
8bde7f77 41 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
db2f721f
WD
42 */
43
44#ifndef __CONFIG_H
45#define __CONFIG_H
46
47/*
48 * High Level Configuration Options
49 * (easy to change)
50 */
51
c837dcb1
WD
52#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
53#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
9c4c5ae3 54#define CONFIG_CPM2 1 /* Has a CPM2 */
db2f721f 55
c837dcb1 56#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
db2f721f
WD
57
58/* allow serial and ethaddr to be overwritten */
59#define CONFIG_ENV_OVERWRITE
60
61/*
62 * select serial console configuration
63 *
64 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
65 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
66 * for SCC).
67 *
68 * if CONFIG_CONS_NONE is defined, then the serial console routines must
69 * defined elsewhere (for example, on the cogent platform, there are serial
70 * ports on the motherboard which are used for the serial console - see
71 * cogent/cma101/serial.[ch]).
72 */
73#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
74#define CONFIG_CONS_ON_SCC /* define if console on SCC */
75#undef CONFIG_CONS_NONE /* define if console on something else */
76#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
77
78/*
79 * select ethernet configuration
80 *
81 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
82 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
83 * for FCC)
84 *
85 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
639221c7 86 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
db2f721f
WD
87 */
88#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
89#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
90#undef CONFIG_ETHER_NONE /* define if ether on something else */
91#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
5d232d0e
WD
92#define CONFIG_MII /* MII PHY management */
93#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
94/*
95 * Port pins used for bit-banged MII communictions (if applicable).
96 */
97#define MDIO_PORT 2 /* Port C */
98#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
99#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
100#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
101
102#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
103 else iop->pdat &= ~0x00400000
104
105#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
106 else iop->pdat &= ~0x00200000
107
108#define MIIDELAY udelay(1)
db2f721f
WD
109
110#if (CONFIG_ETHER_INDEX == 2)
111
112/*
113 * - Rx-CLK is CLK13
114 * - Tx-CLK is CLK14
115 * - Select bus for bd/buffers (see 28-13)
116 * - Half duplex
117 */
6d0f6bcf
JCPV
118# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
119# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
120# define CONFIG_SYS_CPMFCR_RAMTYPE 0
121# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
db2f721f
WD
122
123#endif /* CONFIG_ETHER_INDEX */
124
125/* other options */
126#define CONFIG_HARD_I2C 1 /* To enable I2C support */
6d0f6bcf
JCPV
127#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
128#define CONFIG_SYS_I2C_SLAVE 0x7F
129#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
db2f721f 130
5d232d0e
WD
131/* PCI */
132#define CONFIG_PCI
133#define CONFIG_PCI_PNP
134#define CONFIG_PCI_BOOTDELAY 0
135#undef CONFIG_PCI_SCAN_SHOW
136
db2f721f
WD
137/*-----------------------------------------------------------------------
138 * Definitions for Serial Presence Detect EEPROM address
139 * (to get SDRAM settings)
140 */
2b792afc 141#define SPD_EEPROM_ADDRESS 0x50
db2f721f 142
5d232d0e 143#define CONFIG_8260_CLKIN 66000000 /* in Hz */
db2f721f
WD
144#define CONFIG_BAUDRATE 115200
145
1cc4c458
JL
146/*
147 * Command line configuration.
148 */
298cd4ca
RT
149#include <config_cmd_default.h>
150
151/* Commands we want, that are not part of default set */
152#define CONFIG_CMD_ASKENV /* ask for env variable */
153#define CONFIG_CMD_CACHE /* icache, dcache */
154#define CONFIG_CMD_DHCP /* DHCP Support */
155#define CONFIG_CMD_DIAG /* Diagnostics */
156#define CONFIG_CMD_IMMAP /* IMMR dump support */
157#define CONFIG_CMD_IRQ /* irqinfo */
158#define CONFIG_CMD_MII /* MII support */
159#define CONFIG_CMD_PCI /* pciinfo */
160#define CONFIG_CMD_PING /* ping support */
161#define CONFIG_CMD_PORTIO /* Port I/O */
162#define CONFIG_CMD_REGINFO /* Register dump */
163#define CONFIG_CMD_SAVES /* save S record dump */
164#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
165
166/* Commands from default set we don't need */
167#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
168#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
db2f721f 169
5d232d0e
WD
170/* Define a command string that is automatically executed when no character
171 * is read on the console interface withing "Boot Delay" after reset.
172 */
2b792afc
WD
173#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
174#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
5d232d0e 175
42dfe7a1 176#ifdef CONFIG_BOOT_ROOT_INITRD
5d232d0e
WD
177#define CONFIG_BOOTCOMMAND \
178 "version;" \
179 "echo;" \
180 "bootp;" \
181 "setenv bootargs root=/dev/ram0 rw " \
fe126d8b 182 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
5d232d0e
WD
183 "bootm"
184#endif /* CONFIG_BOOT_ROOT_INITRD */
185
42dfe7a1 186#ifdef CONFIG_BOOT_ROOT_NFS
5d232d0e
WD
187#define CONFIG_BOOTCOMMAND \
188 "version;" \
189 "echo;" \
190 "bootp;" \
fe126d8b
WD
191 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
192 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
5d232d0e
WD
193 "bootm"
194#endif /* CONFIG_BOOT_ROOT_NFS */
195
7be044e4
JL
196/*
197 * BOOTP options
5d232d0e 198 */
7be044e4
JL
199#define CONFIG_BOOTP_SUBNETMASK
200#define CONFIG_BOOTP_GATEWAY
201#define CONFIG_BOOTP_HOSTNAME
202#define CONFIG_BOOTP_BOOTPATH
203#define CONFIG_BOOTP_BOOTFILESIZE
204#define CONFIG_BOOTP_DNS
5d232d0e 205
db2f721f 206#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
db2f721f 207
1cc4c458 208#if defined(CONFIG_CMD_KGDB)
db2f721f
WD
209#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
210#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
211#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
212#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
213#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
214#endif
215
216#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
217
218/*
219 * Miscellaneous configurable options
220 */
6d0f6bcf
JCPV
221#define CONFIG_SYS_LONGHELP /* undef to save memory */
222#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
1cc4c458 223#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 224#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
db2f721f 225#else
6d0f6bcf 226#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
db2f721f 227#endif
6d0f6bcf
JCPV
228#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
229#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
230#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
db2f721f 231
6d0f6bcf
JCPV
232#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
233#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
db2f721f 234
5d232d0e 235#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
db2f721f
WD
236 /* for versions < 2.4.5-pre5 */
237
6d0f6bcf 238#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
db2f721f 239
6d0f6bcf 240#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
db2f721f 241
6d0f6bcf 242#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
db2f721f 243
6d0f6bcf 244#define CONFIG_SYS_FLASH_BASE 0xFE000000
5d232d0e 245#define FLASH_BASE 0xFE000000
6d0f6bcf
JCPV
246#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
247#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
248#define CONFIG_SYS_FLASH_SIZE 8
249#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
250#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
db2f721f 251
6d0f6bcf 252#undef CONFIG_SYS_FLASH_CHECKSUM
db2f721f
WD
253
254/* this is stuff came out of the Motorola docs */
255/* Only change this if you also change the Hardware configuration Word */
6d0f6bcf 256#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
db2f721f 257
db2f721f 258/* Set IMMR to 0xF0000000 or above to boot Linux */
6d0f6bcf
JCPV
259#define CONFIG_SYS_IMMR 0xF0000000
260#define CONFIG_SYS_BCSR 0xF8000000
261#define CONFIG_SYS_PCI_INT 0xF8200000 /* PCI interrupt controller */
db2f721f
WD
262
263/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
264 */
265/*#define CONFIG_VERY_BIG_RAM 1*/
266
267/* What should be the base address of SDRAM DIMM and how big is
268 * it (in Mbytes)? This will normally auto-configure via the SPD.
269*/
6d0f6bcf
JCPV
270#define CONFIG_SYS_SDRAM_BASE 0x00000000
271#define CONFIG_SYS_SDRAM_SIZE 16
db2f721f
WD
272
273#define SDRAM_SPD_ADDR 0x50
274
db2f721f
WD
275/*-----------------------------------------------------------------------
276 * BR2,BR3 - Base Register
277 * Ref: Section 10.3.1 on page 10-14
278 * OR2,OR3 - Option Register
279 * Ref: Section 10.3.2 on page 10-16
280 *-----------------------------------------------------------------------
281 */
282
283/* Bank 2,3 - SDRAM DIMM
284 */
285
286/* The BR2 is configured as follows:
287 *
288 * - Base address of 0x00000000
289 * - 64 bit port size (60x bus only)
290 * - Data errors checking is disabled
291 * - Read and write access
292 * - SDRAM 60x bus
293 * - Access are handled by the memory controller according to MSEL
294 * - Not used for atomic operations
295 * - No data pipelining is done
296 * - Valid
297 */
6d0f6bcf 298#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
db2f721f
WD
299 BRx_PS_64 |\
300 BRx_MS_SDRAM_P |\
301 BRx_V)
302
6d0f6bcf 303#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
db2f721f
WD
304 BRx_PS_64 |\
305 BRx_MS_SDRAM_P |\
306 BRx_V)
307
308/* With a 64 MB DIMM, the OR2 is configured as follows:
309 *
310 * - 64 MB
311 * - 4 internal banks per device
312 * - Row start address bit is A8 with PSDMR[PBI] = 0
313 * - 12 row address lines
314 * - Back-to-back page mode
315 * - Internal bank interleaving within save device enabled
316 */
6d0f6bcf
JCPV
317#if (CONFIG_SYS_SDRAM_SIZE == 64)
318#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE) |\
db2f721f
WD
319 ORxS_BPD_4 |\
320 ORxS_ROWST_PBI0_A8 |\
321 ORxS_NUMR_12)
6d0f6bcf
JCPV
322#elif (CONFIG_SYS_SDRAM_SIZE == 16)
323#define CONFIG_SYS_OR2_PRELIM (0xFF000C80)
db2f721f
WD
324#else
325#error "INVALID SDRAM CONFIGURATION"
326#endif
327
328/*-----------------------------------------------------------------------
329 * PSDMR - 60x Bus SDRAM Mode Register
330 * Ref: Section 10.3.3 on page 10-21
331 *-----------------------------------------------------------------------
332 */
333
6d0f6bcf 334#if (CONFIG_SYS_SDRAM_SIZE == 64)
db2f721f
WD
335/* With a 64 MB DIMM, the PSDMR is configured as follows:
336 *
337 * - Bank Based Interleaving,
338 * - Refresh Enable,
339 * - Address Multiplexing where A5 is output on A14 pin
340 * (A6 on A15, and so on),
341 * - use address pins A14-A16 as bank select,
342 * - A9 is output on SDA10 during an ACTIVATE command,
343 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
344 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
345 * is 3 clocks,
346 * - earliest timing for READ/WRITE command after ACTIVATE command is
347 * 2 clocks,
348 * - earliest timing for PRECHARGE after last data was read is 1 clock,
349 * - earliest timing for PRECHARGE after last data was written is 1 clock,
350 * - CAS Latency is 2.
351 */
6d0f6bcf 352#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
db2f721f
WD
353 PSDMR_SDAM_A14_IS_A5 |\
354 PSDMR_BSMA_A14_A16 |\
355 PSDMR_SDA10_PBI0_A9 |\
356 PSDMR_RFRC_7_CLK |\
357 PSDMR_PRETOACT_3W |\
358 PSDMR_ACTTORW_2W |\
359 PSDMR_LDOTOPRE_1C |\
360 PSDMR_WRC_1C |\
361 PSDMR_CL_2)
6d0f6bcf 362#elif (CONFIG_SYS_SDRAM_SIZE == 16)
db2f721f
WD
363/* With a 16 MB DIMM, the PSDMR is configured as follows:
364 *
365 * configuration parameters found in Motorola documentation
366 */
6d0f6bcf 367#define CONFIG_SYS_PSDMR (0x016EB452)
db2f721f
WD
368#else
369#error "INVALID SDRAM CONFIGURATION"
370#endif
371
db2f721f
WD
372#define RS232EN_1 0x02000002
373#define RS232EN_2 0x01000001
374#define FETHIEN 0x08000008
375#define FETH_RST 0x04000004
376
6d0f6bcf
JCPV
377#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
378#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
379#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
380#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
381#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
db2f721f 382
7a8e9bed 383/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
5d232d0e 384/* 0x0EB2B645 */
6d0f6bcf 385#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
5d232d0e
WD
386 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\
387 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
388 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
db2f721f 389 )
5d232d0e 390
7a8e9bed 391/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */
6d0f6bcf 392/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */
db2f721f 393
8bde7f77 394/* This value should actually be situated in the first 256 bytes of the FLASH
db2f721f
WD
395 which on the standard MPC8266ADS board is at address 0xFF800000
396 The linker script places it at 0xFFF00000 instead.
397
8bde7f77
WD
398 It still works, however, as long as the ADS board jumper JP3 is set to
399 position 2-3 so the board is using the BCSR as Hardware Configuration Word
db2f721f 400
8bde7f77
WD
401 If you want to use the one defined here instead, ust copy the first 256 bytes from
402 0xfff00000 to 0xff800000 (for 8MB flash)
db2f721f
WD
403
404 - Rune
405
7a8e9bed 406*/
db2f721f
WD
407
408/* no slaves */
6d0f6bcf
JCPV
409#define CONFIG_SYS_HRCW_SLAVE1 0
410#define CONFIG_SYS_HRCW_SLAVE2 0
411#define CONFIG_SYS_HRCW_SLAVE3 0
412#define CONFIG_SYS_HRCW_SLAVE4 0
413#define CONFIG_SYS_HRCW_SLAVE5 0
414#define CONFIG_SYS_HRCW_SLAVE6 0
415#define CONFIG_SYS_HRCW_SLAVE7 0
db2f721f
WD
416
417#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
418#define BOOTFLAG_WARM 0x02 /* Software reboot */
419
6d0f6bcf
JCPV
420#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
421#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
422# define CONFIG_SYS_RAMBOOT
db2f721f
WD
423#endif
424
6d0f6bcf
JCPV
425#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
426#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
427#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
db2f721f 428
6d0f6bcf 429#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0 430# define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf 431# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 432# define CONFIG_ENV_SECT_SIZE 0x40000
db2f721f 433#else
9314cee6 434# define CONFIG_ENV_IS_IN_NVRAM 1
6d0f6bcf 435# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586 436# define CONFIG_ENV_SIZE 0x200
6d0f6bcf 437#endif /* CONFIG_SYS_RAMBOOT */
db2f721f 438
6d0f6bcf 439#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
1cc4c458 440#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 441# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
db2f721f
WD
442#endif
443
7a8e9bed 444/*-----------------------------------------------------------------------
2b792afc 445 * HIDx - Hardware Implementation-dependent Registers 2-11
7a8e9bed
WD
446 *-----------------------------------------------------------------------
447 * HID0 also contains cache control - initially enable both caches and
448 * invalidate contents, then the final state leaves only the instruction
449 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
450 * but Soft reset does not.
451 *
452 * HID1 has only read-only information - nothing to set.
453 */
6d0f6bcf
JCPV
454/*#define CONFIG_SYS_HID0_INIT 0 */
455#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
7a8e9bed
WD
456 HID0_DCE |\
457 HID0_ICFI |\
458 HID0_DCI |\
459 HID0_IFEM |\
460 HID0_ABE)
461
6d0f6bcf 462#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
db2f721f 463
6d0f6bcf 464#define CONFIG_SYS_HID2 0
db2f721f 465
6d0f6bcf
JCPV
466#define CONFIG_SYS_SYPCR 0xFFFFFFC3
467#define CONFIG_SYS_BCR 0x004C0000
468#define CONFIG_SYS_SIUMCR 0x4E64C000
469#define CONFIG_SYS_SCCR 0x00000000
db2f721f 470
5d232d0e
WD
471/* local bus memory map
472 *
473 * 0x00000000-0x03FFFFFF 64MB SDRAM
474 * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window
475 * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window
476 * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory
2b792afc 477 * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
5d232d0e
WD
478 * 0xF8000000-0xF8007FFF 32KB BCSR
479 * 0xF8100000-0xF8107FFF 32KB ATM UNI
480 * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller
481 * 0xF8300000-0xF8307FFF 32KB EEPROM
482 * 0xFE000000-0xFFFFFFFF 32MB flash
483 */
6d0f6bcf
JCPV
484#define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */
485#define CONFIG_SYS_OR0_PRELIM 0xFE000836
486#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */
487#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
488#define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */
489#define CONFIG_SYS_OR4_PRELIM 0xFFFF8846
490#define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */
491#define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36
492#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
493#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
494
495#define CONFIG_SYS_RMR 0x0001
496#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
497#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
498#define CONFIG_SYS_RCCR 0
499#define CONFIG_SYS_MPTPR 0x00001900
500#define CONFIG_SYS_PSRT 0x00000021
db2f721f 501
65bd0e28 502/* This address must not exist */
6d0f6bcf 503#define CONFIG_SYS_RESET_ADDRESS 0xFCFFFF00
db2f721f 504
5d232d0e 505/* PCI Memory map (if different from default map */
6d0f6bcf
JCPV
506#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
507#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
508#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
8bde7f77 509 PICMR_PREFETCH_EN)
5d232d0e 510
8bde7f77 511/*
5d232d0e 512 * These are the windows that allow the CPU to access PCI address space.
8bde7f77
WD
513 * All three PCI master windows, which allow the CPU to access PCI
514 * prefetch, non prefetch, and IO space (see below), must all fit within
5d232d0e
WD
515 * these windows.
516 */
517
518/* PCIBR0 */
6d0f6bcf
JCPV
519#define CONFIG_SYS_PCI_MSTR0_LOCAL 0x80000000 /* Local base */
520#define CONFIG_SYS_PCIMSK0_MASK PCIMSK_1GB /* Size of window */
5d232d0e 521/* PCIBR1 */
6d0f6bcf
JCPV
522#define CONFIG_SYS_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
523#define CONFIG_SYS_PCIMSK1_MASK PCIMSK_64MB /* Size of window */
5d232d0e 524
8bde7f77 525/*
5d232d0e
WD
526 * Master window that allows the CPU to access PCI Memory (prefetch).
527 * This window will be setup with the first set of Outbound ATU registers
528 * in the bridge.
529 */
530
6d0f6bcf
JCPV
531#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
532#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
533#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
534#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
535#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
5d232d0e 536
8bde7f77 537/*
5d232d0e
WD
538 * Master window that allows the CPU to access PCI Memory (non-prefetch).
539 * This window will be setup with the second set of Outbound ATU registers
540 * in the bridge.
541 */
542
6d0f6bcf
JCPV
543#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
544#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
545#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
546#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
547#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
5d232d0e 548
8bde7f77 549/*
5d232d0e
WD
550 * Master window that allows the CPU to access PCI IO space.
551 * This window will be setup with the third set of Outbound ATU registers
552 * in the bridge.
553 */
554
6d0f6bcf
JCPV
555#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
556#define CONFIG_SYS_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
557#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
558#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
559#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
5d232d0e 560
700a0c64
WD
561/*
562 * JFFS2 partitions
563 *
564 */
565/* No command line, one static partition, whole device */
566#undef CONFIG_JFFS2_CMDLINE
567#define CONFIG_JFFS2_DEV "nor0"
568#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
569#define CONFIG_JFFS2_PART_OFFSET 0x00000000
570
571/* mtdparts command line support */
572/*
573#define CONFIG_JFFS2_CMDLINE
574#define MTDIDS_DEFAULT ""
575#define MTDPARTS_DEFAULT ""
576*/
5d232d0e 577
db2f721f 578#endif /* __CONFIG_H */