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96b8a054 SW |
1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
96b8a054 SW |
21 | */ |
22 | /* | |
23 | * mpc8313epb board configuration file | |
24 | */ | |
25 | ||
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* | |
30 | * High Level Configuration Options | |
31 | */ | |
32 | #define CONFIG_E300 1 | |
33 | #define CONFIG_MPC83XX 1 | |
34 | #define CONFIG_MPC831X 1 | |
35 | #define CONFIG_MPC8313 1 | |
36 | #define CONFIG_MPC8313ERDB 1 | |
37 | ||
38 | #define CONFIG_PCI | |
39 | #define CONFIG_83XX_GENERIC_PCI | |
40 | ||
89c7784e TT |
41 | #define CONFIG_MISC_INIT_R |
42 | ||
43 | /* | |
44 | * On-board devices | |
45 | */ | |
46 | #define CONFIG_VSC7385_ENET | |
47 | ||
48 | ||
96b8a054 | 49 | #ifdef CFG_66MHZ |
5c5d3242 | 50 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ |
96b8a054 | 51 | #elif defined(CFG_33MHZ) |
5c5d3242 | 52 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ |
96b8a054 SW |
53 | #else |
54 | #error Unknown oscillator frequency. | |
55 | #endif | |
56 | ||
57 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
58 | ||
59 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
60 | ||
61 | #define CFG_IMMR 0xE0000000 | |
62 | ||
63 | #define CFG_MEMTEST_START 0x00001000 | |
64 | #define CFG_MEMTEST_END 0x07f00000 | |
65 | ||
66 | /* Early revs of this board will lock up hard when attempting | |
67 | * to access the PMC registers, unless a JTAG debugger is | |
68 | * connected, or some resistor modifications are made. | |
69 | */ | |
70 | #define CFG_8313ERDB_BROKEN_PMC 1 | |
71 | ||
72 | #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ | |
73 | #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
74 | ||
89c7784e TT |
75 | /* |
76 | * Device configurations | |
77 | */ | |
78 | ||
79 | /* Vitesse 7385 */ | |
80 | ||
81 | #ifdef CONFIG_VSC7385_ENET | |
82 | ||
83 | #define CONFIG_TSEC2 | |
84 | ||
85 | /* The flash address and size of the VSC7385 firmware image */ | |
86 | #define CONFIG_VSC7385_IMAGE 0xFE7FE000 | |
87 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
88 | ||
89 | #endif | |
90 | ||
96b8a054 SW |
91 | /* |
92 | * DDR Setup | |
93 | */ | |
94 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ | |
95 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
96 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
97 | ||
98 | /* | |
99 | * Manually set up DDR parameters, as this board does not | |
100 | * seem to have the SPD connected to I2C. | |
101 | */ | |
102 | #define CFG_DDR_SIZE 128 /* MB */ | |
e1d8ed2c PA |
103 | #define CFG_DDR_CONFIG ( CSCONFIG_EN \ |
104 | | 0x00010000 /* TODO */ \ | |
96b8a054 | 105 | | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) |
e1d8ed2c | 106 | /* 0x80010102 */ |
96b8a054 SW |
107 | |
108 | #define CFG_DDR_TIMING_3 0x00000000 | |
109 | #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ | |
110 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ | |
111 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | |
112 | | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | |
113 | | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | |
114 | | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | |
115 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | |
116 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | |
117 | /* 0x00220802 */ | |
118 | #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ | |
e1d8ed2c | 119 | | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ |
96b8a054 SW |
120 | | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ |
121 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | |
e1d8ed2c | 122 | | (10 << TIMING_CFG1_REFREC_SHIFT ) \ |
96b8a054 SW |
123 | | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ |
124 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | |
125 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | |
e1d8ed2c PA |
126 | /* 0x3835a322 */ |
127 | #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ | |
128 | | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ | |
96b8a054 SW |
129 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ |
130 | | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | |
131 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | |
132 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | |
e1d8ed2c PA |
133 | | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) |
134 | /* 0x129048c6 */ /* P9-45,may need tuning */ | |
135 | #define CFG_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ | |
136 | | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) | |
137 | /* 0x05100500 */ | |
96b8a054 SW |
138 | #if defined(CONFIG_DDR_2T_TIMING) |
139 | #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ | |
bbea46f7 | 140 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
96b8a054 SW |
141 | | SDRAM_CFG_2T_EN \ |
142 | | SDRAM_CFG_DBW_32 ) | |
143 | #else | |
144 | #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ | |
bbea46f7 | 145 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
96b8a054 SW |
146 | | SDRAM_CFG_32_BE ) |
147 | /* 0x43080000 */ | |
148 | #endif | |
149 | #define CFG_SDRAM_CFG2 0x00401000; | |
150 | /* set burst length to 8 for 32-bit data path */ | |
e1d8ed2c PA |
151 | #define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ |
152 | | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) | |
153 | /* 0x44480632 */ | |
96b8a054 SW |
154 | #define CFG_DDR_MODE_2 0x8000C000; |
155 | ||
156 | #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
157 | /*0x02000000*/ | |
158 | #define CFG_DDRCDR_VALUE ( DDRCDR_EN \ | |
159 | | DDRCDR_PZ_NOMZ \ | |
160 | | DDRCDR_NZ_NOMZ \ | |
161 | | DDRCDR_M_ODR ) | |
162 | ||
163 | /* | |
164 | * FLASH on the Local Bus | |
165 | */ | |
166 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
167 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
168 | #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ | |
169 | #define CFG_FLASH_SIZE 8 /* flash size in MB */ | |
170 | #define CFG_FLASH_EMPTY_INFO /* display empty sectors */ | |
171 | #define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ | |
172 | ||
a7676ea7 WD |
173 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ |
174 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ | |
175 | BR_V) /* valid */ | |
176 | #define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \ | |
96b8a054 SW |
177 | | OR_GPCM_XACS \ |
178 | | OR_GPCM_SCY_9 \ | |
179 | | OR_GPCM_EHTR \ | |
180 | | OR_GPCM_EAD ) | |
181 | /* 0xFF006FF7 TODO SLOW 16 MB flash size */ | |
182 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ | |
183 | #define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ | |
184 | ||
185 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
186 | #define CFG_MAX_FLASH_SECT 135 /* sectors per device */ | |
187 | ||
188 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
189 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
190 | ||
191 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
192 | ||
193 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
194 | #define CFG_RAMBOOT | |
195 | #endif | |
196 | ||
197 | #define CFG_INIT_RAM_LOCK 1 | |
198 | #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
199 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
200 | ||
201 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
202 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
203 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
204 | ||
b2893e1f | 205 | /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ |
96b8a054 SW |
206 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
207 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
208 | ||
209 | /* | |
210 | * Local Bus LCRR and LBCR regs | |
211 | */ | |
212 | #define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ | |
213 | #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ | |
214 | | (0xFF << LBCR_BMT_SHIFT) \ | |
215 | | 0xF ) /* 0x0004ff0f */ | |
216 | ||
a7676ea7 | 217 | #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ |
96b8a054 | 218 | |
7817cb20 | 219 | /* drivers/mtd/nand/nand.c */ |
a7676ea7 | 220 | #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ |
96b8a054 SW |
221 | #define CFG_MAX_NAND_DEVICE 1 |
222 | #define NAND_MAX_CHIPS 1 | |
223 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
224 | ||
225 | #define CFG_BR1_PRELIM ( CFG_NAND_BASE \ | |
a7676ea7 WD |
226 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
227 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
228 | | BR_MS_FCM /* MSEL = FCM */ \ | |
229 | | BR_V ) /* valid */ | |
230 | #define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ | |
96b8a054 SW |
231 | | OR_FCM_CSCT \ |
232 | | OR_FCM_CST \ | |
233 | | OR_FCM_CHT \ | |
234 | | OR_FCM_SCY_1 \ | |
235 | | OR_FCM_TRLX \ | |
236 | | OR_FCM_EHTR ) | |
237 | /* 0xFFFF8396 */ | |
238 | #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE | |
239 | #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ | |
240 | ||
89c7784e TT |
241 | /* local bus read write buffer mapping */ |
242 | #define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ | |
243 | #define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ | |
244 | #define CFG_LBLAWBAR3_PRELIM 0xFA000000 | |
245 | #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ | |
246 | ||
247 | /* Vitesse 7385 */ | |
248 | ||
96b8a054 SW |
249 | #define CFG_VSC7385_BASE 0xF0000000 |
250 | ||
89c7784e TT |
251 | #ifdef CONFIG_VSC7385_ENET |
252 | ||
96b8a054 SW |
253 | #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ |
254 | #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ | |
255 | #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ | |
256 | #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ | |
257 | ||
89c7784e | 258 | #endif |
96b8a054 SW |
259 | |
260 | /* pass open firmware flat tree */ | |
35cc4e48 | 261 | #define CONFIG_OF_LIBFDT 1 |
96b8a054 | 262 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 263 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
96b8a054 SW |
264 | |
265 | /* | |
266 | * Serial Port | |
267 | */ | |
268 | #define CONFIG_CONS_INDEX 1 | |
269 | #define CFG_NS16550 | |
270 | #define CFG_NS16550_SERIAL | |
271 | #define CFG_NS16550_REG_SIZE 1 | |
272 | #define CFG_NS16550_CLK get_bus_freq(0) | |
273 | ||
274 | #define CFG_BAUDRATE_TABLE \ | |
275 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
276 | ||
277 | #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) | |
278 | #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) | |
279 | ||
280 | /* Use the HUSH parser */ | |
281 | #define CFG_HUSH_PARSER | |
282 | #define CFG_PROMPT_HUSH_PS2 "> " | |
283 | ||
284 | /* I2C */ | |
285 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
286 | #define CONFIG_FSL_I2C | |
287 | #define CONFIG_I2C_MULTI_BUS | |
288 | #define CONFIG_I2C_CMD_TREE | |
289 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
290 | #define CFG_I2C_SLAVE 0x7F | |
cdd917a4 | 291 | #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
96b8a054 SW |
292 | #define CFG_I2C_OFFSET 0x3000 |
293 | #define CFG_I2C2_OFFSET 0x3100 | |
294 | ||
96b8a054 SW |
295 | /* |
296 | * General PCI | |
297 | * Addresses are mapped 1-1. | |
298 | */ | |
299 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
300 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
301 | #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
302 | #define CFG_PCI1_MMIO_BASE 0x90000000 | |
303 | #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE | |
304 | #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
305 | #define CFG_PCI1_IO_BASE 0x00000000 | |
306 | #define CFG_PCI1_IO_PHYS 0xE2000000 | |
307 | #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
308 | ||
309 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
310 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
311 | ||
312 | /* | |
89c7784e | 313 | * TSEC |
96b8a054 SW |
314 | */ |
315 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
316 | ||
89c7784e TT |
317 | #define CONFIG_NET_MULTI |
318 | #define CONFIG_GMII /* MII PHY management */ | |
96b8a054 | 319 | |
89c7784e TT |
320 | #ifdef CONFIG_TSEC1 |
321 | #define CONFIG_HAS_ETH0 | |
255a3577 | 322 | #define CONFIG_TSEC1_NAME "TSEC0" |
89c7784e TT |
323 | #define CFG_TSEC1_OFFSET 0x24000 |
324 | #define TSEC1_PHY_ADDR 0x1c | |
325 | #define TSEC1_FLAGS TSEC_GIGABIT | |
326 | #define TSEC1_PHYIDX 0 | |
327 | #endif | |
328 | ||
329 | #ifdef CONFIG_TSEC2 | |
330 | #define CONFIG_HAS_ETH1 | |
255a3577 | 331 | #define CONFIG_TSEC2_NAME "TSEC1" |
89c7784e TT |
332 | #define CFG_TSEC2_OFFSET 0x25000 |
333 | #define TSEC2_PHY_ADDR 4 | |
334 | #define TSEC2_FLAGS TSEC_GIGABIT | |
335 | #define TSEC2_PHYIDX 0 | |
336 | #endif | |
337 | ||
96b8a054 SW |
338 | |
339 | /* Options are: TSEC[0-1] */ | |
340 | #define CONFIG_ETHPRIME "TSEC1" | |
341 | ||
342 | /* | |
343 | * Configure on-board RTC | |
344 | */ | |
345 | #define CONFIG_RTC_DS1337 | |
346 | #define CFG_I2C_RTC_ADDR 0x68 | |
347 | ||
348 | /* | |
349 | * Environment | |
350 | */ | |
351 | #ifndef CFG_RAMBOOT | |
352 | #define CFG_ENV_IS_IN_FLASH 1 | |
b2893e1f | 353 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
96b8a054 SW |
354 | #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
355 | #define CFG_ENV_SIZE 0x2000 | |
356 | ||
357 | /* Address and size of Redundant Environment Sector */ | |
358 | #else | |
359 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
360 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
361 | #define CFG_ENV_SIZE 0x2000 | |
362 | #endif | |
363 | ||
364 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
365 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
366 | ||
079a136c JL |
367 | /* |
368 | * BOOTP options | |
369 | */ | |
370 | #define CONFIG_BOOTP_BOOTFILESIZE | |
371 | #define CONFIG_BOOTP_BOOTPATH | |
372 | #define CONFIG_BOOTP_GATEWAY | |
373 | #define CONFIG_BOOTP_HOSTNAME | |
374 | ||
375 | ||
8ea5499a JL |
376 | /* |
377 | * Command line configuration. | |
378 | */ | |
379 | #include <config_cmd_default.h> | |
96b8a054 | 380 | |
8ea5499a JL |
381 | #define CONFIG_CMD_PING |
382 | #define CONFIG_CMD_DHCP | |
383 | #define CONFIG_CMD_I2C | |
384 | #define CONFIG_CMD_MII | |
385 | #define CONFIG_CMD_DATE | |
386 | #define CONFIG_CMD_PCI | |
96b8a054 SW |
387 | |
388 | #if defined(CFG_RAMBOOT) | |
8ea5499a JL |
389 | #undef CONFIG_CMD_ENV |
390 | #undef CONFIG_CMD_LOADS | |
96b8a054 SW |
391 | #endif |
392 | ||
8ea5499a JL |
393 | #define CONFIG_CMDLINE_EDITING 1 |
394 | ||
96b8a054 SW |
395 | |
396 | /* | |
397 | * Miscellaneous configurable options | |
398 | */ | |
399 | #define CFG_LONGHELP /* undef to save memory */ | |
400 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
401 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
402 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
403 | ||
a7676ea7 | 404 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
96b8a054 SW |
405 | #define CFG_MAXARGS 16 /* max number of command args */ |
406 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
407 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
408 | ||
409 | /* | |
410 | * For booting Linux, the board info and command line data | |
411 | * have to be in the first 8 MB of memory, since this is | |
412 | * the maximum mapped by the Linux kernel during initialization. | |
413 | */ | |
414 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
415 | ||
a7676ea7 | 416 | #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
96b8a054 SW |
417 | |
418 | #ifdef CFG_66MHZ | |
419 | ||
420 | /* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ | |
421 | /* 0x62040000 */ | |
422 | #define CFG_HRCW_LOW (\ | |
423 | 0x20000000 /* reserved, must be set */ |\ | |
424 | HRCWL_DDRCM |\ | |
425 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
426 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
427 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
428 | HRCWL_CORE_TO_CSB_2X1) | |
429 | ||
430 | #elif defined(CFG_33MHZ) | |
431 | ||
432 | /* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ | |
433 | /* 0x65040000 */ | |
434 | #define CFG_HRCW_LOW (\ | |
435 | 0x20000000 /* reserved, must be set */ |\ | |
436 | HRCWL_DDRCM |\ | |
437 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
438 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
439 | HRCWL_CSB_TO_CLKIN_5X1 |\ | |
440 | HRCWL_CORE_TO_CSB_2X1) | |
441 | ||
442 | #endif | |
443 | ||
444 | /* 0xa0606c00 */ | |
445 | #define CFG_HRCW_HIGH (\ | |
446 | HRCWH_PCI_HOST |\ | |
447 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
448 | HRCWH_CORE_ENABLE |\ | |
449 | HRCWH_FROM_0X00000100 |\ | |
450 | HRCWH_BOOTSEQ_DISABLE |\ | |
451 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
452 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
453 | HRCWH_RL_EXT_LEGACY |\ | |
454 | HRCWH_TSEC1M_IN_RGMII |\ | |
455 | HRCWH_TSEC2M_IN_RGMII |\ | |
456 | HRCWH_BIG_ENDIAN |\ | |
457 | HRCWH_LALE_NORMAL) | |
458 | ||
459 | /* System IO Config */ | |
a7676ea7 WD |
460 | #define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ |
461 | #define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */ | |
96b8a054 SW |
462 | |
463 | #define CFG_HID0_INIT 0x000000000 | |
464 | #define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
a7676ea7 | 465 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
96b8a054 SW |
466 | |
467 | #define CFG_HID2 HID2_HBE | |
468 | ||
469 | /* DDR @ 0x00000000 */ | |
470 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) | |
471 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
472 | ||
473 | /* PCI @ 0x80000000 */ | |
474 | #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10) | |
475 | #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
476 | #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
477 | #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
478 | ||
479 | /* PCI2 not supported on 8313 */ | |
480 | #define CFG_IBAT3L (0) | |
481 | #define CFG_IBAT3U (0) | |
482 | #define CFG_IBAT4L (0) | |
483 | #define CFG_IBAT4U (0) | |
484 | ||
485 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
486 | #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
487 | #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
488 | ||
489 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
490 | #define CFG_IBAT6L (0xF0000000 | BATL_PP_10) | |
491 | #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
492 | ||
493 | #define CFG_IBAT7L (0) | |
494 | #define CFG_IBAT7U (0) | |
495 | ||
496 | #define CFG_DBAT0L CFG_IBAT0L | |
497 | #define CFG_DBAT0U CFG_IBAT0U | |
498 | #define CFG_DBAT1L CFG_IBAT1L | |
499 | #define CFG_DBAT1U CFG_IBAT1U | |
500 | #define CFG_DBAT2L CFG_IBAT2L | |
501 | #define CFG_DBAT2U CFG_IBAT2U | |
502 | #define CFG_DBAT3L CFG_IBAT3L | |
503 | #define CFG_DBAT3U CFG_IBAT3U | |
504 | #define CFG_DBAT4L CFG_IBAT4L | |
505 | #define CFG_DBAT4U CFG_IBAT4U | |
506 | #define CFG_DBAT5L CFG_IBAT5L | |
507 | #define CFG_DBAT5U CFG_IBAT5U | |
508 | #define CFG_DBAT6L CFG_IBAT6L | |
509 | #define CFG_DBAT6U CFG_IBAT6U | |
510 | #define CFG_DBAT7L CFG_IBAT7L | |
511 | #define CFG_DBAT7U CFG_IBAT7U | |
512 | ||
513 | /* | |
514 | * Internal Definitions | |
515 | * | |
516 | * Boot Flags | |
517 | */ | |
518 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
519 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
520 | ||
521 | /* | |
522 | * Environment Configuration | |
523 | */ | |
524 | #define CONFIG_ENV_OVERWRITE | |
525 | ||
89c7784e | 526 | #ifdef CONFIG_HAS_ETH0 |
96b8a054 | 527 | #define CONFIG_ETHADDR 00:E0:0C:00:95:01 |
89c7784e TT |
528 | #endif |
529 | ||
530 | #ifdef CONFIG_HAS_ETH1 | |
96b8a054 | 531 | #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 |
89c7784e | 532 | #endif |
96b8a054 SW |
533 | |
534 | #define CONFIG_IPADDR 10.0.0.2 | |
535 | #define CONFIG_SERVERIP 10.0.0.1 | |
536 | #define CONFIG_GATEWAYIP 10.0.0.1 | |
537 | #define CONFIG_NETMASK 255.0.0.0 | |
538 | #define CONFIG_NETDEV eth1 | |
539 | ||
540 | #define CONFIG_HOSTNAME mpc8313erdb | |
541 | #define CONFIG_ROOTPATH /nfs/root/path | |
542 | #define CONFIG_BOOTFILE uImage | |
543 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
544 | #define CONFIG_FDTFILE mpc8313erdb.dtb | |
545 | ||
b2115757 | 546 | #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ |
96b8a054 SW |
547 | #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ |
548 | #define CONFIG_BAUDRATE 115200 | |
549 | ||
550 | #define XMK_STR(x) #x | |
551 | #define MK_STR(x) XMK_STR(x) | |
552 | ||
553 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
554 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ | |
555 | "ethprime=TSEC1\0" \ | |
556 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
557 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
558 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
559 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
560 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
561 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
562 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
563 | "fdtaddr=400000\0" \ | |
564 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ | |
565 | "console=ttyS0\0" \ | |
566 | "setbootargs=setenv bootargs " \ | |
567 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ | |
568 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ | |
569 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
570 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" | |
571 | ||
572 | #define CONFIG_NFSBOOTCOMMAND \ | |
573 | "setenv rootdev /dev/nfs;" \ | |
574 | "run setbootargs;" \ | |
575 | "run setipargs;" \ | |
576 | "tftp $loadaddr $bootfile;" \ | |
577 | "tftp $fdtaddr $fdtfile;" \ | |
578 | "bootm $loadaddr - $fdtaddr" | |
579 | ||
580 | #define CONFIG_RAMBOOTCOMMAND \ | |
581 | "setenv rootdev /dev/ram;" \ | |
582 | "run setbootargs;" \ | |
583 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
584 | "tftp $loadaddr $bootfile;" \ | |
585 | "tftp $fdtaddr $fdtfile;" \ | |
586 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
587 | ||
588 | #undef MK_STR | |
589 | #undef XMK_STR | |
590 | ||
591 | #endif /* __CONFIG_H */ |