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8bd522ce | 1 | /* |
e8d3ca8b | 2 | * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. |
8bd522ce DL |
3 | * |
4 | * Dave Liu <daveliu@freescale.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
8bd522ce DL |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
f1c574d4 SW |
12 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) |
13 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
14 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
15 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 | |
16 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
17 | ||
2ae18241 WD |
18 | #ifndef CONFIG_SYS_TEXT_BASE |
19 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 | |
2e95004d AV |
20 | #endif |
21 | ||
f1c574d4 SW |
22 | #ifndef CONFIG_SYS_MONITOR_BASE |
23 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
24 | #endif | |
25 | ||
8bd522ce DL |
26 | /* |
27 | * High Level Configuration Options | |
28 | */ | |
29 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af | 30 | #define CONFIG_MPC831x 1 /* MPC831x CPU family */ |
8bd522ce DL |
31 | #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ |
32 | #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ | |
33 | ||
34 | /* | |
35 | * System Clock Setup | |
36 | */ | |
37 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
38 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
39 | ||
40 | /* | |
41 | * Hardware Reset Configuration Word | |
42 | * if CLKIN is 66.66MHz, then | |
43 | * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz | |
44 | */ | |
6d0f6bcf | 45 | #define CONFIG_SYS_HRCW_LOW (\ |
8bd522ce DL |
46 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
47 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
48 | HRCWL_SVCOD_DIV_2 |\ | |
49 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
50 | HRCWL_CORE_TO_CSB_3X1) | |
2e95004d | 51 | #define CONFIG_SYS_HRCW_HIGH_BASE (\ |
8bd522ce DL |
52 | HRCWH_PCI_HOST |\ |
53 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
54 | HRCWH_CORE_ENABLE |\ | |
8bd522ce DL |
55 | HRCWH_BOOTSEQ_DISABLE |\ |
56 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
8bd522ce DL |
57 | HRCWH_TSEC1M_IN_RGMII |\ |
58 | HRCWH_TSEC2M_IN_RGMII |\ | |
59 | HRCWH_BIG_ENDIAN |\ | |
60 | HRCWH_LALE_NORMAL) | |
61 | ||
2e95004d AV |
62 | #ifdef CONFIG_NAND_SPL |
63 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ | |
64 | HRCWH_FROM_0XFFF00100 |\ | |
65 | HRCWH_ROM_LOC_NAND_SP_8BIT |\ | |
66 | HRCWH_RL_EXT_NAND) | |
67 | #else | |
68 | #define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ | |
69 | HRCWH_FROM_0X00000100 |\ | |
70 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
71 | HRCWH_RL_EXT_LEGACY) | |
72 | #endif | |
73 | ||
8bd522ce DL |
74 | /* |
75 | * System IO Config | |
76 | */ | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_SICRH 0x00000000 |
78 | #define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ | |
8bd522ce DL |
79 | |
80 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
b8b71ffb | 81 | #define CONFIG_HWCONFIG |
8bd522ce DL |
82 | |
83 | /* | |
84 | * IMMR new address | |
85 | */ | |
6d0f6bcf | 86 | #define CONFIG_SYS_IMMR 0xE0000000 |
8bd522ce DL |
87 | |
88 | /* | |
89 | * Arbiter Setup | |
90 | */ | |
6d0f6bcf | 91 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
6f681b73 JH |
92 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
93 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ | |
8bd522ce DL |
94 | |
95 | /* | |
96 | * DDR Setup | |
97 | */ | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
99 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
100 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
101 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
6f681b73 | 102 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ |
8bd522ce DL |
103 | | DDRCDR_PZ_LOZ \ |
104 | | DDRCDR_NZ_LOZ \ | |
105 | | DDRCDR_ODT \ | |
6f681b73 | 106 | | DDRCDR_Q_DRN) |
8bd522ce DL |
107 | /* 0x7b880001 */ |
108 | /* | |
109 | * Manually set up DDR parameters | |
110 | * consist of two chips HY5PS12621BFP-C4 from HYNIX | |
111 | */ | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ |
113 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 | |
6f681b73 | 114 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
2fef4020 JH |
115 | | CSCONFIG_ODT_RD_NEVER \ |
116 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
6f681b73 JH |
117 | | CSCONFIG_ROW_BIT_13 \ |
118 | | CSCONFIG_COL_BIT_10) | |
8bd522ce | 119 | /* 0x80010102 */ |
6d0f6bcf | 120 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
6f681b73 JH |
121 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
122 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
123 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
124 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
125 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
126 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
127 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
128 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
8bd522ce | 129 | /* 0x00220802 */ |
6f681b73 JH |
130 | #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ |
131 | | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
132 | | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
133 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
134 | | (6 << TIMING_CFG1_REFREC_SHIFT) \ | |
135 | | (2 << TIMING_CFG1_WRREC_SHIFT) \ | |
136 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
137 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
2f2a5c37 | 138 | /* 0x27256222 */ |
6f681b73 JH |
139 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
140 | | (4 << TIMING_CFG2_CPO_SHIFT) \ | |
141 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
142 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
143 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
144 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
145 | | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
2f2a5c37 | 146 | /* 0x121048c5 */ |
6f681b73 JH |
147 | #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
148 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
8bd522ce | 149 | /* 0x03600100 */ |
6f681b73 | 150 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
8bd522ce | 151 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
2fef4020 | 152 | | SDRAM_CFG_DBW_32) |
8bd522ce | 153 | /* 0x43080000 */ |
6d0f6bcf | 154 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ |
6f681b73 JH |
155 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ |
156 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) | |
8bd522ce | 157 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
6f681b73 | 158 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
8bd522ce DL |
159 | |
160 | /* | |
161 | * Memory test | |
162 | */ | |
6d0f6bcf JCPV |
163 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
164 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
165 | #define CONFIG_SYS_MEMTEST_END 0x00140000 | |
8bd522ce DL |
166 | |
167 | /* | |
168 | * The reserved memory | |
169 | */ | |
16c8c170 | 170 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
6f681b73 | 171 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
8bd522ce DL |
172 | |
173 | /* | |
174 | * Initial RAM Base Address Setup | |
175 | */ | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
177 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 178 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
6f681b73 JH |
179 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
180 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
8bd522ce DL |
181 | |
182 | /* | |
183 | * Local Bus Configuration & Clock Setup | |
184 | */ | |
c7190f02 KP |
185 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
186 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
6d0f6bcf | 187 | #define CONFIG_SYS_LBC_LBCR 0x00040000 |
0914f483 | 188 | #define CONFIG_FSL_ELBC 1 |
8bd522ce DL |
189 | |
190 | /* | |
191 | * FLASH on the Local Bus | |
192 | */ | |
6d0f6bcf | 193 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 194 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf | 195 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
8bd522ce | 196 | |
6d0f6bcf | 197 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
6f681b73 JH |
198 | #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ |
199 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
8bd522ce | 200 | |
6f681b73 JH |
201 | /* Window base at flash base */ |
202 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 203 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) |
8bd522ce | 204 | |
2e95004d | 205 | #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
206 | | BR_PS_16 /* 16 bit port */ \ |
207 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
208 | | BR_V) /* valid */ | |
209 | #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
210 | | OR_UPM_XAM \ | |
211 | | OR_GPCM_CSNT \ | |
212 | | OR_GPCM_ACS_DIV2 \ | |
213 | | OR_GPCM_XACS \ | |
214 | | OR_GPCM_SCY_15 \ | |
215 | | OR_GPCM_TRLX_SET \ | |
216 | | OR_GPCM_EHTR_SET \ | |
217 | | OR_GPCM_EAD) | |
8bd522ce | 218 | |
6d0f6bcf | 219 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
6f681b73 JH |
220 | /* 127 64KB sectors and 8 8KB top sectors per device */ |
221 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
8bd522ce | 222 | |
6d0f6bcf JCPV |
223 | #undef CONFIG_SYS_FLASH_CHECKSUM |
224 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
225 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
8bd522ce DL |
226 | |
227 | /* | |
228 | * NAND Flash on the Local Bus | |
229 | */ | |
2e95004d AV |
230 | |
231 | #ifdef CONFIG_NAND_SPL | |
232 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 | |
233 | #else | |
234 | #define CONFIG_SYS_NAND_BASE 0xE0600000 | |
235 | #endif | |
236 | ||
e8d3ca8b SW |
237 | #define CONFIG_MTD_DEVICE |
238 | #define CONFIG_MTD_PARTITION | |
239 | #define CONFIG_CMD_MTDPARTS | |
240 | #define MTDIDS_DEFAULT "nand0=e0600000.flash" | |
6f681b73 | 241 | #define MTDPARTS_DEFAULT \ |
63865278 | 242 | "mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)" |
e8d3ca8b | 243 | |
6d0f6bcf | 244 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
1ac5744e DL |
245 | #define CONFIG_CMD_NAND 1 |
246 | #define CONFIG_NAND_FSL_ELBC 1 | |
7d6a0982 JH |
247 | #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 |
248 | #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ | |
2e95004d AV |
249 | |
250 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) | |
251 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 | |
252 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 | |
253 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 | |
254 | #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 | |
8bd522ce | 255 | |
2e95004d | 256 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 | 257 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
6f681b73 | 258 | | BR_PS_8 /* 8 bit port */ \ |
8bd522ce | 259 | | BR_MS_FCM /* MSEL = FCM */ \ |
6f681b73 | 260 | | BR_V) /* valid */ |
7d6a0982 JH |
261 | #define CONFIG_SYS_NAND_OR_PRELIM \ |
262 | (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ | |
8bd522ce DL |
263 | | OR_FCM_CSCT \ |
264 | | OR_FCM_CST \ | |
265 | | OR_FCM_CHT \ | |
266 | | OR_FCM_SCY_1 \ | |
267 | | OR_FCM_TRLX \ | |
6f681b73 | 268 | | OR_FCM_EHTR) |
8bd522ce DL |
269 | /* 0xFFFF8396 */ |
270 | ||
2e95004d AV |
271 | #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM |
272 | #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM | |
273 | #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM | |
274 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM | |
2e95004d | 275 | |
6d0f6bcf | 276 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 277 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
8bd522ce | 278 | |
2e95004d AV |
279 | #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM |
280 | #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM | |
281 | ||
282 | #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ | |
283 | !defined(CONFIG_NAND_SPL) | |
284 | #define CONFIG_SYS_RAMBOOT | |
285 | #else | |
286 | #undef CONFIG_SYS_RAMBOOT | |
287 | #endif | |
288 | ||
8bd522ce DL |
289 | /* |
290 | * Serial Port | |
291 | */ | |
292 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
293 | #define CONFIG_SYS_NS16550_SERIAL |
294 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
2e95004d | 295 | #define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) |
8bd522ce | 296 | |
6d0f6bcf | 297 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
6f681b73 | 298 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
8bd522ce | 299 | |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
301 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
8bd522ce | 302 | |
8bd522ce | 303 | /* I2C */ |
00f792e0 HS |
304 | #define CONFIG_SYS_I2C |
305 | #define CONFIG_SYS_I2C_FSL | |
306 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
307 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
308 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
309 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
8bd522ce DL |
310 | |
311 | /* | |
312 | * Board info - revision and where boot from | |
313 | */ | |
6d0f6bcf | 314 | #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 |
8bd522ce DL |
315 | |
316 | /* | |
317 | * Config on-board RTC | |
318 | */ | |
319 | #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ | |
6d0f6bcf | 320 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
8bd522ce DL |
321 | |
322 | /* | |
323 | * General PCI | |
324 | * Addresses are mapped 1-1. | |
325 | */ | |
6f681b73 JH |
326 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
327 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
328 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
329 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
330 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
331 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
332 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
333 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
334 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
335 | ||
336 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE | |
337 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
338 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
8bd522ce | 339 | |
8f11e34b AV |
340 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
341 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 | |
342 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 | |
343 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
344 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 | |
345 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 | |
346 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
347 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 | |
348 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
349 | ||
350 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
351 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 | |
352 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 | |
353 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
354 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 | |
355 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 | |
356 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
357 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 | |
358 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
359 | ||
842033e6 | 360 | #define CONFIG_PCI_INDIRECT_BRIDGE |
be9b56df | 361 | #define CONFIG_PCIE |
8bd522ce | 362 | |
8bd522ce DL |
363 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
364 | ||
365 | #define CONFIG_EEPRO100 | |
366 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 367 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
8bd522ce | 368 | |
25f5f0d4 | 369 | #define CONFIG_HAS_FSL_DR_USB |
6823e9b0 VM |
370 | #define CONFIG_SYS_SCCR_USBDRCM 3 |
371 | ||
6823e9b0 VM |
372 | #define CONFIG_USB_EHCI |
373 | #define CONFIG_USB_EHCI_FSL | |
6f681b73 | 374 | #define CONFIG_USB_PHY_TYPE "utmi" |
6823e9b0 | 375 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
25f5f0d4 | 376 | |
8bd522ce DL |
377 | /* |
378 | * TSEC | |
379 | */ | |
380 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
6d0f6bcf | 381 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
6f681b73 | 382 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 383 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
6f681b73 | 384 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
8bd522ce DL |
385 | |
386 | /* | |
387 | * TSEC ethernet configuration | |
388 | */ | |
389 | #define CONFIG_MII 1 /* MII PHY management */ | |
390 | #define CONFIG_TSEC1 1 | |
391 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
392 | #define CONFIG_TSEC2 1 | |
393 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
394 | #define TSEC1_PHY_ADDR 0 | |
395 | #define TSEC2_PHY_ADDR 1 | |
396 | #define TSEC1_PHYIDX 0 | |
397 | #define TSEC2_PHYIDX 0 | |
398 | #define TSEC1_FLAGS TSEC_GIGABIT | |
399 | #define TSEC2_FLAGS TSEC_GIGABIT | |
400 | ||
401 | /* Options are: eTSEC[0-1] */ | |
402 | #define CONFIG_ETHPRIME "eTSEC1" | |
403 | ||
730e7929 KP |
404 | /* |
405 | * SATA | |
406 | */ | |
407 | #define CONFIG_LIBATA | |
408 | #define CONFIG_FSL_SATA | |
409 | ||
6d0f6bcf | 410 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
730e7929 | 411 | #define CONFIG_SATA1 |
6d0f6bcf | 412 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
6f681b73 JH |
413 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
414 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
730e7929 | 415 | #define CONFIG_SATA2 |
6d0f6bcf | 416 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
6f681b73 JH |
417 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
418 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
730e7929 KP |
419 | |
420 | #ifdef CONFIG_FSL_SATA | |
421 | #define CONFIG_LBA48 | |
422 | #define CONFIG_CMD_SATA | |
423 | #define CONFIG_DOS_PARTITION | |
730e7929 KP |
424 | #endif |
425 | ||
8bd522ce DL |
426 | /* |
427 | * Environment | |
428 | */ | |
d0fb0fce | 429 | #if !defined(CONFIG_SYS_RAMBOOT) |
5a1aceb0 | 430 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6f681b73 JH |
431 | #define CONFIG_ENV_ADDR \ |
432 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
433 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
434 | #define CONFIG_ENV_SIZE 0x2000 | |
8bd522ce | 435 | #else |
6f681b73 | 436 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 437 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 438 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 439 | #define CONFIG_ENV_SIZE 0x2000 |
8bd522ce DL |
440 | #endif |
441 | ||
442 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 443 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
8bd522ce DL |
444 | |
445 | /* | |
446 | * BOOTP options | |
447 | */ | |
448 | #define CONFIG_BOOTP_BOOTFILESIZE | |
449 | #define CONFIG_BOOTP_BOOTPATH | |
450 | #define CONFIG_BOOTP_GATEWAY | |
451 | #define CONFIG_BOOTP_HOSTNAME | |
452 | ||
453 | /* | |
454 | * Command line configuration. | |
455 | */ | |
8bd522ce DL |
456 | #define CONFIG_CMD_DATE |
457 | #define CONFIG_CMD_PCI | |
458 | ||
8bd522ce | 459 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
6f681b73 | 460 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
8bd522ce DL |
461 | |
462 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
463 | ||
464 | /* | |
465 | * Miscellaneous configurable options | |
466 | */ | |
6d0f6bcf JCPV |
467 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
468 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
8bd522ce DL |
469 | |
470 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 471 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
8bd522ce | 472 | #else |
6d0f6bcf | 473 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
8bd522ce DL |
474 | #endif |
475 | ||
6f681b73 JH |
476 | /* Print Buffer Size */ |
477 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
478 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
479 | /* Boot Argument Buffer Size */ | |
480 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
8bd522ce DL |
481 | |
482 | /* | |
483 | * For booting Linux, the board info and command line data | |
9f530d59 | 484 | * have to be in the first 256 MB of memory, since this is |
8bd522ce DL |
485 | * the maximum mapped by the Linux kernel during initialization. |
486 | */ | |
6f681b73 | 487 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
63865278 | 488 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
8bd522ce DL |
489 | |
490 | /* | |
491 | * Core HID Setup | |
492 | */ | |
1a2e203b KP |
493 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
494 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
495 | HID0_ENABLE_INSTRUCTION_CACHE | \ | |
8bd522ce | 496 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) |
6d0f6bcf | 497 | #define CONFIG_SYS_HID2 HID2_HBE |
8bd522ce DL |
498 | |
499 | /* | |
500 | * MMU Setup | |
501 | */ | |
31d82672 | 502 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
8bd522ce DL |
503 | |
504 | /* DDR: cache cacheable */ | |
6f681b73 | 505 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 506 | | BATL_PP_RW \ |
6f681b73 JH |
507 | | BATL_MEMCOHERENCE) |
508 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
509 | | BATU_BL_128M \ | |
510 | | BATU_VS \ | |
511 | | BATU_VP) | |
6d0f6bcf JCPV |
512 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
513 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
8bd522ce DL |
514 | |
515 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
6f681b73 | 516 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
72cd4087 | 517 | | BATL_PP_RW \ |
6f681b73 JH |
518 | | BATL_CACHEINHIBIT \ |
519 | | BATL_GUARDEDSTORAGE) | |
520 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ | |
521 | | BATU_BL_8M \ | |
522 | | BATU_VS \ | |
523 | | BATU_VP) | |
6d0f6bcf JCPV |
524 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
525 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
8bd522ce DL |
526 | |
527 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
6f681b73 | 528 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 529 | | BATL_PP_RW \ |
6f681b73 JH |
530 | | BATL_MEMCOHERENCE) |
531 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ | |
532 | | BATU_BL_32M \ | |
533 | | BATU_VS \ | |
534 | | BATU_VP) | |
535 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 536 | | BATL_PP_RW \ |
6f681b73 JH |
537 | | BATL_CACHEINHIBIT \ |
538 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 539 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
8bd522ce DL |
540 | |
541 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 542 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
6f681b73 JH |
543 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \ |
544 | | BATU_BL_128K \ | |
545 | | BATU_VS \ | |
546 | | BATU_VP) | |
6d0f6bcf JCPV |
547 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
548 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
8bd522ce DL |
549 | |
550 | /* PCI MEM space: cacheable */ | |
6f681b73 | 551 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 552 | | BATL_PP_RW \ |
6f681b73 JH |
553 | | BATL_MEMCOHERENCE) |
554 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \ | |
555 | | BATU_BL_256M \ | |
556 | | BATU_VS \ | |
557 | | BATU_VP) | |
6d0f6bcf JCPV |
558 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
559 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
8bd522ce DL |
560 | |
561 | /* PCI MMIO space: cache-inhibit and guarded */ | |
6f681b73 | 562 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 563 | | BATL_PP_RW \ |
6f681b73 JH |
564 | | BATL_CACHEINHIBIT \ |
565 | | BATL_GUARDEDSTORAGE) | |
566 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
567 | | BATU_BL_256M \ | |
568 | | BATU_VS \ | |
569 | | BATU_VP) | |
6d0f6bcf JCPV |
570 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
571 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
572 | ||
573 | #define CONFIG_SYS_IBAT6L 0 | |
574 | #define CONFIG_SYS_IBAT6U 0 | |
575 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
576 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
577 | ||
578 | #define CONFIG_SYS_IBAT7L 0 | |
579 | #define CONFIG_SYS_IBAT7U 0 | |
580 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
581 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
8bd522ce | 582 | |
8bd522ce DL |
583 | #if defined(CONFIG_CMD_KGDB) |
584 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
8bd522ce DL |
585 | #endif |
586 | ||
587 | /* | |
588 | * Environment Configuration | |
589 | */ | |
590 | ||
591 | #define CONFIG_ENV_OVERWRITE | |
592 | ||
593 | #if defined(CONFIG_TSEC_ENET) | |
594 | #define CONFIG_HAS_ETH0 | |
8bd522ce | 595 | #define CONFIG_HAS_ETH1 |
8bd522ce DL |
596 | #endif |
597 | ||
598 | #define CONFIG_BAUDRATE 115200 | |
599 | ||
79f516bc | 600 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
8bd522ce | 601 | |
8bd522ce DL |
602 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
603 | ||
604 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
6f681b73 JH |
605 | "netdev=eth0\0" \ |
606 | "consoledev=ttyS0\0" \ | |
607 | "ramdiskaddr=1000000\0" \ | |
608 | "ramdiskfile=ramfs.83xx\0" \ | |
609 | "fdtaddr=780000\0" \ | |
610 | "fdtfile=mpc8315erdb.dtb\0" \ | |
611 | "usb_phy_type=utmi\0" \ | |
612 | "" | |
8bd522ce DL |
613 | |
614 | #define CONFIG_NFSBOOTCOMMAND \ | |
6f681b73 JH |
615 | "setenv bootargs root=/dev/nfs rw " \ |
616 | "nfsroot=$serverip:$rootpath " \ | |
617 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
618 | "$netdev:off " \ | |
619 | "console=$consoledev,$baudrate $othbootargs;" \ | |
620 | "tftp $loadaddr $bootfile;" \ | |
621 | "tftp $fdtaddr $fdtfile;" \ | |
622 | "bootm $loadaddr - $fdtaddr" | |
8bd522ce DL |
623 | |
624 | #define CONFIG_RAMBOOTCOMMAND \ | |
6f681b73 JH |
625 | "setenv bootargs root=/dev/ram rw " \ |
626 | "console=$consoledev,$baudrate $othbootargs;" \ | |
627 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
628 | "tftp $loadaddr $bootfile;" \ | |
629 | "tftp $fdtaddr $fdtfile;" \ | |
630 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
8bd522ce | 631 | |
8bd522ce DL |
632 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
633 | ||
634 | #endif /* __CONFIG_H */ |