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991425fe MB |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * mpc8349emds board configuration file | |
26 | * | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
991425fe MB |
32 | /* |
33 | * High Level Configuration Options | |
34 | */ | |
35 | #define CONFIG_E300 1 /* E300 Family */ | |
0f898604 | 36 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
2c7920af | 37 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
991425fe MB |
38 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
39 | #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ | |
40 | ||
991425fe MB |
41 | #define PCI_66M |
42 | #ifdef PCI_66M | |
43 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
44 | #else | |
45 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
46 | #endif | |
47 | ||
447ad576 IS |
48 | #ifdef CONFIG_PCISLAVE |
49 | #define CONFIG_PCI | |
50 | #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ | |
51 | #endif /* CONFIG_PCISLAVE */ | |
52 | ||
991425fe MB |
53 | #ifndef CONFIG_SYS_CLK_FREQ |
54 | #ifdef PCI_66M | |
55 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
8fe9bf61 | 56 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
991425fe MB |
57 | #else |
58 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
8fe9bf61 | 59 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
991425fe MB |
60 | #endif |
61 | #endif | |
62 | ||
63 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
64 | ||
6d0f6bcf | 65 | #define CONFIG_SYS_IMMR 0xE0000000 |
991425fe | 66 | |
6d0f6bcf JCPV |
67 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
68 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
69 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
991425fe MB |
70 | |
71 | /* | |
72 | * DDR Setup | |
73 | */ | |
8d172c0f | 74 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
d326f4a2 | 75 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
991425fe MB |
76 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
77 | ||
dc9e499c RJ |
78 | /* |
79 | * 32-bit data path mode. | |
cf48eb9a | 80 | * |
dc9e499c RJ |
81 | * Please note that using this mode for devices with the real density of 64-bit |
82 | * effectively reduces the amount of available memory due to the effect of | |
83 | * wrapping around while translating address to row/columns, for example in the | |
84 | * 256MB module the upper 128MB get aliased with contents of the lower | |
85 | * 128MB); normally this define should be used for devices with real 32-bit | |
cf48eb9a | 86 | * data path. |
dc9e499c RJ |
87 | */ |
88 | #undef CONFIG_DDR_32BIT | |
89 | ||
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
91 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
92 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
93 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ | |
8d172c0f | 94 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
991425fe MB |
95 | #undef CONFIG_DDR_2T_TIMING |
96 | ||
8d172c0f XX |
97 | /* |
98 | * DDRCDR - DDR Control Driver Register | |
99 | */ | |
6d0f6bcf | 100 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
8d172c0f | 101 | |
991425fe | 102 | #if defined(CONFIG_SPD_EEPROM) |
dc9e499c RJ |
103 | /* |
104 | * Determine DDR configuration from I2C interface. | |
105 | */ | |
106 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
991425fe | 107 | #else |
dc9e499c RJ |
108 | /* |
109 | * Manually set up DDR parameters | |
110 | */ | |
6d0f6bcf | 111 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
8d172c0f | 112 | #if defined(CONFIG_DDR_II) |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_DDRCDR 0x80080001 |
114 | #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f | |
115 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 | |
116 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 | |
117 | #define CONFIG_SYS_DDR_TIMING_1 0x38357322 | |
118 | #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 | |
119 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
120 | #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 | |
121 | #define CONFIG_SYS_DDR_MODE 0x47d00432 | |
122 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
123 | #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 | |
124 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 | |
125 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
8d172c0f | 126 | #else |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
128 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 | |
129 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
130 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
131 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ | |
dc9e499c RJ |
132 | |
133 | #if defined(CONFIG_DDR_32BIT) | |
134 | /* set burst length to 8 for 32-bit data path */ | |
6d0f6bcf | 135 | #define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ |
dc9e499c RJ |
136 | #else |
137 | /* the default burst length is 4 - for 64-bit data path */ | |
6d0f6bcf | 138 | #define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ |
dc9e499c | 139 | #endif |
991425fe | 140 | #endif |
8d172c0f | 141 | #endif |
991425fe MB |
142 | |
143 | /* | |
144 | * SDRAM on the Local Bus | |
145 | */ | |
6d0f6bcf JCPV |
146 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
147 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
991425fe MB |
148 | |
149 | /* | |
150 | * FLASH on the Local Bus | |
151 | */ | |
6d0f6bcf | 152 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 153 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
155 | #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ | |
156 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
157 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ | |
991425fe | 158 | |
6d0f6bcf | 159 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ |
8d172c0f | 160 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ |
991425fe | 161 | BR_V) /* valid */ |
6d0f6bcf | 162 | #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ |
f9023afb | 163 | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ |
8d172c0f | 164 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ |
166 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ | |
991425fe | 167 | |
6d0f6bcf JCPV |
168 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
169 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
991425fe | 170 | |
6d0f6bcf JCPV |
171 | #undef CONFIG_SYS_FLASH_CHECKSUM |
172 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
173 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
991425fe | 174 | |
14d0a02a | 175 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
991425fe | 176 | |
6d0f6bcf JCPV |
177 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
178 | #define CONFIG_SYS_RAMBOOT | |
991425fe | 179 | #else |
6d0f6bcf | 180 | #undef CONFIG_SYS_RAMBOOT |
991425fe MB |
181 | #endif |
182 | ||
183 | /* | |
184 | * BCSR register on local bus 32KB, 8-bit wide for MDS config reg | |
185 | */ | |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_BCSR 0xE2400000 |
187 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ | |
188 | #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ | |
189 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ | |
190 | #define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ | |
991425fe | 191 | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
193 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
194 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
991425fe | 195 | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
197 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
198 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
991425fe | 199 | |
4a9932a4 | 200 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
6d0f6bcf | 201 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
991425fe MB |
202 | |
203 | /* | |
204 | * Local Bus LCRR and LBCR regs | |
205 | * LCRR: DLL bypass, Clock divider is 4 | |
206 | * External Local Bus rate is | |
207 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
208 | */ | |
c7190f02 KP |
209 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
210 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 211 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
991425fe | 212 | |
8d172c0f XX |
213 | /* |
214 | * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. | |
6d0f6bcf | 215 | * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM |
8d172c0f | 216 | */ |
6d0f6bcf | 217 | #undef CONFIG_SYS_LB_SDRAM |
991425fe | 218 | |
6d0f6bcf | 219 | #ifdef CONFIG_SYS_LB_SDRAM |
991425fe MB |
220 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ |
221 | /* | |
222 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 223 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
991425fe MB |
224 | * |
225 | * For BR2, need: | |
226 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
227 | * port-size = 32-bits = BR2[19:20] = 11 | |
228 | * no parity checking = BR2[21:22] = 00 | |
229 | * SDRAM for MSEL = BR2[24:26] = 011 | |
230 | * Valid = BR[31] = 1 | |
231 | * | |
232 | * 0 4 8 12 16 20 24 28 | |
233 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
234 | * | |
6d0f6bcf | 235 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
991425fe MB |
236 | * FIXME: the top 17 bits of BR2. |
237 | */ | |
238 | ||
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ |
240 | #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 | |
241 | #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ | |
991425fe MB |
242 | |
243 | /* | |
6d0f6bcf | 244 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
991425fe MB |
245 | * |
246 | * For OR2, need: | |
247 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
248 | * XAM, OR2[17:18] = 11 | |
249 | * 9 columns OR2[19-21] = 010 | |
250 | * 13 rows OR2[23-25] = 100 | |
251 | * EAD set for extra time OR[31] = 1 | |
252 | * | |
253 | * 0 4 8 12 16 20 24 28 | |
254 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
255 | */ | |
256 | ||
6d0f6bcf | 257 | #define CONFIG_SYS_OR2_PRELIM 0xFC006901 |
991425fe | 258 | |
6d0f6bcf JCPV |
259 | #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
260 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ | |
991425fe | 261 | |
540dcf1c KG |
262 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \ |
263 | | LSDMR_BSMA1516 \ | |
264 | | LSDMR_RFCR8 \ | |
265 | | LSDMR_PRETOACT6 \ | |
266 | | LSDMR_ACTTORW3 \ | |
267 | | LSDMR_BL8 \ | |
268 | | LSDMR_WRC3 \ | |
269 | | LSDMR_CL3 \ | |
991425fe MB |
270 | ) |
271 | ||
272 | /* | |
273 | * SDRAM Controller configuration sequence. | |
274 | */ | |
540dcf1c KG |
275 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
276 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
277 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
278 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
279 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
991425fe MB |
280 | #endif |
281 | ||
282 | /* | |
283 | * Serial Port | |
284 | */ | |
285 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_NS16550 |
287 | #define CONFIG_SYS_NS16550_SERIAL | |
288 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
289 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
991425fe | 290 | |
6d0f6bcf | 291 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
991425fe MB |
292 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
293 | ||
6d0f6bcf JCPV |
294 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
295 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
991425fe | 296 | |
22d71a71 | 297 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a059e90e | 298 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
991425fe | 299 | /* Use the HUSH parser */ |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_HUSH_PARSER |
301 | #ifdef CONFIG_SYS_HUSH_PARSER | |
302 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
991425fe MB |
303 | #endif |
304 | ||
bf0b542d | 305 | /* pass open firmware flat tree */ |
35cc4e48 | 306 | #define CONFIG_OF_LIBFDT 1 |
bf0b542d | 307 | #define CONFIG_OF_BOARD_SETUP 1 |
5b8bc606 | 308 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
bf0b542d | 309 | |
991425fe MB |
310 | /* I2C */ |
311 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
312 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
be5e6181 | 313 | #define CONFIG_FSL_I2C |
b24f119d | 314 | #define CONFIG_I2C_MULTI_BUS |
6d0f6bcf JCPV |
315 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
316 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
317 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
318 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
319 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
991425fe | 320 | |
80ddd226 | 321 | /* SPI */ |
8931ab17 | 322 | #define CONFIG_MPC8XXX_SPI |
80ddd226 | 323 | #undef CONFIG_SOFT_SPI /* SPI bit-banged */ |
80ddd226 BW |
324 | |
325 | /* GPIOs. Used as SPI chip selects */ | |
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_GPIO1_PRELIM |
327 | #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ | |
328 | #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ | |
80ddd226 | 329 | |
991425fe | 330 | /* TSEC */ |
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
332 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) | |
333 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
334 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) | |
991425fe | 335 | |
8fe9bf61 | 336 | /* USB */ |
6d0f6bcf | 337 | #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ |
991425fe MB |
338 | |
339 | /* | |
340 | * General PCI | |
341 | * Addresses are mapped 1-1. | |
342 | */ | |
6d0f6bcf JCPV |
343 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
344 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
345 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
346 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
347 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
348 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
349 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
350 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
351 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
352 | ||
353 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
354 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
355 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
356 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
357 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
358 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
359 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 | |
360 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
361 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
991425fe MB |
362 | |
363 | #if defined(CONFIG_PCI) | |
364 | ||
8fe9bf61 | 365 | #define PCI_ONE_PCI1 |
991425fe MB |
366 | #if defined(PCI_64BIT) |
367 | #undef PCI_ALL_PCI1 | |
368 | #undef PCI_TWO_PCI1 | |
369 | #undef PCI_ONE_PCI1 | |
370 | #endif | |
371 | ||
372 | #define CONFIG_NET_MULTI | |
373 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
162338e1 | 374 | #define CONFIG_83XX_PCI_STREAMING |
991425fe MB |
375 | |
376 | #undef CONFIG_EEPRO100 | |
377 | #undef CONFIG_TULIP | |
378 | ||
379 | #if !defined(CONFIG_PCI_PNP) | |
380 | #define PCI_ENET0_IOADDR 0xFIXME | |
381 | #define PCI_ENET0_MEMADDR 0xFIXME | |
53677ef1 | 382 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
991425fe MB |
383 | #endif |
384 | ||
385 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 386 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
991425fe MB |
387 | |
388 | #endif /* CONFIG_PCI */ | |
389 | ||
390 | /* | |
391 | * TSEC configuration | |
392 | */ | |
393 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
394 | ||
395 | #if defined(CONFIG_TSEC_ENET) | |
396 | #ifndef CONFIG_NET_MULTI | |
397 | #define CONFIG_NET_MULTI 1 | |
398 | #endif | |
399 | ||
400 | #define CONFIG_GMII 1 /* MII PHY management */ | |
255a3577 KP |
401 | #define CONFIG_TSEC1 1 |
402 | #define CONFIG_TSEC1_NAME "TSEC0" | |
403 | #define CONFIG_TSEC2 1 | |
404 | #define CONFIG_TSEC2_NAME "TSEC1" | |
991425fe MB |
405 | #define TSEC1_PHY_ADDR 0 |
406 | #define TSEC2_PHY_ADDR 1 | |
407 | #define TSEC1_PHYIDX 0 | |
408 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
409 | #define TSEC1_FLAGS TSEC_GIGABIT |
410 | #define TSEC2_FLAGS TSEC_GIGABIT | |
991425fe MB |
411 | |
412 | /* Options are: TSEC[0-1] */ | |
413 | #define CONFIG_ETHPRIME "TSEC0" | |
414 | ||
415 | #endif /* CONFIG_TSEC_ENET */ | |
416 | ||
417 | /* | |
418 | * Configure on-board RTC | |
419 | */ | |
420 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 421 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
991425fe MB |
422 | |
423 | /* | |
424 | * Environment | |
425 | */ | |
6d0f6bcf | 426 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 427 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 428 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
429 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
430 | #define CONFIG_ENV_SIZE 0x2000 | |
991425fe MB |
431 | |
432 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
433 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
434 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
991425fe MB |
435 | |
436 | #else | |
6d0f6bcf | 437 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 438 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 439 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 440 | #define CONFIG_ENV_SIZE 0x2000 |
991425fe MB |
441 | #endif |
442 | ||
443 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 444 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
991425fe | 445 | |
8ea5499a | 446 | |
659e2f67 JL |
447 | /* |
448 | * BOOTP options | |
449 | */ | |
450 | #define CONFIG_BOOTP_BOOTFILESIZE | |
451 | #define CONFIG_BOOTP_BOOTPATH | |
452 | #define CONFIG_BOOTP_GATEWAY | |
453 | #define CONFIG_BOOTP_HOSTNAME | |
454 | ||
455 | ||
8ea5499a JL |
456 | /* |
457 | * Command line configuration. | |
458 | */ | |
459 | #include <config_cmd_default.h> | |
460 | ||
461 | #define CONFIG_CMD_PING | |
462 | #define CONFIG_CMD_I2C | |
463 | #define CONFIG_CMD_DATE | |
464 | #define CONFIG_CMD_MII | |
465 | ||
991425fe | 466 | #if defined(CONFIG_PCI) |
8ea5499a | 467 | #define CONFIG_CMD_PCI |
991425fe | 468 | #endif |
8ea5499a | 469 | |
6d0f6bcf | 470 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 471 | #undef CONFIG_CMD_SAVEENV |
8ea5499a | 472 | #undef CONFIG_CMD_LOADS |
991425fe MB |
473 | #endif |
474 | ||
991425fe MB |
475 | |
476 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
477 | ||
478 | /* | |
479 | * Miscellaneous configurable options | |
480 | */ | |
6d0f6bcf JCPV |
481 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
482 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
483 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
991425fe | 484 | |
8ea5499a | 485 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 486 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
991425fe | 487 | #else |
6d0f6bcf | 488 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
991425fe MB |
489 | #endif |
490 | ||
6d0f6bcf JCPV |
491 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
492 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
493 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
494 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
991425fe MB |
495 | |
496 | /* | |
497 | * For booting Linux, the board info and command line data | |
9f530d59 | 498 | * have to be in the first 256 MB of memory, since this is |
991425fe MB |
499 | * the maximum mapped by the Linux kernel during initialization. |
500 | */ | |
9f530d59 | 501 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
991425fe | 502 | |
6d0f6bcf | 503 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
991425fe MB |
504 | |
505 | #if 1 /*528/264*/ | |
6d0f6bcf | 506 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
507 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
508 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 509 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
510 | HRCWL_VCO_1X2 |\ |
511 | HRCWL_CORE_TO_CSB_2X1) | |
512 | #elif 0 /*396/132*/ | |
6d0f6bcf | 513 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
514 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
515 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 516 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
517 | HRCWL_VCO_1X4 |\ |
518 | HRCWL_CORE_TO_CSB_3X1) | |
519 | #elif 0 /*264/132*/ | |
6d0f6bcf | 520 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
521 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
522 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 523 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
524 | HRCWL_VCO_1X4 |\ |
525 | HRCWL_CORE_TO_CSB_2X1) | |
526 | #elif 0 /*132/132*/ | |
6d0f6bcf | 527 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
528 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
529 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 530 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
531 | HRCWL_VCO_1X4 |\ |
532 | HRCWL_CORE_TO_CSB_1X1) | |
533 | #elif 0 /*264/264 */ | |
6d0f6bcf | 534 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
535 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
536 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 537 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
538 | HRCWL_VCO_1X4 |\ |
539 | HRCWL_CORE_TO_CSB_1X1) | |
540 | #endif | |
541 | ||
447ad576 | 542 | #ifdef CONFIG_PCISLAVE |
6d0f6bcf | 543 | #define CONFIG_SYS_HRCW_HIGH (\ |
447ad576 IS |
544 | HRCWH_PCI_AGENT |\ |
545 | HRCWH_64_BIT_PCI |\ | |
546 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
547 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
548 | HRCWH_CORE_ENABLE |\ | |
549 | HRCWH_FROM_0X00000100 |\ | |
550 | HRCWH_BOOTSEQ_DISABLE |\ | |
551 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
552 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
553 | HRCWH_TSEC1M_IN_GMII |\ | |
554 | HRCWH_TSEC2M_IN_GMII ) | |
555 | #else | |
991425fe | 556 | #if defined(PCI_64BIT) |
6d0f6bcf | 557 | #define CONFIG_SYS_HRCW_HIGH (\ |
991425fe MB |
558 | HRCWH_PCI_HOST |\ |
559 | HRCWH_64_BIT_PCI |\ | |
560 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
561 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
562 | HRCWH_CORE_ENABLE |\ | |
563 | HRCWH_FROM_0X00000100 |\ | |
564 | HRCWH_BOOTSEQ_DISABLE |\ | |
565 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
566 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
567 | HRCWH_TSEC1M_IN_GMII |\ | |
568 | HRCWH_TSEC2M_IN_GMII ) | |
569 | #else | |
6d0f6bcf | 570 | #define CONFIG_SYS_HRCW_HIGH (\ |
991425fe MB |
571 | HRCWH_PCI_HOST |\ |
572 | HRCWH_32_BIT_PCI |\ | |
573 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
574 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
575 | HRCWH_CORE_ENABLE |\ | |
576 | HRCWH_FROM_0X00000100 |\ | |
577 | HRCWH_BOOTSEQ_DISABLE |\ | |
578 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
579 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
580 | HRCWH_TSEC1M_IN_GMII |\ | |
581 | HRCWH_TSEC2M_IN_GMII ) | |
447ad576 IS |
582 | #endif /* PCI_64BIT */ |
583 | #endif /* CONFIG_PCISLAVE */ | |
991425fe | 584 | |
a5fe514e LN |
585 | /* |
586 | * System performance | |
587 | */ | |
6d0f6bcf JCPV |
588 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
589 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
590 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ | |
591 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
592 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
593 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
a5fe514e | 594 | |
991425fe | 595 | /* System IO Config */ |
3c9b1ee1 | 596 | #define CONFIG_SYS_SICRH 0 |
6d0f6bcf | 597 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
991425fe | 598 | |
6d0f6bcf | 599 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
1a2e203b KP |
600 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ |
601 | HID0_ENABLE_INSTRUCTION_CACHE) | |
991425fe | 602 | |
6d0f6bcf | 603 | /* #define CONFIG_SYS_HID0_FINAL (\ |
991425fe MB |
604 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
605 | HID0_ENABLE_M_BIT |\ | |
606 | HID0_ENABLE_ADDRESS_BROADCAST ) */ | |
607 | ||
608 | ||
6d0f6bcf | 609 | #define CONFIG_SYS_HID2 HID2_HBE |
31d82672 | 610 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
991425fe MB |
611 | |
612 | /* DDR @ 0x00000000 */ | |
6d0f6bcf JCPV |
613 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
614 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
991425fe MB |
615 | |
616 | /* PCI @ 0x80000000 */ | |
617 | #ifdef CONFIG_PCI | |
6d0f6bcf JCPV |
618 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
619 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
620 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
621 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
991425fe | 622 | #else |
6d0f6bcf JCPV |
623 | #define CONFIG_SYS_IBAT1L (0) |
624 | #define CONFIG_SYS_IBAT1U (0) | |
625 | #define CONFIG_SYS_IBAT2L (0) | |
626 | #define CONFIG_SYS_IBAT2U (0) | |
991425fe MB |
627 | #endif |
628 | ||
8fe9bf61 | 629 | #ifdef CONFIG_MPC83XX_PCI2 |
6d0f6bcf JCPV |
630 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
631 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
632 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
633 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
8fe9bf61 | 634 | #else |
6d0f6bcf JCPV |
635 | #define CONFIG_SYS_IBAT3L (0) |
636 | #define CONFIG_SYS_IBAT3U (0) | |
637 | #define CONFIG_SYS_IBAT4L (0) | |
638 | #define CONFIG_SYS_IBAT4U (0) | |
8fe9bf61 | 639 | #endif |
991425fe | 640 | |
8fe9bf61 | 641 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
6d0f6bcf JCPV |
642 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
643 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
991425fe | 644 | |
8fe9bf61 | 645 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
c1230980 SW |
646 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ |
647 | BATL_GUARDEDSTORAGE) | |
6d0f6bcf JCPV |
648 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
649 | ||
650 | #define CONFIG_SYS_IBAT7L (0) | |
651 | #define CONFIG_SYS_IBAT7U (0) | |
652 | ||
653 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
654 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
655 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
656 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
657 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
658 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
659 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
660 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
661 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
662 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
663 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
664 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
665 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
666 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
667 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
668 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
991425fe MB |
669 | |
670 | /* | |
671 | * Internal Definitions | |
672 | * | |
673 | * Boot Flags | |
674 | */ | |
675 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
676 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
677 | ||
8ea5499a | 678 | #if defined(CONFIG_CMD_KGDB) |
991425fe MB |
679 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
680 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
681 | #endif | |
682 | ||
683 | /* | |
684 | * Environment Configuration | |
685 | */ | |
686 | #define CONFIG_ENV_OVERWRITE | |
687 | ||
688 | #if defined(CONFIG_TSEC_ENET) | |
991425fe | 689 | #define CONFIG_HAS_ETH1 |
10327dc5 | 690 | #define CONFIG_HAS_ETH0 |
991425fe MB |
691 | #endif |
692 | ||
991425fe | 693 | #define CONFIG_HOSTNAME mpc8349emds |
bf0b542d KP |
694 | #define CONFIG_ROOTPATH /nfsroot/rootfs |
695 | #define CONFIG_BOOTFILE uImage | |
991425fe | 696 | |
79f516bc | 697 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
991425fe MB |
698 | |
699 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
700 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
701 | ||
702 | #define CONFIG_BAUDRATE 115200 | |
703 | ||
704 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 705 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
991425fe MB |
706 | "echo" |
707 | ||
708 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
709 | "netdev=eth0\0" \ | |
710 | "hostname=mpc8349emds\0" \ | |
711 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
712 | "nfsroot=${serverip}:${rootpath}\0" \ | |
713 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
714 | "addip=setenv bootargs ${bootargs} " \ | |
715 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
716 | ":${hostname}:${netdev}:off panic=1\0" \ | |
717 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
718 | "flash_nfs=run nfsargs addip addtty;" \ | |
719 | "bootm ${kernel_addr}\0" \ | |
720 | "flash_self=run ramargs addip addtty;" \ | |
721 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
722 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
723 | "bootm\0" \ | |
991425fe MB |
724 | "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ |
725 | "update=protect off fe000000 fe03ffff; " \ | |
726 | "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ | |
d8ab58b2 | 727 | "upd=run load update\0" \ |
79f516bc | 728 | "fdtaddr=780000\0" \ |
cc861f71 | 729 | "fdtfile=mpc834x_mds.dtb\0" \ |
991425fe MB |
730 | "" |
731 | ||
bf0b542d KP |
732 | #define CONFIG_NFSBOOTCOMMAND \ |
733 | "setenv bootargs root=/dev/nfs rw " \ | |
734 | "nfsroot=$serverip:$rootpath " \ | |
735 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
736 | "console=$consoledev,$baudrate $othbootargs;" \ | |
737 | "tftp $loadaddr $bootfile;" \ | |
738 | "tftp $fdtaddr $fdtfile;" \ | |
739 | "bootm $loadaddr - $fdtaddr" | |
740 | ||
741 | #define CONFIG_RAMBOOTCOMMAND \ | |
742 | "setenv bootargs root=/dev/ram rw " \ | |
743 | "console=$consoledev,$baudrate $othbootargs;" \ | |
744 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
745 | "tftp $loadaddr $bootfile;" \ | |
746 | "tftp $fdtaddr $fdtfile;" \ | |
747 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
748 | ||
991425fe MB |
749 | #define CONFIG_BOOTCOMMAND "run flash_self" |
750 | ||
751 | #endif /* __CONFIG_H */ |