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991425fe MB |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * mpc8349emds board configuration file | |
26 | * | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
991425fe MB |
32 | #undef DEBUG |
33 | ||
34 | /* | |
35 | * High Level Configuration Options | |
36 | */ | |
37 | #define CONFIG_E300 1 /* E300 Family */ | |
bf0b542d | 38 | #define CONFIG_MPC83XX 1 /* MPC83XX family */ |
b24f119d | 39 | #define CONFIG_MPC834X 1 /* MPC834X family */ |
991425fe MB |
40 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
41 | #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ | |
42 | ||
977b50f8 | 43 | #undef CONFIG_PCI |
8fe9bf61 | 44 | #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ |
991425fe MB |
45 | |
46 | #define PCI_66M | |
47 | #ifdef PCI_66M | |
48 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
49 | #else | |
50 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
51 | #endif | |
52 | ||
53 | #ifndef CONFIG_SYS_CLK_FREQ | |
54 | #ifdef PCI_66M | |
55 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
8fe9bf61 | 56 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
991425fe MB |
57 | #else |
58 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
8fe9bf61 | 59 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
991425fe MB |
60 | #endif |
61 | #endif | |
62 | ||
bf0b542d KP |
63 | #define CFG_SCCR_INIT (SCCR_DEFAULT & (~SCCR_CLK_MASK)) |
64 | #define CFG_SCCR_TSEC1CM SCCR_TSEC1CM_1 /* TSEC1 clock setting */ | |
65 | #define CFG_SCCR_TSEC2CM SCCR_TSEC2CM_1 /* TSEC2 clock setting */ | |
66 | #define CFG_SCCR_ENCCM SCCR_ENCCM_3 /* ENC clock setting */ | |
67 | #define CFG_SCCR_USBCM SCCR_USBCM_3 /* USB clock setting */ | |
68 | #define CFG_SCCR_VAL ( CFG_SCCR_INIT \ | |
69 | | CFG_SCCR_TSEC1CM \ | |
70 | | CFG_SCCR_TSEC2CM \ | |
71 | | CFG_SCCR_ENCCM \ | |
72 | | CFG_SCCR_USBCM ) | |
73 | ||
991425fe MB |
74 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
75 | ||
d239d74b | 76 | #define CFG_IMMR 0xE0000000 |
991425fe MB |
77 | |
78 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
79 | #define CFG_MEMTEST_START 0x00000000 /* memtest region */ | |
80 | #define CFG_MEMTEST_END 0x00100000 | |
81 | ||
82 | /* | |
83 | * DDR Setup | |
84 | */ | |
8d172c0f | 85 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
d326f4a2 | 86 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
991425fe MB |
87 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
88 | ||
dc9e499c RJ |
89 | /* |
90 | * 32-bit data path mode. | |
cf48eb9a | 91 | * |
dc9e499c RJ |
92 | * Please note that using this mode for devices with the real density of 64-bit |
93 | * effectively reduces the amount of available memory due to the effect of | |
94 | * wrapping around while translating address to row/columns, for example in the | |
95 | * 256MB module the upper 128MB get aliased with contents of the lower | |
96 | * 128MB); normally this define should be used for devices with real 32-bit | |
cf48eb9a | 97 | * data path. |
dc9e499c RJ |
98 | */ |
99 | #undef CONFIG_DDR_32BIT | |
100 | ||
991425fe MB |
101 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ |
102 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
103 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
8d172c0f XX |
104 | #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
105 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
991425fe MB |
106 | #undef CONFIG_DDR_2T_TIMING |
107 | ||
8d172c0f XX |
108 | /* |
109 | * DDRCDR - DDR Control Driver Register | |
110 | */ | |
111 | #define CFG_DDRCDR_VALUE 0x80080001 | |
112 | ||
991425fe | 113 | #if defined(CONFIG_SPD_EEPROM) |
dc9e499c RJ |
114 | /* |
115 | * Determine DDR configuration from I2C interface. | |
116 | */ | |
117 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
991425fe | 118 | #else |
dc9e499c RJ |
119 | /* |
120 | * Manually set up DDR parameters | |
121 | */ | |
122 | #define CFG_DDR_SIZE 256 /* MB */ | |
8d172c0f XX |
123 | #if defined(CONFIG_DDR_II) |
124 | #define CFG_DDRCDR 0x80080001 | |
125 | #define CFG_DDR_CS2_BNDS 0x0000000f | |
126 | #define CFG_DDR_CS2_CONFIG 0x80330102 | |
127 | #define CFG_DDR_TIMING_0 0x00220802 | |
128 | #define CFG_DDR_TIMING_1 0x38357322 | |
129 | #define CFG_DDR_TIMING_2 0x2f9048c8 | |
130 | #define CFG_DDR_TIMING_3 0x00000000 | |
131 | #define CFG_DDR_CLK_CNTL 0x02000000 | |
132 | #define CFG_DDR_MODE 0x47d00432 | |
133 | #define CFG_DDR_MODE2 0x8000c000 | |
134 | #define CFG_DDR_INTERVAL 0x03cf0080 | |
135 | #define CFG_DDR_SDRAM_CFG 0x43000000 | |
136 | #define CFG_DDR_SDRAM_CFG2 0x00401000 | |
137 | #else | |
dc9e499c RJ |
138 | #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) |
139 | #define CFG_DDR_TIMING_1 0x36332321 | |
140 | #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
141 | #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
142 | #define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ | |
143 | ||
144 | #if defined(CONFIG_DDR_32BIT) | |
145 | /* set burst length to 8 for 32-bit data path */ | |
146 | #define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ | |
147 | #else | |
148 | /* the default burst length is 4 - for 64-bit data path */ | |
149 | #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ | |
150 | #endif | |
991425fe | 151 | #endif |
8d172c0f | 152 | #endif |
991425fe MB |
153 | |
154 | /* | |
155 | * SDRAM on the Local Bus | |
156 | */ | |
157 | #define CFG_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ | |
158 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
159 | ||
160 | /* | |
161 | * FLASH on the Local Bus | |
162 | */ | |
163 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
164 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
165 | #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ | |
8d172c0f | 166 | #define CFG_FLASH_SIZE 32 /* max flash size in MB */ |
991425fe MB |
167 | /* #define CFG_FLASH_USE_BUFFER_WRITE */ |
168 | ||
169 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ | |
8d172c0f | 170 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ |
991425fe | 171 | BR_V) /* valid */ |
8d172c0f XX |
172 | #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ |
173 | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ | |
174 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) | |
991425fe | 175 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ |
8d172c0f | 176 | #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ |
991425fe MB |
177 | |
178 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
8d172c0f | 179 | #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ |
991425fe MB |
180 | |
181 | #undef CFG_FLASH_CHECKSUM | |
182 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
183 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
184 | ||
185 | #define CFG_MID_FLASH_JUMP 0x7F000000 | |
186 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
187 | ||
188 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
189 | #define CFG_RAMBOOT | |
190 | #else | |
191 | #undef CFG_RAMBOOT | |
192 | #endif | |
193 | ||
194 | /* | |
195 | * BCSR register on local bus 32KB, 8-bit wide for MDS config reg | |
196 | */ | |
8fe9bf61 | 197 | #define CFG_BCSR 0xE2400000 |
991425fe MB |
198 | #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ |
199 | #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ | |
200 | #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ | |
201 | #define CFG_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ | |
202 | ||
203 | #define CONFIG_L1_INIT_RAM | |
204 | #define CFG_INIT_RAM_LOCK 1 | |
8fe9bf61 | 205 | #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
991425fe MB |
206 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ |
207 | ||
208 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
209 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
210 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
211 | ||
212 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
213 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
214 | ||
215 | /* | |
216 | * Local Bus LCRR and LBCR regs | |
217 | * LCRR: DLL bypass, Clock divider is 4 | |
218 | * External Local Bus rate is | |
219 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
220 | */ | |
221 | #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) | |
222 | #define CFG_LBC_LBCR 0x00000000 | |
223 | ||
8d172c0f XX |
224 | /* |
225 | * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. | |
226 | * if board has SRDAM on local bus, you can define CFG_LB_SDRAM | |
227 | */ | |
228 | #undef CFG_LB_SDRAM | |
991425fe MB |
229 | |
230 | #ifdef CFG_LB_SDRAM | |
231 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ | |
232 | /* | |
233 | * Base Register 2 and Option Register 2 configure SDRAM. | |
234 | * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. | |
235 | * | |
236 | * For BR2, need: | |
237 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
238 | * port-size = 32-bits = BR2[19:20] = 11 | |
239 | * no parity checking = BR2[21:22] = 00 | |
240 | * SDRAM for MSEL = BR2[24:26] = 011 | |
241 | * Valid = BR[31] = 1 | |
242 | * | |
243 | * 0 4 8 12 16 20 24 28 | |
244 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
245 | * | |
246 | * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into | |
247 | * FIXME: the top 17 bits of BR2. | |
248 | */ | |
249 | ||
250 | #define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ | |
251 | #define CFG_LBLAWBAR2_PRELIM 0xF0000000 | |
252 | #define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ | |
253 | ||
254 | /* | |
255 | * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. | |
256 | * | |
257 | * For OR2, need: | |
258 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
259 | * XAM, OR2[17:18] = 11 | |
260 | * 9 columns OR2[19-21] = 010 | |
261 | * 13 rows OR2[23-25] = 100 | |
262 | * EAD set for extra time OR[31] = 1 | |
263 | * | |
264 | * 0 4 8 12 16 20 24 28 | |
265 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
266 | */ | |
267 | ||
268 | #define CFG_OR2_PRELIM 0xFC006901 | |
269 | ||
270 | #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ | |
271 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ | |
272 | ||
273 | /* | |
274 | * LSDMR masks | |
275 | */ | |
276 | #define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) | |
277 | #define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) | |
278 | #define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) | |
279 | #define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) | |
280 | #define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) | |
281 | #define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) | |
282 | #define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) | |
283 | #define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) | |
284 | #define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) | |
285 | #define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) | |
286 | #define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) | |
287 | #define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) | |
288 | #define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) | |
289 | #define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) | |
290 | #define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) | |
291 | #define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) | |
292 | #define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) | |
293 | #define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) | |
294 | ||
295 | #define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) | |
296 | #define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) | |
297 | #define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) | |
298 | #define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) | |
299 | #define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) | |
300 | #define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) | |
301 | #define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) | |
302 | #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) | |
303 | ||
304 | #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ | |
305 | | CFG_LBC_LSDMR_BSMA1516 \ | |
306 | | CFG_LBC_LSDMR_RFCR8 \ | |
307 | | CFG_LBC_LSDMR_PRETOACT6 \ | |
308 | | CFG_LBC_LSDMR_ACTTORW3 \ | |
309 | | CFG_LBC_LSDMR_BL8 \ | |
310 | | CFG_LBC_LSDMR_WRC3 \ | |
311 | | CFG_LBC_LSDMR_CL3 \ | |
312 | ) | |
313 | ||
314 | /* | |
315 | * SDRAM Controller configuration sequence. | |
316 | */ | |
317 | #define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ | |
318 | | CFG_LBC_LSDMR_OP_PCHALL) | |
319 | #define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ | |
320 | | CFG_LBC_LSDMR_OP_ARFRSH) | |
321 | #define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ | |
322 | | CFG_LBC_LSDMR_OP_ARFRSH) | |
323 | #define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ | |
324 | | CFG_LBC_LSDMR_OP_MRW) | |
325 | #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ | |
326 | | CFG_LBC_LSDMR_OP_NORMAL) | |
327 | #endif | |
328 | ||
329 | /* | |
330 | * Serial Port | |
331 | */ | |
332 | #define CONFIG_CONS_INDEX 1 | |
333 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
334 | #define CFG_NS16550 | |
335 | #define CFG_NS16550_SERIAL | |
336 | #define CFG_NS16550_REG_SIZE 1 | |
337 | #define CFG_NS16550_CLK get_bus_freq(0) | |
338 | ||
339 | #define CFG_BAUDRATE_TABLE \ | |
340 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
341 | ||
d239d74b TT |
342 | #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) |
343 | #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) | |
991425fe MB |
344 | |
345 | /* Use the HUSH parser */ | |
346 | #define CFG_HUSH_PARSER | |
347 | #ifdef CFG_HUSH_PARSER | |
348 | #define CFG_PROMPT_HUSH_PS2 "> " | |
349 | #endif | |
350 | ||
bf0b542d KP |
351 | /* pass open firmware flat tree */ |
352 | #define CONFIG_OF_FLAT_TREE 1 | |
353 | #define CONFIG_OF_BOARD_SETUP 1 | |
354 | ||
355 | /* maximum size of the flat tree (8K) */ | |
356 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
357 | ||
358 | #define OF_CPU "PowerPC,8349@0" | |
359 | #define OF_SOC "soc8349@e0000000" | |
360 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
361 | #define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" | |
362 | ||
991425fe MB |
363 | /* I2C */ |
364 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
365 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
be5e6181 | 366 | #define CONFIG_FSL_I2C |
b24f119d BW |
367 | #define CONFIG_I2C_MULTI_BUS |
368 | #define CONFIG_I2C_CMD_TREE | |
991425fe MB |
369 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
370 | #define CFG_I2C_SLAVE 0x7F | |
b24f119d | 371 | #define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ |
991425fe MB |
372 | #define CFG_I2C_OFFSET 0x3000 |
373 | #define CFG_I2C2_OFFSET 0x3100 | |
374 | ||
375 | /* TSEC */ | |
376 | #define CFG_TSEC1_OFFSET 0x24000 | |
d239d74b | 377 | #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) |
991425fe | 378 | #define CFG_TSEC2_OFFSET 0x25000 |
d239d74b | 379 | #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) |
991425fe | 380 | |
8fe9bf61 KG |
381 | /* USB */ |
382 | #define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ | |
991425fe MB |
383 | |
384 | /* | |
385 | * General PCI | |
386 | * Addresses are mapped 1-1. | |
387 | */ | |
388 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
389 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
8fe9bf61 KG |
390 | #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
391 | #define CFG_PCI1_MMIO_BASE 0x90000000 | |
392 | #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE | |
393 | #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
991425fe | 394 | #define CFG_PCI1_IO_BASE 0x00000000 |
8fe9bf61 KG |
395 | #define CFG_PCI1_IO_PHYS 0xE2000000 |
396 | #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
991425fe MB |
397 | |
398 | #define CFG_PCI2_MEM_BASE 0xA0000000 | |
399 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE | |
8fe9bf61 KG |
400 | #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ |
401 | #define CFG_PCI2_MMIO_BASE 0xB0000000 | |
402 | #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE | |
403 | #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
991425fe | 404 | #define CFG_PCI2_IO_BASE 0x00000000 |
8fe9bf61 KG |
405 | #define CFG_PCI2_IO_PHYS 0xE2100000 |
406 | #define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
991425fe MB |
407 | |
408 | #if defined(CONFIG_PCI) | |
409 | ||
8fe9bf61 | 410 | #define PCI_ONE_PCI1 |
991425fe MB |
411 | #if defined(PCI_64BIT) |
412 | #undef PCI_ALL_PCI1 | |
413 | #undef PCI_TWO_PCI1 | |
414 | #undef PCI_ONE_PCI1 | |
415 | #endif | |
416 | ||
417 | #define CONFIG_NET_MULTI | |
418 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
419 | ||
420 | #undef CONFIG_EEPRO100 | |
421 | #undef CONFIG_TULIP | |
422 | ||
423 | #if !defined(CONFIG_PCI_PNP) | |
424 | #define PCI_ENET0_IOADDR 0xFIXME | |
425 | #define PCI_ENET0_MEMADDR 0xFIXME | |
426 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
427 | #endif | |
428 | ||
429 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
430 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
431 | ||
432 | #endif /* CONFIG_PCI */ | |
433 | ||
434 | /* | |
435 | * TSEC configuration | |
436 | */ | |
437 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
438 | ||
439 | #if defined(CONFIG_TSEC_ENET) | |
440 | #ifndef CONFIG_NET_MULTI | |
441 | #define CONFIG_NET_MULTI 1 | |
442 | #endif | |
443 | ||
444 | #define CONFIG_GMII 1 /* MII PHY management */ | |
445 | #define CONFIG_MPC83XX_TSEC1 1 | |
446 | #define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" | |
447 | #define CONFIG_MPC83XX_TSEC2 1 | |
448 | #define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" | |
449 | #define TSEC1_PHY_ADDR 0 | |
450 | #define TSEC2_PHY_ADDR 1 | |
451 | #define TSEC1_PHYIDX 0 | |
452 | #define TSEC2_PHYIDX 0 | |
453 | ||
454 | /* Options are: TSEC[0-1] */ | |
455 | #define CONFIG_ETHPRIME "TSEC0" | |
456 | ||
457 | #endif /* CONFIG_TSEC_ENET */ | |
458 | ||
459 | /* | |
460 | * Configure on-board RTC | |
461 | */ | |
462 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
463 | #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
464 | ||
465 | /* | |
466 | * Environment | |
467 | */ | |
468 | #ifndef CFG_RAMBOOT | |
469 | #define CFG_ENV_IS_IN_FLASH 1 | |
470 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
471 | #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
472 | #define CFG_ENV_SIZE 0x2000 | |
473 | ||
474 | /* Address and size of Redundant Environment Sector */ | |
475 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) | |
476 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
477 | ||
478 | #else | |
479 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ | |
480 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
481 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
482 | #define CFG_ENV_SIZE 0x2000 | |
483 | #endif | |
484 | ||
485 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
486 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
487 | ||
488 | #if defined(CFG_RAMBOOT) | |
489 | #if defined(CONFIG_PCI) | |
490 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | |
491 | | CFG_CMD_PING \ | |
492 | | CFG_CMD_PCI \ | |
493 | | CFG_CMD_I2C \ | |
494 | | CFG_CMD_DATE) \ | |
495 | & \ | |
496 | ~(CFG_CMD_ENV \ | |
497 | | CFG_CMD_LOADS)) | |
498 | #else | |
499 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ | |
500 | | CFG_CMD_PING \ | |
501 | | CFG_CMD_I2C \ | |
502 | | CFG_CMD_DATE) \ | |
503 | & \ | |
504 | ~(CFG_CMD_ENV \ | |
505 | | CFG_CMD_LOADS)) | |
506 | #endif | |
507 | #else | |
508 | #if defined(CONFIG_PCI) | |
509 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
510 | | CFG_CMD_PCI \ | |
511 | | CFG_CMD_PING \ | |
512 | | CFG_CMD_I2C \ | |
513 | | CFG_CMD_DATE \ | |
514 | ) | |
515 | #else | |
516 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
517 | | CFG_CMD_PING \ | |
518 | | CFG_CMD_I2C \ | |
519 | | CFG_CMD_MII \ | |
520 | | CFG_CMD_DATE \ | |
521 | ) | |
522 | #endif | |
523 | #endif | |
524 | ||
525 | #include <cmd_confdefs.h> | |
526 | ||
527 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
528 | ||
529 | /* | |
530 | * Miscellaneous configurable options | |
531 | */ | |
532 | #define CFG_LONGHELP /* undef to save memory */ | |
533 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
534 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
535 | ||
536 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
537 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
538 | #else | |
539 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
540 | #endif | |
541 | ||
542 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
543 | #define CFG_MAXARGS 16 /* max number of command args */ | |
544 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
545 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
546 | ||
547 | /* | |
548 | * For booting Linux, the board info and command line data | |
549 | * have to be in the first 8 MB of memory, since this is | |
550 | * the maximum mapped by the Linux kernel during initialization. | |
551 | */ | |
552 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
553 | ||
554 | /* Cache Configuration */ | |
555 | #define CFG_DCACHE_SIZE 32768 | |
556 | #define CFG_CACHELINE_SIZE 32 | |
557 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
558 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ | |
559 | #endif | |
560 | ||
561 | #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ | |
562 | ||
563 | #if 1 /*528/264*/ | |
564 | #define CFG_HRCW_LOW (\ | |
565 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
566 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 567 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
568 | HRCWL_VCO_1X2 |\ |
569 | HRCWL_CORE_TO_CSB_2X1) | |
570 | #elif 0 /*396/132*/ | |
571 | #define CFG_HRCW_LOW (\ | |
572 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
573 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 574 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
575 | HRCWL_VCO_1X4 |\ |
576 | HRCWL_CORE_TO_CSB_3X1) | |
577 | #elif 0 /*264/132*/ | |
578 | #define CFG_HRCW_LOW (\ | |
579 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
580 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 581 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
582 | HRCWL_VCO_1X4 |\ |
583 | HRCWL_CORE_TO_CSB_2X1) | |
584 | #elif 0 /*132/132*/ | |
585 | #define CFG_HRCW_LOW (\ | |
586 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
587 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 588 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
589 | HRCWL_VCO_1X4 |\ |
590 | HRCWL_CORE_TO_CSB_1X1) | |
591 | #elif 0 /*264/264 */ | |
592 | #define CFG_HRCW_LOW (\ | |
593 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
594 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 595 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
596 | HRCWL_VCO_1X4 |\ |
597 | HRCWL_CORE_TO_CSB_1X1) | |
598 | #endif | |
599 | ||
600 | #if defined(PCI_64BIT) | |
601 | #define CFG_HRCW_HIGH (\ | |
602 | HRCWH_PCI_HOST |\ | |
603 | HRCWH_64_BIT_PCI |\ | |
604 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
605 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
606 | HRCWH_CORE_ENABLE |\ | |
607 | HRCWH_FROM_0X00000100 |\ | |
608 | HRCWH_BOOTSEQ_DISABLE |\ | |
609 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
610 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
611 | HRCWH_TSEC1M_IN_GMII |\ | |
612 | HRCWH_TSEC2M_IN_GMII ) | |
613 | #else | |
614 | #define CFG_HRCW_HIGH (\ | |
615 | HRCWH_PCI_HOST |\ | |
616 | HRCWH_32_BIT_PCI |\ | |
617 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
618 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
619 | HRCWH_CORE_ENABLE |\ | |
620 | HRCWH_FROM_0X00000100 |\ | |
621 | HRCWH_BOOTSEQ_DISABLE |\ | |
622 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
623 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
624 | HRCWH_TSEC1M_IN_GMII |\ | |
625 | HRCWH_TSEC2M_IN_GMII ) | |
626 | #endif | |
627 | ||
628 | /* System IO Config */ | |
629 | #define CFG_SICRH SICRH_TSOBI1 | |
630 | #define CFG_SICRL SICRL_LDP_A | |
631 | ||
632 | #define CFG_HID0_INIT 0x000000000 | |
8fe9bf61 | 633 | #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK |
991425fe MB |
634 | |
635 | /* #define CFG_HID0_FINAL (\ | |
636 | HID0_ENABLE_INSTRUCTION_CACHE |\ | |
637 | HID0_ENABLE_M_BIT |\ | |
638 | HID0_ENABLE_ADDRESS_BROADCAST ) */ | |
639 | ||
640 | ||
641 | #define CFG_HID2 HID2_HBE | |
642 | ||
643 | /* DDR @ 0x00000000 */ | |
644 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
645 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
646 | ||
647 | /* PCI @ 0x80000000 */ | |
648 | #ifdef CONFIG_PCI | |
649 | #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
650 | #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
651 | #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
652 | #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
653 | #else | |
654 | #define CFG_IBAT1L (0) | |
655 | #define CFG_IBAT1U (0) | |
656 | #define CFG_IBAT2L (0) | |
657 | #define CFG_IBAT2U (0) | |
658 | #endif | |
659 | ||
8fe9bf61 KG |
660 | #ifdef CONFIG_MPC83XX_PCI2 |
661 | #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
662 | #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
663 | #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
664 | #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
665 | #else | |
666 | #define CFG_IBAT3L (0) | |
667 | #define CFG_IBAT3U (0) | |
668 | #define CFG_IBAT4L (0) | |
669 | #define CFG_IBAT4U (0) | |
670 | #endif | |
991425fe | 671 | |
8fe9bf61 | 672 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
d239d74b TT |
673 | #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
674 | #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
991425fe | 675 | |
8fe9bf61 KG |
676 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
677 | #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) | |
678 | #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
991425fe | 679 | |
8fe9bf61 KG |
680 | #define CFG_IBAT7L (0) |
681 | #define CFG_IBAT7U (0) | |
991425fe MB |
682 | |
683 | #define CFG_DBAT0L CFG_IBAT0L | |
684 | #define CFG_DBAT0U CFG_IBAT0U | |
685 | #define CFG_DBAT1L CFG_IBAT1L | |
686 | #define CFG_DBAT1U CFG_IBAT1U | |
687 | #define CFG_DBAT2L CFG_IBAT2L | |
688 | #define CFG_DBAT2U CFG_IBAT2U | |
689 | #define CFG_DBAT3L CFG_IBAT3L | |
690 | #define CFG_DBAT3U CFG_IBAT3U | |
691 | #define CFG_DBAT4L CFG_IBAT4L | |
692 | #define CFG_DBAT4U CFG_IBAT4U | |
693 | #define CFG_DBAT5L CFG_IBAT5L | |
694 | #define CFG_DBAT5U CFG_IBAT5U | |
695 | #define CFG_DBAT6L CFG_IBAT6L | |
696 | #define CFG_DBAT6U CFG_IBAT6U | |
697 | #define CFG_DBAT7L CFG_IBAT7L | |
698 | #define CFG_DBAT7U CFG_IBAT7U | |
699 | ||
700 | /* | |
701 | * Internal Definitions | |
702 | * | |
703 | * Boot Flags | |
704 | */ | |
705 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
706 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
707 | ||
708 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
709 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
710 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
711 | #endif | |
712 | ||
713 | /* | |
714 | * Environment Configuration | |
715 | */ | |
716 | #define CONFIG_ENV_OVERWRITE | |
717 | ||
718 | #if defined(CONFIG_TSEC_ENET) | |
719 | #define CONFIG_ETHADDR 00:04:9f:ef:23:33 | |
720 | #define CONFIG_HAS_ETH1 | |
721 | #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 | |
722 | #endif | |
723 | ||
bf0b542d | 724 | #define CONFIG_IPADDR 192.168.1.253 |
991425fe MB |
725 | |
726 | #define CONFIG_HOSTNAME mpc8349emds | |
bf0b542d KP |
727 | #define CONFIG_ROOTPATH /nfsroot/rootfs |
728 | #define CONFIG_BOOTFILE uImage | |
991425fe MB |
729 | |
730 | #define CONFIG_SERVERIP 192.168.1.1 | |
731 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
732 | #define CONFIG_NETMASK 255.255.255.0 | |
733 | ||
734 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
735 | ||
736 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
737 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
738 | ||
739 | #define CONFIG_BAUDRATE 115200 | |
740 | ||
741 | #define CONFIG_PREBOOT "echo;" \ | |
742 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
743 | "echo" | |
744 | ||
745 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
746 | "netdev=eth0\0" \ | |
747 | "hostname=mpc8349emds\0" \ | |
748 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
749 | "nfsroot=${serverip}:${rootpath}\0" \ | |
750 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
751 | "addip=setenv bootargs ${bootargs} " \ | |
752 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
753 | ":${hostname}:${netdev}:off panic=1\0" \ | |
754 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
755 | "flash_nfs=run nfsargs addip addtty;" \ | |
756 | "bootm ${kernel_addr}\0" \ | |
757 | "flash_self=run ramargs addip addtty;" \ | |
758 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
759 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
760 | "bootm\0" \ | |
991425fe MB |
761 | "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ |
762 | "update=protect off fe000000 fe03ffff; " \ | |
763 | "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ | |
764 | "upd=run load;run update\0" \ | |
bf0b542d KP |
765 | "fdtaddr=400000\0" \ |
766 | "fdtfile=mpc8349emds.dtb\0" \ | |
991425fe MB |
767 | "" |
768 | ||
bf0b542d KP |
769 | #define CONFIG_NFSBOOTCOMMAND \ |
770 | "setenv bootargs root=/dev/nfs rw " \ | |
771 | "nfsroot=$serverip:$rootpath " \ | |
772 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
773 | "console=$consoledev,$baudrate $othbootargs;" \ | |
774 | "tftp $loadaddr $bootfile;" \ | |
775 | "tftp $fdtaddr $fdtfile;" \ | |
776 | "bootm $loadaddr - $fdtaddr" | |
777 | ||
778 | #define CONFIG_RAMBOOTCOMMAND \ | |
779 | "setenv bootargs root=/dev/ram rw " \ | |
780 | "console=$consoledev,$baudrate $othbootargs;" \ | |
781 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
782 | "tftp $loadaddr $bootfile;" \ | |
783 | "tftp $fdtaddr $fdtfile;" \ | |
784 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
785 | ||
991425fe MB |
786 | #define CONFIG_BOOTCOMMAND "run flash_self" |
787 | ||
788 | #endif /* __CONFIG_H */ |