]>
Commit | Line | Data |
---|---|---|
2ad6b513 TT |
1 | /* |
2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
7a78f148 | 24 | MPC8349E-mITX and MPC8349E-mITX-GP board configuration file |
2ad6b513 TT |
25 | |
26 | Memory map: | |
27 | ||
28 | 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) | |
29 | 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) | |
30 | 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) | |
31 | 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) | |
32 | 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) | |
33 | 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) | |
7a78f148 | 34 | 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) |
2ad6b513 | 35 | 0xF001_0000-0xF001_FFFF Local bus expansion slot |
7a78f148 TT |
36 | 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) |
37 | 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory | |
38 | 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) | |
2ad6b513 TT |
39 | |
40 | I2C address list: | |
dd520bf3 WD |
41 | Align. Board |
42 | Bus Addr Part No. Description Length Location | |
2ad6b513 | 43 | ---------------------------------------------------------------- |
dd520bf3 | 44 | I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
2ad6b513 | 45 | |
dd520bf3 WD |
46 | I2C1 0x20 PCF8574 I2C Expander 0 U8 |
47 | I2C1 0x21 PCF8574 I2C Expander 0 U10 | |
48 | I2C1 0x38 PCF8574A I2C Expander 0 U8 | |
49 | I2C1 0x39 PCF8574A I2C Expander 0 U10 | |
50 | I2C1 0x51 (DDR) DDR EEPROM 1 U1 | |
51 | I2C1 0x68 DS1339 RTC 1 U68 | |
2ad6b513 TT |
52 | |
53 | Note that a given board has *either* a pair of 8574s or a pair of 8574As. | |
54 | */ | |
55 | ||
56 | #ifndef __CONFIG_H | |
57 | #define __CONFIG_H | |
58 | ||
7a78f148 TT |
59 | #if (TEXT_BASE == 0xFE000000) |
60 | #define CFG_LOWBOOT | |
61 | #endif | |
2ad6b513 TT |
62 | |
63 | /* | |
64 | * High Level Configuration Options | |
65 | */ | |
66 | #define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ | |
67 | #define CONFIG_MPC8349 /* MPC8349 specific */ | |
68 | ||
7a78f148 TT |
69 | #define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ |
70 | ||
89c7784e TT |
71 | #define CONFIG_MISC_INIT_F |
72 | #define CONFIG_MISC_INIT_R | |
7a78f148 | 73 | |
89c7784e TT |
74 | /* |
75 | * On-board devices | |
76 | */ | |
2ad6b513 | 77 | |
7a78f148 | 78 | #ifdef CONFIG_MPC8349ITX |
2ad6b513 | 79 | #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ |
89c7784e | 80 | #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ |
7a78f148 | 81 | #endif |
2ad6b513 | 82 | |
7a78f148 TT |
83 | #define CONFIG_PCI |
84 | #define CONFIG_RTC_DS1337 | |
2ad6b513 | 85 | #define CONFIG_HARD_I2C |
7a78f148 | 86 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ |
2ad6b513 | 87 | |
7a78f148 TT |
88 | /* |
89 | * Device configurations | |
90 | */ | |
91 | ||
92 | /* I2C */ | |
2ad6b513 TT |
93 | #ifdef CONFIG_HARD_I2C |
94 | ||
be5e6181 | 95 | #define CONFIG_FSL_I2C |
2ad6b513 TT |
96 | #define CONFIG_I2C_MULTI_BUS |
97 | #define CONFIG_I2C_CMD_TREE | |
dd520bf3 WD |
98 | #define CFG_I2C_OFFSET 0x3000 |
99 | #define CFG_I2C2_OFFSET 0x3100 | |
be5e6181 | 100 | #define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ |
2ad6b513 | 101 | |
be5e6181 TT |
102 | #define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ |
103 | #define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ | |
104 | #define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ | |
105 | #define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ | |
dd520bf3 | 106 | #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ |
be5e6181 TT |
107 | #define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ |
108 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ | |
2ad6b513 TT |
109 | |
110 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
111 | #define CFG_I2C_SLAVE 0x7F | |
112 | ||
113 | /* Don't probe these addresses: */ | |
dd520bf3 | 114 | #define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ |
2ad6b513 TT |
115 | {1, CFG_I2C_8574_ADDR2}, \ |
116 | {1, CFG_I2C_8574A_ADDR1}, \ | |
117 | {1, CFG_I2C_8574A_ADDR2}} | |
118 | /* Bit definitions for the 8574[A] I2C expander */ | |
119 | #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ | |
120 | #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ | |
121 | #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ | |
122 | #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ | |
123 | #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ | |
124 | ||
125 | #undef CONFIG_SOFT_I2C | |
126 | ||
127 | #endif | |
128 | ||
7a78f148 TT |
129 | /* Compact Flash */ |
130 | #ifdef CONFIG_COMPACT_FLASH | |
2ad6b513 | 131 | |
7a78f148 TT |
132 | #define CFG_IDE_MAXBUS 1 |
133 | #define CFG_IDE_MAXDEVICE 1 | |
2ad6b513 | 134 | |
7a78f148 TT |
135 | #define CFG_ATA_IDE0_OFFSET 0x0000 |
136 | #define CFG_ATA_BASE_ADDR CFG_CF_BASE | |
137 | #define CFG_ATA_DATA_OFFSET 0x0000 | |
138 | #define CFG_ATA_REG_OFFSET 0 | |
139 | #define CFG_ATA_ALT_OFFSET 0x0200 | |
140 | #define CFG_ATA_STRIDE 2 | |
2ad6b513 | 141 | |
7a78f148 | 142 | #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ |
2ad6b513 | 143 | |
7a78f148 | 144 | #define CONFIG_DOS_PARTITION |
2ad6b513 | 145 | |
7a78f148 | 146 | #endif |
2ad6b513 TT |
147 | |
148 | /* | |
7a78f148 | 149 | * DDR Setup |
2ad6b513 | 150 | */ |
7a78f148 | 151 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ |
53677ef1 WD |
152 | #define CFG_SDRAM_BASE CFG_DDR_BASE |
153 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
2ad6b513 | 154 | #define CFG_83XX_DDR_USES_CS0 |
7a78f148 TT |
155 | #define CFG_MEMTEST_START 0x1000 /* memtest region */ |
156 | #define CFG_MEMTEST_END 0x2000 | |
2ad6b513 | 157 | |
f64702b7 | 158 | #define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ |
507e2d79 | 159 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) |
f64702b7 | 160 | |
7a78f148 TT |
161 | #ifdef CONFIG_HARD_I2C |
162 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ | |
163 | #endif | |
164 | ||
165 | #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ | |
2ad6b513 TT |
166 | #define CFG_DDR_SIZE 256 /* Mb */ |
167 | #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) | |
168 | ||
169 | #define CFG_DDR_TIMING_1 0x26242321 | |
170 | #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ | |
171 | #endif | |
172 | ||
7a78f148 TT |
173 | /* |
174 | *Flash on the Local Bus | |
175 | */ | |
176 | ||
2ad6b513 | 177 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 178 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
2ad6b513 | 179 | #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ |
be5e6181 | 180 | #define CFG_FLASH_EMPTY_INFO |
7a78f148 TT |
181 | #define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ |
182 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
183 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
184 | #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
185 | ||
186 | /* The ITX has two flash chips, but the ITX-GP has only one. To support both | |
187 | boards, we say we have two, but don't display a message if we find only one. */ | |
188 | #define CFG_FLASH_QUIET_TEST | |
189 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
53677ef1 | 190 | #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} |
7a78f148 TT |
191 | #define CFG_FLASH_SIZE 16 /* FLASH size in MB */ |
192 | #define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ | |
193 | ||
89c7784e TT |
194 | /* Vitesse 7385 */ |
195 | ||
196 | #ifdef CONFIG_VSC7385_ENET | |
197 | ||
198 | #define CONFIG_TSEC2 | |
199 | ||
200 | /* The flash address and size of the VSC7385 firmware image */ | |
201 | #define CONFIG_VSC7385_IMAGE 0xFEFFE000 | |
202 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
203 | ||
204 | #endif | |
205 | ||
7a78f148 TT |
206 | /* |
207 | * BRx, ORx, LBLAWBARx, and LBLAWARx | |
208 | */ | |
209 | ||
210 | /* Flash */ | |
2ad6b513 TT |
211 | |
212 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) | |
213 | #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ | |
f9023afb | 214 | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ |
2ad6b513 | 215 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
7a78f148 TT |
216 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE |
217 | #define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) | |
2ad6b513 | 218 | |
7a78f148 | 219 | /* Vitesse 7385 */ |
2ad6b513 | 220 | |
7a78f148 | 221 | #define CFG_VSC7385_BASE 0xF8000000 |
2ad6b513 | 222 | |
89c7784e TT |
223 | #ifdef CONFIG_VSC7385_ENET |
224 | ||
7a78f148 TT |
225 | #define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) |
226 | #define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ | |
227 | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ | |
228 | OR_GPCM_EHTR | OR_GPCM_EAD) | |
2ad6b513 | 229 | |
7a78f148 TT |
230 | #define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE |
231 | #define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) | |
2ad6b513 | 232 | |
7a78f148 | 233 | #endif |
2ad6b513 | 234 | |
7a78f148 TT |
235 | /* LED */ |
236 | ||
237 | #define CFG_LED_BASE 0xF9000000 | |
2ad6b513 | 238 | #define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) |
f9023afb | 239 | #define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ |
7a78f148 TT |
240 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ |
241 | OR_GPCM_EHTR | OR_GPCM_EAD) | |
242 | ||
243 | /* Compact Flash */ | |
2ad6b513 TT |
244 | |
245 | #ifdef CONFIG_COMPACT_FLASH | |
246 | ||
dd520bf3 | 247 | #define CFG_CF_BASE 0xF0000000 |
2ad6b513 | 248 | |
dd520bf3 WD |
249 | #define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) |
250 | #define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) | |
2ad6b513 | 251 | |
7a78f148 TT |
252 | #define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE |
253 | #define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) | |
2ad6b513 TT |
254 | |
255 | #endif | |
256 | ||
7a78f148 TT |
257 | /* |
258 | * U-Boot memory configuration | |
259 | */ | |
dd520bf3 | 260 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
2ad6b513 | 261 | |
2ad6b513 TT |
262 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
263 | #define CFG_RAMBOOT | |
264 | #else | |
dd520bf3 | 265 | #undef CFG_RAMBOOT |
2ad6b513 TT |
266 | #endif |
267 | ||
268 | #define CONFIG_L1_INIT_RAM | |
269 | #define CFG_INIT_RAM_LOCK | |
7a78f148 TT |
270 | #define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ |
271 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
2ad6b513 | 272 | |
7a78f148 | 273 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
2ad6b513 TT |
274 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
275 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
276 | ||
b2893e1f | 277 | /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ |
dd520bf3 WD |
278 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
279 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
2ad6b513 TT |
280 | |
281 | /* | |
282 | * Local Bus LCRR and LBCR regs | |
283 | * LCRR: DLL bypass, Clock divider is 4 | |
284 | * External Local Bus rate is | |
285 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
286 | */ | |
287 | #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) | |
288 | #define CFG_LBC_LBCR 0x00000000 | |
289 | ||
2ad6b513 TT |
290 | #define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
291 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ | |
292 | ||
2ad6b513 TT |
293 | /* |
294 | * Serial Port | |
295 | */ | |
296 | #define CONFIG_CONS_INDEX 1 | |
297 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
298 | #define CFG_NS16550 | |
299 | #define CFG_NS16550_SERIAL | |
300 | #define CFG_NS16550_REG_SIZE 1 | |
301 | #define CFG_NS16550_CLK get_bus_freq(0) | |
302 | ||
303 | #define CFG_BAUDRATE_TABLE \ | |
7a78f148 TT |
304 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
305 | ||
8a364f09 | 306 | #define CONFIG_CONSOLE ttyS0 |
7a78f148 | 307 | #define CONFIG_BAUDRATE 115200 |
2ad6b513 | 308 | |
d239d74b TT |
309 | #define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) |
310 | #define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) | |
2ad6b513 | 311 | |
bf0b542d | 312 | /* pass open firmware flat tree */ |
35cc4e48 | 313 | #define CONFIG_OF_LIBFDT 1 |
5b8bc606 KP |
314 | #define CONFIG_OF_BOARD_SETUP 1 |
315 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
2ad6b513 | 316 | |
7a78f148 TT |
317 | /* |
318 | * PCI | |
319 | */ | |
2ad6b513 TT |
320 | #ifdef CONFIG_PCI |
321 | ||
322 | #define CONFIG_MPC83XX_PCI2 | |
323 | ||
324 | /* | |
325 | * General PCI | |
326 | * Addresses are mapped 1-1. | |
327 | */ | |
328 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
329 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
330 | #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
331 | #define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) | |
332 | #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE | |
333 | #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
334 | #define CFG_PCI1_IO_BASE 0x00000000 | |
335 | #define CFG_PCI1_IO_PHYS 0xE2000000 | |
336 | #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
337 | ||
338 | #ifdef CONFIG_MPC83XX_PCI2 | |
339 | #define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) | |
340 | #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE | |
341 | #define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
342 | #define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) | |
343 | #define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE | |
344 | #define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
345 | #define CFG_PCI2_IO_BASE 0x00000000 | |
346 | #define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) | |
347 | #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ | |
348 | #endif | |
349 | ||
350 | #define _IO_BASE 0x00000000 /* points to PCI I/O space */ | |
351 | ||
352 | #define CONFIG_NET_MULTI | |
dd520bf3 | 353 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
2ad6b513 TT |
354 | |
355 | #ifdef CONFIG_RTL8139 | |
356 | /* This macro is used by RTL8139 but not defined in PPC architecture */ | |
357 | #define KSEG1ADDR(x) (x) | |
358 | #endif | |
359 | ||
360 | #ifndef CONFIG_PCI_PNP | |
361 | #define PCI_ENET0_IOADDR 0x00000000 | |
362 | #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE | |
363 | #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ | |
364 | #endif | |
365 | ||
366 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
367 | ||
368 | #endif | |
369 | ||
7a78f148 TT |
370 | #define PCI_66M |
371 | #ifdef PCI_66M | |
372 | #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ | |
373 | #else | |
374 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
375 | #endif | |
376 | ||
2ad6b513 TT |
377 | /* TSEC */ |
378 | ||
379 | #ifdef CONFIG_TSEC_ENET | |
380 | ||
2ad6b513 | 381 | #define CONFIG_NET_MULTI |
2ad6b513 | 382 | #define CONFIG_MII |
659e2f67 | 383 | #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ |
2ad6b513 | 384 | |
255a3577 | 385 | #define CONFIG_TSEC1 |
2ad6b513 | 386 | |
255a3577 | 387 | #ifdef CONFIG_TSEC1 |
10327dc5 | 388 | #define CONFIG_HAS_ETH0 |
255a3577 | 389 | #define CONFIG_TSEC1_NAME "TSEC0" |
dd520bf3 WD |
390 | #define CFG_TSEC1_OFFSET 0x24000 |
391 | #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ | |
2ad6b513 | 392 | #define TSEC1_PHYIDX 0 |
3a79013e | 393 | #define TSEC1_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
394 | #endif |
395 | ||
255a3577 | 396 | #ifdef CONFIG_TSEC2 |
7a78f148 | 397 | #define CONFIG_HAS_ETH1 |
255a3577 | 398 | #define CONFIG_TSEC2_NAME "TSEC1" |
dd520bf3 | 399 | #define CFG_TSEC2_OFFSET 0x25000 |
89c7784e | 400 | |
2ad6b513 TT |
401 | #define TSEC2_PHY_ADDR 4 |
402 | #define TSEC2_PHYIDX 0 | |
3a79013e | 403 | #define TSEC2_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
404 | #endif |
405 | ||
406 | #define CONFIG_ETHPRIME "Freescale TSEC" | |
407 | ||
408 | #endif | |
409 | ||
2ad6b513 TT |
410 | /* |
411 | * Environment | |
412 | */ | |
7a78f148 TT |
413 | #define CONFIG_ENV_OVERWRITE |
414 | ||
2ad6b513 TT |
415 | #ifndef CFG_RAMBOOT |
416 | #define CFG_ENV_IS_IN_FLASH | |
b2893e1f | 417 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
7a78f148 | 418 | #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ |
2ad6b513 TT |
419 | #define CFG_ENV_SIZE 0x2000 |
420 | #else | |
421 | #define CFG_NO_FLASH /* Flash is not usable now */ | |
00b1883a | 422 | #undef CONFIG_FLASH_CFI_DRIVER |
2ad6b513 TT |
423 | #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
424 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
425 | #define CFG_ENV_SIZE 0x2000 | |
426 | #endif | |
427 | ||
428 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
429 | #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
430 | ||
659e2f67 JL |
431 | /* |
432 | * BOOTP options | |
433 | */ | |
434 | #define CONFIG_BOOTP_BOOTFILESIZE | |
435 | #define CONFIG_BOOTP_BOOTPATH | |
436 | #define CONFIG_BOOTP_GATEWAY | |
437 | #define CONFIG_BOOTP_HOSTNAME | |
438 | ||
439 | ||
8ea5499a JL |
440 | /* |
441 | * Command line configuration. | |
442 | */ | |
443 | #include <config_cmd_default.h> | |
444 | ||
445 | #define CONFIG_CMD_CACHE | |
446 | #define CONFIG_CMD_DATE | |
447 | #define CONFIG_CMD_IRQ | |
448 | #define CONFIG_CMD_NET | |
449 | #define CONFIG_CMD_PING | |
450 | #define CONFIG_CMD_SDRAM | |
2ad6b513 TT |
451 | |
452 | #ifdef CONFIG_COMPACT_FLASH | |
8ea5499a JL |
453 | #define CONFIG_CMD_IDE |
454 | #define CONFIG_CMD_FAT | |
2ad6b513 TT |
455 | #endif |
456 | ||
457 | #ifdef CONFIG_PCI | |
8ea5499a | 458 | #define CONFIG_CMD_PCI |
2ad6b513 TT |
459 | #endif |
460 | ||
461 | #ifdef CONFIG_HARD_I2C | |
8ea5499a | 462 | #define CONFIG_CMD_I2C |
2ad6b513 TT |
463 | #endif |
464 | ||
2ad6b513 | 465 | /* Watchdog */ |
2ad6b513 | 466 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
2ad6b513 TT |
467 | |
468 | /* | |
469 | * Miscellaneous configurable options | |
470 | */ | |
dd520bf3 | 471 | #define CFG_LONGHELP /* undef to save memory */ |
7a78f148 TT |
472 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
473 | #define CFG_HUSH_PARSER /* Use the HUSH parser */ | |
474 | #define CFG_PROMPT_HUSH_PS2 "> " | |
475 | ||
2ad6b513 | 476 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
b2115757 | 477 | #define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ |
7a78f148 TT |
478 | |
479 | #ifdef CONFIG_MPC8349ITX | |
480 | #define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ | |
481 | #else | |
482 | #define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ | |
483 | #endif | |
2ad6b513 | 484 | |
8ea5499a | 485 | #if defined(CONFIG_CMD_KGDB) |
2ad6b513 TT |
486 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
487 | #else | |
488 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
489 | #endif | |
490 | ||
dd520bf3 | 491 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ |
2ad6b513 TT |
492 | #define CFG_MAXARGS 16 /* max number of command args */ |
493 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
494 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
495 | ||
496 | /* | |
497 | * For booting Linux, the board info and command line data | |
498 | * have to be in the first 8 MB of memory, since this is | |
499 | * the maximum mapped by the Linux kernel during initialization. | |
500 | */ | |
501 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ | |
502 | ||
2ad6b513 TT |
503 | #define CFG_HRCW_LOW (\ |
504 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
505 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
506 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
507 | HRCWL_VCO_1X2 |\ | |
508 | HRCWL_CORE_TO_CSB_2X1) | |
509 | ||
7a78f148 | 510 | #ifdef CFG_LOWBOOT |
2ad6b513 TT |
511 | #define CFG_HRCW_HIGH (\ |
512 | HRCWH_PCI_HOST |\ | |
7a78f148 | 513 | HRCWH_32_BIT_PCI |\ |
2ad6b513 | 514 | HRCWH_PCI1_ARBITER_ENABLE |\ |
7a78f148 | 515 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
516 | HRCWH_CORE_ENABLE |\ |
517 | HRCWH_FROM_0X00000100 |\ | |
518 | HRCWH_BOOTSEQ_DISABLE |\ | |
519 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
520 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
521 | HRCWH_TSEC1M_IN_GMII |\ | |
522 | HRCWH_TSEC2M_IN_GMII ) | |
523 | #else | |
524 | #define CFG_HRCW_HIGH (\ | |
525 | HRCWH_PCI_HOST |\ | |
526 | HRCWH_32_BIT_PCI |\ | |
527 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
7a78f148 | 528 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
529 | HRCWH_CORE_ENABLE |\ |
530 | HRCWH_FROM_0XFFF00100 |\ | |
531 | HRCWH_BOOTSEQ_DISABLE |\ | |
532 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
533 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
534 | HRCWH_TSEC1M_IN_GMII |\ | |
535 | HRCWH_TSEC2M_IN_GMII ) | |
536 | #endif | |
537 | ||
7a78f148 TT |
538 | /* |
539 | * System performance | |
540 | */ | |
2ad6b513 TT |
541 | #define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
542 | #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
543 | #define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ | |
544 | #define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
545 | #define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
be5e6181 | 546 | #define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ |
2ad6b513 | 547 | |
7a78f148 TT |
548 | /* |
549 | * System IO Config | |
550 | */ | |
2ad6b513 | 551 | #define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ |
98883332 | 552 | #define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) |
2ad6b513 | 553 | |
7a78f148 TT |
554 | #define CFG_HID0_INIT 0x000000000 |
555 | #define CFG_HID0_FINAL CFG_HID0_INIT | |
2ad6b513 | 556 | |
dd520bf3 | 557 | #define CFG_HID2 HID2_HBE |
31d82672 | 558 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
2ad6b513 | 559 | |
7a78f148 | 560 | /* DDR */ |
2ad6b513 TT |
561 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
562 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
563 | ||
7a78f148 | 564 | /* PCI */ |
2ad6b513 TT |
565 | #ifdef CONFIG_PCI |
566 | #define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
567 | #define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
568 | #define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
569 | #define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
570 | #else | |
571 | #define CFG_IBAT1L 0 | |
572 | #define CFG_IBAT1U 0 | |
573 | #define CFG_IBAT2L 0 | |
574 | #define CFG_IBAT2U 0 | |
575 | #endif | |
576 | ||
577 | #ifdef CONFIG_MPC83XX_PCI2 | |
578 | #define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
579 | #define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
580 | #define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
581 | #define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
582 | #else | |
583 | #define CFG_IBAT3L 0 | |
584 | #define CFG_IBAT3U 0 | |
585 | #define CFG_IBAT4L 0 | |
586 | #define CFG_IBAT4U 0 | |
587 | #endif | |
588 | ||
589 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
d239d74b TT |
590 | #define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
591 | #define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
2ad6b513 TT |
592 | |
593 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
594 | #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) | |
595 | #define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) | |
596 | ||
597 | #define CFG_IBAT7L 0 | |
598 | #define CFG_IBAT7U 0 | |
599 | ||
600 | #define CFG_DBAT0L CFG_IBAT0L | |
601 | #define CFG_DBAT0U CFG_IBAT0U | |
602 | #define CFG_DBAT1L CFG_IBAT1L | |
603 | #define CFG_DBAT1U CFG_IBAT1U | |
604 | #define CFG_DBAT2L CFG_IBAT2L | |
605 | #define CFG_DBAT2U CFG_IBAT2U | |
606 | #define CFG_DBAT3L CFG_IBAT3L | |
607 | #define CFG_DBAT3U CFG_IBAT3U | |
608 | #define CFG_DBAT4L CFG_IBAT4L | |
609 | #define CFG_DBAT4U CFG_IBAT4U | |
610 | #define CFG_DBAT5L CFG_IBAT5L | |
611 | #define CFG_DBAT5U CFG_IBAT5U | |
612 | #define CFG_DBAT6L CFG_IBAT6L | |
613 | #define CFG_DBAT6U CFG_IBAT6U | |
614 | #define CFG_DBAT7L CFG_IBAT7L | |
615 | #define CFG_DBAT7U CFG_IBAT7U | |
616 | ||
617 | /* | |
618 | * Internal Definitions | |
619 | * | |
620 | * Boot Flags | |
621 | */ | |
622 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
623 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
624 | ||
8ea5499a | 625 | #if defined(CONFIG_CMD_KGDB) |
2ad6b513 TT |
626 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
627 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
628 | #endif | |
629 | ||
630 | ||
631 | /* | |
632 | * Environment Configuration | |
633 | */ | |
634 | #define CONFIG_ENV_OVERWRITE | |
635 | ||
89c7784e | 636 | #ifdef CONFIG_HAS_ETH0 |
2ad6b513 TT |
637 | #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 |
638 | #endif | |
639 | ||
89c7784e | 640 | #ifdef CONFIG_HAS_ETH1 |
2ad6b513 TT |
641 | #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 |
642 | #endif | |
643 | ||
bf0b542d KP |
644 | #define CONFIG_IPADDR 192.168.1.253 |
645 | #define CONFIG_SERVERIP 192.168.1.1 | |
646 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
2ad6b513 | 647 | #define CONFIG_NETMASK 255.255.252.0 |
98883332 | 648 | #define CONFIG_NETDEV eth0 |
2ad6b513 | 649 | |
7a78f148 | 650 | #ifdef CONFIG_MPC8349ITX |
2ad6b513 | 651 | #define CONFIG_HOSTNAME mpc8349emitx |
7a78f148 TT |
652 | #else |
653 | #define CONFIG_HOSTNAME mpc8349emitxgp | |
be5e6181 TT |
654 | #endif |
655 | ||
7a78f148 TT |
656 | /* Default path and filenames */ |
657 | #define CONFIG_ROOTPATH /nfsroot/rootfs | |
658 | #define CONFIG_BOOTFILE uImage | |
659 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
2ad6b513 | 660 | |
7a78f148 TT |
661 | #ifdef CONFIG_MPC8349ITX |
662 | #define CONFIG_FDTFILE mpc8349emitx.dtb | |
2ad6b513 | 663 | #else |
7a78f148 | 664 | #define CONFIG_FDTFILE mpc8349emitxgp.dtb |
2ad6b513 TT |
665 | #endif |
666 | ||
7a78f148 TT |
667 | #define CONFIG_BOOTDELAY 0 |
668 | ||
2ad6b513 TT |
669 | #define XMK_STR(x) #x |
670 | #define MK_STR(x) XMK_STR(x) | |
671 | ||
98883332 TT |
672 | #define CONFIG_BOOTARGS \ |
673 | "root=/dev/nfs rw" \ | |
674 | " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ | |
53677ef1 | 675 | " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ |
98883332 TT |
676 | MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ |
677 | MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ | |
8a364f09 | 678 | " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) |
98883332 | 679 | |
dd520bf3 | 680 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
53677ef1 WD |
681 | "console=" MK_STR(CONFIG_CONSOLE) "\0" \ |
682 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ | |
683 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
684 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
685 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
686 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
687 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
688 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
689 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
dd520bf3 | 690 | "fdtaddr=400000\0" \ |
7a78f148 | 691 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" |
bf0b542d | 692 | |
dd520bf3 | 693 | #define CONFIG_NFSBOOTCOMMAND \ |
7a78f148 TT |
694 | "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ |
695 | " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
696 | " console=$console,$baudrate $othbootargs; " \ | |
697 | "tftp $loadaddr $bootfile;" \ | |
698 | "tftp $fdtaddr $fdtfile;" \ | |
699 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d | 700 | |
dd520bf3 | 701 | #define CONFIG_RAMBOOTCOMMAND \ |
7a78f148 TT |
702 | "setenv bootargs root=/dev/ram rw" \ |
703 | " console=$console,$baudrate $othbootargs; " \ | |
704 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
705 | "tftp $loadaddr $bootfile;" \ | |
706 | "tftp $fdtaddr $fdtfile;" \ | |
707 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
2ad6b513 TT |
708 | |
709 | #undef MK_STR | |
710 | #undef XMK_STR | |
711 | ||
712 | #endif |