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Commit | Line | Data |
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2ad6b513 | 1 | /* |
4c2e3da8 | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
2ad6b513 | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
2ad6b513 TT |
5 | */ |
6 | ||
7 | /* | |
7a78f148 | 8 | MPC8349E-mITX and MPC8349E-mITX-GP board configuration file |
2ad6b513 TT |
9 | |
10 | Memory map: | |
11 | ||
12 | 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) | |
13 | 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) | |
14 | 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) | |
15 | 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) | |
16 | 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) | |
17 | 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) | |
7a78f148 | 18 | 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) |
2ad6b513 | 19 | 0xF001_0000-0xF001_FFFF Local bus expansion slot |
7a78f148 TT |
20 | 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) |
21 | 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory | |
22 | 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) | |
2ad6b513 TT |
23 | |
24 | I2C address list: | |
dd520bf3 WD |
25 | Align. Board |
26 | Bus Addr Part No. Description Length Location | |
2ad6b513 | 27 | ---------------------------------------------------------------- |
dd520bf3 | 28 | I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
2ad6b513 | 29 | |
dd520bf3 WD |
30 | I2C1 0x20 PCF8574 I2C Expander 0 U8 |
31 | I2C1 0x21 PCF8574 I2C Expander 0 U10 | |
32 | I2C1 0x38 PCF8574A I2C Expander 0 U8 | |
33 | I2C1 0x39 PCF8574A I2C Expander 0 U10 | |
34 | I2C1 0x51 (DDR) DDR EEPROM 1 U1 | |
35 | I2C1 0x68 DS1339 RTC 1 U68 | |
2ad6b513 TT |
36 | |
37 | Note that a given board has *either* a pair of 8574s or a pair of 8574As. | |
38 | */ | |
39 | ||
40 | #ifndef __CONFIG_H | |
41 | #define __CONFIG_H | |
42 | ||
14d0a02a | 43 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) |
6d0f6bcf | 44 | #define CONFIG_SYS_LOWBOOT |
7a78f148 | 45 | #endif |
2ad6b513 TT |
46 | |
47 | /* | |
48 | * High Level Configuration Options | |
49 | */ | |
1a2e203b | 50 | #define CONFIG_MPC83xx 1 |
2c7920af | 51 | #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ |
2ad6b513 TT |
52 | #define CONFIG_MPC8349 /* MPC8349 specific */ |
53 | ||
2ae18241 WD |
54 | #ifndef CONFIG_SYS_TEXT_BASE |
55 | #define CONFIG_SYS_TEXT_BASE 0xFEF00000 | |
56 | #endif | |
57 | ||
396abba2 | 58 | #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ |
7a78f148 | 59 | |
89c7784e TT |
60 | #define CONFIG_MISC_INIT_F |
61 | #define CONFIG_MISC_INIT_R | |
7a78f148 | 62 | |
89c7784e TT |
63 | /* |
64 | * On-board devices | |
65 | */ | |
2ad6b513 | 66 | |
7a78f148 | 67 | #ifdef CONFIG_MPC8349ITX |
396abba2 JH |
68 | /* The CF card interface on the back of the board */ |
69 | #define CONFIG_COMPACT_FLASH | |
89c7784e | 70 | #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ |
c9e34fe2 | 71 | #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ |
c31e1326 | 72 | #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ |
7a78f148 | 73 | #endif |
2ad6b513 | 74 | |
7a78f148 TT |
75 | #define CONFIG_PCI |
76 | #define CONFIG_RTC_DS1337 | |
00f792e0 | 77 | #define CONFIG_SYS_I2C |
7a78f148 | 78 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ |
2ad6b513 | 79 | |
7a78f148 TT |
80 | /* |
81 | * Device configurations | |
82 | */ | |
83 | ||
84 | /* I2C */ | |
00f792e0 HS |
85 | #ifdef CONFIG_SYS_I2C |
86 | #define CONFIG_SYS_I2C_FSL | |
87 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
88 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
89 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
90 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
91 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
92 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
2ad6b513 | 93 | |
6d0f6bcf | 94 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ |
b7be63ab | 95 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
6d0f6bcf JCPV |
96 | |
97 | #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ | |
98 | #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ | |
99 | #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ | |
100 | #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ | |
101 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ | |
396abba2 JH |
102 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ |
103 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ | |
2ad6b513 | 104 | |
2ad6b513 | 105 | /* Don't probe these addresses: */ |
396abba2 | 106 | #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ |
6d0f6bcf JCPV |
107 | {1, CONFIG_SYS_I2C_8574_ADDR2}, \ |
108 | {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ | |
396abba2 | 109 | {1, CONFIG_SYS_I2C_8574A_ADDR2} } |
2ad6b513 | 110 | /* Bit definitions for the 8574[A] I2C expander */ |
396abba2 JH |
111 | /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ |
112 | #define I2C_8574_REVISION 0x03 | |
2ad6b513 TT |
113 | #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ |
114 | #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ | |
115 | #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ | |
116 | #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ | |
117 | ||
2ad6b513 TT |
118 | #endif |
119 | ||
7a78f148 TT |
120 | /* Compact Flash */ |
121 | #ifdef CONFIG_COMPACT_FLASH | |
2ad6b513 | 122 | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_IDE_MAXBUS 1 |
124 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
2ad6b513 | 125 | |
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
127 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE | |
128 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 | |
129 | #define CONFIG_SYS_ATA_REG_OFFSET 0 | |
130 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 | |
131 | #define CONFIG_SYS_ATA_STRIDE 2 | |
2ad6b513 | 132 | |
396abba2 JH |
133 | /* If a CF card is not inserted, time out quickly */ |
134 | #define ATA_RESET_TIME 1 | |
2ad6b513 | 135 | |
c9e34fe2 VG |
136 | #endif |
137 | ||
138 | /* | |
139 | * SATA | |
140 | */ | |
141 | #ifdef CONFIG_SATA_SIL3114 | |
142 | ||
143 | #define CONFIG_SYS_SATA_MAX_DEVICE 4 | |
144 | #define CONFIG_LIBATA | |
145 | #define CONFIG_LBA48 | |
2ad6b513 | 146 | |
7a78f148 | 147 | #endif |
2ad6b513 | 148 | |
c31e1326 VG |
149 | #ifdef CONFIG_SYS_USB_HOST |
150 | /* | |
151 | * Support USB | |
152 | */ | |
153 | #define CONFIG_CMD_USB | |
154 | #define CONFIG_USB_STORAGE | |
155 | #define CONFIG_USB_EHCI | |
156 | #define CONFIG_USB_EHCI_FSL | |
157 | ||
158 | /* Current USB implementation supports the only USB controller, | |
159 | * so we have to choose between the MPH or the DR ones */ | |
160 | #if 1 | |
161 | #define CONFIG_HAS_FSL_MPH_USB | |
162 | #else | |
163 | #define CONFIG_HAS_FSL_DR_USB | |
164 | #endif | |
165 | ||
166 | #endif | |
167 | ||
2ad6b513 | 168 | /* |
7a78f148 | 169 | * DDR Setup |
2ad6b513 | 170 | */ |
396abba2 | 171 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
173 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
174 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
396abba2 | 175 | #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_MEMTEST_END 0x2000 |
177 | ||
396abba2 JH |
178 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
179 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) | |
f64702b7 | 180 | |
b7be63ab VG |
181 | #define CONFIG_VERY_BIG_RAM |
182 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) | |
183 | ||
00f792e0 | 184 | #ifdef CONFIG_SYS_I2C |
7a78f148 TT |
185 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
186 | #endif | |
187 | ||
396abba2 JH |
188 | /* No SPD? Then manually set up DDR parameters */ |
189 | #ifndef CONFIG_SPD_EEPROM | |
190 | #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ | |
2e651b24 | 191 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
396abba2 JH |
192 | | CSCONFIG_ROW_BIT_13 \ |
193 | | CSCONFIG_COL_BIT_10) | |
2ad6b513 | 194 | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_DDR_TIMING_1 0x26242321 |
196 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ | |
2ad6b513 TT |
197 | #endif |
198 | ||
7a78f148 TT |
199 | /* |
200 | *Flash on the Local Bus | |
201 | */ | |
202 | ||
396abba2 JH |
203 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
204 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
206 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
396abba2 JH |
207 | /* 127 64KB sectors + 8 8KB sectors per device */ |
208 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
210 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
211 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
7a78f148 TT |
212 | |
213 | /* The ITX has two flash chips, but the ITX-GP has only one. To support both | |
214 | boards, we say we have two, but don't display a message if we find only one. */ | |
6d0f6bcf | 215 | #define CONFIG_SYS_FLASH_QUIET_TEST |
396abba2 JH |
216 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
217 | #define CONFIG_SYS_FLASH_BANKS_LIST \ | |
218 | {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} | |
219 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ | |
396abba2 | 220 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
7a78f148 | 221 | |
89c7784e TT |
222 | /* Vitesse 7385 */ |
223 | ||
224 | #ifdef CONFIG_VSC7385_ENET | |
225 | ||
226 | #define CONFIG_TSEC2 | |
227 | ||
228 | /* The flash address and size of the VSC7385 firmware image */ | |
229 | #define CONFIG_VSC7385_IMAGE 0xFEFFE000 | |
230 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
231 | ||
232 | #endif | |
233 | ||
7a78f148 TT |
234 | /* |
235 | * BRx, ORx, LBLAWBARx, and LBLAWARx | |
236 | */ | |
237 | ||
238 | /* Flash */ | |
2ad6b513 | 239 | |
7d6a0982 JH |
240 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
241 | | BR_PS_16 \ | |
242 | | BR_MS_GPCM \ | |
243 | | BR_V) | |
244 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
396abba2 JH |
245 | | OR_UPM_XAM \ |
246 | | OR_GPCM_CSNT \ | |
247 | | OR_GPCM_ACS_DIV2 \ | |
248 | | OR_GPCM_XACS \ | |
249 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
250 | | OR_GPCM_TRLX_SET \ |
251 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 252 | | OR_GPCM_EAD) |
6d0f6bcf | 253 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
7d6a0982 | 254 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) |
2ad6b513 | 255 | |
7a78f148 | 256 | /* Vitesse 7385 */ |
2ad6b513 | 257 | |
6d0f6bcf | 258 | #define CONFIG_SYS_VSC7385_BASE 0xF8000000 |
2ad6b513 | 259 | |
89c7784e TT |
260 | #ifdef CONFIG_VSC7385_ENET |
261 | ||
7d6a0982 JH |
262 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ |
263 | | BR_PS_8 \ | |
264 | | BR_MS_GPCM \ | |
265 | | BR_V) | |
396abba2 JH |
266 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ |
267 | | OR_GPCM_CSNT \ | |
268 | | OR_GPCM_XACS \ | |
269 | | OR_GPCM_SCY_15 \ | |
270 | | OR_GPCM_SETA \ | |
7d6a0982 JH |
271 | | OR_GPCM_TRLX_SET \ |
272 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 273 | | OR_GPCM_EAD) |
2ad6b513 | 274 | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE |
276 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) | |
2ad6b513 | 277 | |
7a78f148 | 278 | #endif |
2ad6b513 | 279 | |
7a78f148 TT |
280 | /* LED */ |
281 | ||
396abba2 | 282 | #define CONFIG_SYS_LED_BASE 0xF9000000 |
7d6a0982 JH |
283 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ |
284 | | BR_PS_8 \ | |
285 | | BR_MS_GPCM \ | |
286 | | BR_V) | |
396abba2 JH |
287 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ |
288 | | OR_GPCM_CSNT \ | |
289 | | OR_GPCM_ACS_DIV2 \ | |
290 | | OR_GPCM_XACS \ | |
291 | | OR_GPCM_SCY_9 \ | |
7d6a0982 JH |
292 | | OR_GPCM_TRLX_SET \ |
293 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 294 | | OR_GPCM_EAD) |
7a78f148 TT |
295 | |
296 | /* Compact Flash */ | |
2ad6b513 TT |
297 | |
298 | #ifdef CONFIG_COMPACT_FLASH | |
299 | ||
396abba2 | 300 | #define CONFIG_SYS_CF_BASE 0xF0000000 |
2ad6b513 | 301 | |
396abba2 JH |
302 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ |
303 | | BR_PS_16 \ | |
304 | | BR_MS_UPMA \ | |
305 | | BR_V) | |
306 | #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) | |
2ad6b513 | 307 | |
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE |
309 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) | |
2ad6b513 TT |
310 | |
311 | #endif | |
312 | ||
7a78f148 TT |
313 | /* |
314 | * U-Boot memory configuration | |
315 | */ | |
14d0a02a | 316 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
2ad6b513 | 317 | |
6d0f6bcf JCPV |
318 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
319 | #define CONFIG_SYS_RAMBOOT | |
2ad6b513 | 320 | #else |
6d0f6bcf | 321 | #undef CONFIG_SYS_RAMBOOT |
2ad6b513 TT |
322 | #endif |
323 | ||
6d0f6bcf | 324 | #define CONFIG_SYS_INIT_RAM_LOCK |
396abba2 JH |
325 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
326 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
2ad6b513 | 327 | |
396abba2 JH |
328 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
329 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 330 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
2ad6b513 | 331 | |
6d0f6bcf | 332 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
396abba2 | 333 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
c8a90646 | 334 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
2ad6b513 TT |
335 | |
336 | /* | |
337 | * Local Bus LCRR and LBCR regs | |
338 | * LCRR: DLL bypass, Clock divider is 4 | |
339 | * External Local Bus rate is | |
340 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
341 | */ | |
c7190f02 KP |
342 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
343 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 344 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
2ad6b513 | 345 | |
396abba2 JH |
346 | /* LB sdram refresh timer, about 6us */ |
347 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
348 | /* LB refresh timer prescal, 266MHz/32*/ | |
349 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
2ad6b513 | 350 | |
2ad6b513 TT |
351 | /* |
352 | * Serial Port | |
353 | */ | |
354 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
355 | #define CONFIG_SYS_NS16550 |
356 | #define CONFIG_SYS_NS16550_SERIAL | |
357 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
358 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
2ad6b513 | 359 | |
6d0f6bcf | 360 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
396abba2 | 361 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
7a78f148 | 362 | |
8a364f09 | 363 | #define CONFIG_CONSOLE ttyS0 |
7a78f148 | 364 | #define CONFIG_BAUDRATE 115200 |
2ad6b513 | 365 | |
6d0f6bcf JCPV |
366 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
367 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
2ad6b513 | 368 | |
bf0b542d | 369 | /* pass open firmware flat tree */ |
35cc4e48 | 370 | #define CONFIG_OF_LIBFDT 1 |
5b8bc606 KP |
371 | #define CONFIG_OF_BOARD_SETUP 1 |
372 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
2ad6b513 | 373 | |
7a78f148 TT |
374 | /* |
375 | * PCI | |
376 | */ | |
2ad6b513 | 377 | #ifdef CONFIG_PCI |
842033e6 | 378 | #define CONFIG_PCI_INDIRECT_BRIDGE |
2ad6b513 TT |
379 | |
380 | #define CONFIG_MPC83XX_PCI2 | |
381 | ||
382 | /* | |
383 | * General PCI | |
384 | * Addresses are mapped 1-1. | |
385 | */ | |
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
387 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
388 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
389 | #define CONFIG_SYS_PCI1_MMIO_BASE \ |
390 | (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
6d0f6bcf JCPV |
391 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
392 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
393 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
394 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
395 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
2ad6b513 TT |
396 | |
397 | #ifdef CONFIG_MPC83XX_PCI2 | |
396abba2 JH |
398 | #define CONFIG_SYS_PCI2_MEM_BASE \ |
399 | (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) | |
6d0f6bcf JCPV |
400 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE |
401 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
402 | #define CONFIG_SYS_PCI2_MMIO_BASE \ |
403 | (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) | |
6d0f6bcf JCPV |
404 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE |
405 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
406 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
407 | #define CONFIG_SYS_PCI2_IO_PHYS \ | |
408 | (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) | |
409 | #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ | |
2ad6b513 TT |
410 | #endif |
411 | ||
dd520bf3 | 412 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
2ad6b513 | 413 | |
2ad6b513 TT |
414 | #ifndef CONFIG_PCI_PNP |
415 | #define PCI_ENET0_IOADDR 0x00000000 | |
6d0f6bcf | 416 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE |
2ad6b513 TT |
417 | #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ |
418 | #endif | |
419 | ||
420 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
421 | ||
422 | #endif | |
423 | ||
2ae18241 WD |
424 | #define CONFIG_PCI_66M |
425 | #ifdef CONFIG_PCI_66M | |
7a78f148 TT |
426 | #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ |
427 | #else | |
428 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
429 | #endif | |
430 | ||
2ad6b513 TT |
431 | /* TSEC */ |
432 | ||
433 | #ifdef CONFIG_TSEC_ENET | |
434 | ||
2ad6b513 | 435 | #define CONFIG_MII |
659e2f67 | 436 | #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ |
2ad6b513 | 437 | |
255a3577 | 438 | #define CONFIG_TSEC1 |
2ad6b513 | 439 | |
255a3577 | 440 | #ifdef CONFIG_TSEC1 |
10327dc5 | 441 | #define CONFIG_HAS_ETH0 |
255a3577 | 442 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 443 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
dd520bf3 | 444 | #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ |
2ad6b513 | 445 | #define TSEC1_PHYIDX 0 |
3a79013e | 446 | #define TSEC1_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
447 | #endif |
448 | ||
255a3577 | 449 | #ifdef CONFIG_TSEC2 |
7a78f148 | 450 | #define CONFIG_HAS_ETH1 |
255a3577 | 451 | #define CONFIG_TSEC2_NAME "TSEC1" |
6d0f6bcf | 452 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e | 453 | |
2ad6b513 TT |
454 | #define TSEC2_PHY_ADDR 4 |
455 | #define TSEC2_PHYIDX 0 | |
3a79013e | 456 | #define TSEC2_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
457 | #endif |
458 | ||
459 | #define CONFIG_ETHPRIME "Freescale TSEC" | |
460 | ||
461 | #endif | |
462 | ||
2ad6b513 TT |
463 | /* |
464 | * Environment | |
465 | */ | |
7a78f148 TT |
466 | #define CONFIG_ENV_OVERWRITE |
467 | ||
6d0f6bcf | 468 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 469 | #define CONFIG_ENV_IS_IN_FLASH |
396abba2 JH |
470 | #define CONFIG_ENV_ADDR \ |
471 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 | 472 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ |
396abba2 | 473 | #define CONFIG_ENV_SIZE 0x2000 |
2ad6b513 | 474 | #else |
396abba2 | 475 | #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ |
00b1883a | 476 | #undef CONFIG_FLASH_CFI_DRIVER |
93f6d725 | 477 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
396abba2 JH |
478 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
479 | #define CONFIG_ENV_SIZE 0x2000 | |
2ad6b513 TT |
480 | #endif |
481 | ||
482 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
6d0f6bcf | 483 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
2ad6b513 | 484 | |
659e2f67 JL |
485 | /* |
486 | * BOOTP options | |
487 | */ | |
488 | #define CONFIG_BOOTP_BOOTFILESIZE | |
489 | #define CONFIG_BOOTP_BOOTPATH | |
490 | #define CONFIG_BOOTP_GATEWAY | |
491 | #define CONFIG_BOOTP_HOSTNAME | |
492 | ||
493 | ||
8ea5499a JL |
494 | /* |
495 | * Command line configuration. | |
496 | */ | |
497 | #include <config_cmd_default.h> | |
498 | ||
499 | #define CONFIG_CMD_CACHE | |
500 | #define CONFIG_CMD_DATE | |
501 | #define CONFIG_CMD_IRQ | |
502 | #define CONFIG_CMD_NET | |
503 | #define CONFIG_CMD_PING | |
b7be63ab | 504 | #define CONFIG_CMD_DHCP |
8ea5499a | 505 | #define CONFIG_CMD_SDRAM |
2ad6b513 | 506 | |
c31e1326 | 507 | #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ |
396abba2 JH |
508 | || defined(CONFIG_USB_STORAGE) |
509 | #define CONFIG_DOS_PARTITION | |
510 | #define CONFIG_CMD_FAT | |
511 | #define CONFIG_SUPPORT_VFAT | |
c9e34fe2 VG |
512 | #endif |
513 | ||
2ad6b513 | 514 | #ifdef CONFIG_COMPACT_FLASH |
396abba2 | 515 | #define CONFIG_CMD_IDE |
c9e34fe2 VG |
516 | #endif |
517 | ||
518 | #ifdef CONFIG_SATA_SIL3114 | |
396abba2 | 519 | #define CONFIG_CMD_SATA |
c31e1326 VG |
520 | #endif |
521 | ||
522 | #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) | |
396abba2 | 523 | #define CONFIG_CMD_EXT2 |
2ad6b513 TT |
524 | #endif |
525 | ||
526 | #ifdef CONFIG_PCI | |
396abba2 | 527 | #define CONFIG_CMD_PCI |
2ad6b513 TT |
528 | #endif |
529 | ||
00f792e0 | 530 | #ifdef CONFIG_SYS_I2C |
396abba2 | 531 | #define CONFIG_CMD_I2C |
2ad6b513 TT |
532 | #endif |
533 | ||
2ad6b513 | 534 | /* Watchdog */ |
2ad6b513 | 535 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
2ad6b513 TT |
536 | |
537 | /* | |
538 | * Miscellaneous configurable options | |
539 | */ | |
396abba2 JH |
540 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
541 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
542 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
543 | #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ | |
7a78f148 | 544 | |
6d0f6bcf | 545 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
05f91a65 | 546 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
7a78f148 TT |
547 | |
548 | #ifdef CONFIG_MPC8349ITX | |
396abba2 | 549 | #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ |
7a78f148 | 550 | #else |
396abba2 | 551 | #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ |
7a78f148 | 552 | #endif |
2ad6b513 | 553 | |
8ea5499a | 554 | #if defined(CONFIG_CMD_KGDB) |
396abba2 | 555 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
2ad6b513 | 556 | #else |
396abba2 | 557 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
2ad6b513 TT |
558 | #endif |
559 | ||
396abba2 JH |
560 | /* Print Buffer Size */ |
561 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
562 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
563 | /* Boot Argument Buffer Size */ | |
564 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
565 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
2ad6b513 TT |
566 | |
567 | /* | |
568 | * For booting Linux, the board info and command line data | |
9f530d59 | 569 | * have to be in the first 256 MB of memory, since this is |
2ad6b513 TT |
570 | * the maximum mapped by the Linux kernel during initialization. |
571 | */ | |
396abba2 JH |
572 | /* Initial Memory map for Linux*/ |
573 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
2ad6b513 | 574 | |
6d0f6bcf | 575 | #define CONFIG_SYS_HRCW_LOW (\ |
2ad6b513 TT |
576 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
577 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
578 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
579 | HRCWL_VCO_1X2 |\ | |
580 | HRCWL_CORE_TO_CSB_2X1) | |
581 | ||
6d0f6bcf JCPV |
582 | #ifdef CONFIG_SYS_LOWBOOT |
583 | #define CONFIG_SYS_HRCW_HIGH (\ | |
2ad6b513 | 584 | HRCWH_PCI_HOST |\ |
7a78f148 | 585 | HRCWH_32_BIT_PCI |\ |
2ad6b513 | 586 | HRCWH_PCI1_ARBITER_ENABLE |\ |
7a78f148 | 587 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
588 | HRCWH_CORE_ENABLE |\ |
589 | HRCWH_FROM_0X00000100 |\ | |
590 | HRCWH_BOOTSEQ_DISABLE |\ | |
591 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
592 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
593 | HRCWH_TSEC1M_IN_GMII |\ | |
396abba2 | 594 | HRCWH_TSEC2M_IN_GMII) |
2ad6b513 | 595 | #else |
6d0f6bcf | 596 | #define CONFIG_SYS_HRCW_HIGH (\ |
2ad6b513 TT |
597 | HRCWH_PCI_HOST |\ |
598 | HRCWH_32_BIT_PCI |\ | |
599 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
7a78f148 | 600 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
601 | HRCWH_CORE_ENABLE |\ |
602 | HRCWH_FROM_0XFFF00100 |\ | |
603 | HRCWH_BOOTSEQ_DISABLE |\ | |
604 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
605 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
606 | HRCWH_TSEC1M_IN_GMII |\ | |
396abba2 | 607 | HRCWH_TSEC2M_IN_GMII) |
2ad6b513 TT |
608 | #endif |
609 | ||
7a78f148 TT |
610 | /* |
611 | * System performance | |
612 | */ | |
6d0f6bcf | 613 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
396abba2 | 614 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
6d0f6bcf JCPV |
615 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
616 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
617 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
618 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
c31e1326 VG |
619 | #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ |
620 | #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ | |
2ad6b513 | 621 | |
7a78f148 TT |
622 | /* |
623 | * System IO Config | |
624 | */ | |
396abba2 JH |
625 | /* Needed for gigabit to work on TSEC 1 */ |
626 | #define CONFIG_SYS_SICRH SICRH_TSOBI1 | |
627 | /* USB DR as device + USB MPH as host */ | |
628 | #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) | |
2ad6b513 | 629 | |
1a2e203b KP |
630 | #define CONFIG_SYS_HID0_INIT 0x00000000 |
631 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE | |
2ad6b513 | 632 | |
6d0f6bcf | 633 | #define CONFIG_SYS_HID2 HID2_HBE |
31d82672 | 634 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
2ad6b513 | 635 | |
7a78f148 | 636 | /* DDR */ |
396abba2 | 637 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 638 | | BATL_PP_RW \ |
396abba2 JH |
639 | | BATL_MEMCOHERENCE) |
640 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
641 | | BATU_BL_256M \ | |
642 | | BATU_VS \ | |
643 | | BATU_VP) | |
2ad6b513 | 644 | |
7a78f148 | 645 | /* PCI */ |
2ad6b513 | 646 | #ifdef CONFIG_PCI |
396abba2 | 647 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 648 | | BATL_PP_RW \ |
396abba2 JH |
649 | | BATL_MEMCOHERENCE) |
650 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
651 | | BATU_BL_256M \ | |
652 | | BATU_VS \ | |
653 | | BATU_VP) | |
654 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 655 | | BATL_PP_RW \ |
396abba2 JH |
656 | | BATL_CACHEINHIBIT \ |
657 | | BATL_GUARDEDSTORAGE) | |
658 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
659 | | BATU_BL_256M \ | |
660 | | BATU_VS \ | |
661 | | BATU_VP) | |
2ad6b513 | 662 | #else |
6d0f6bcf JCPV |
663 | #define CONFIG_SYS_IBAT1L 0 |
664 | #define CONFIG_SYS_IBAT1U 0 | |
665 | #define CONFIG_SYS_IBAT2L 0 | |
666 | #define CONFIG_SYS_IBAT2U 0 | |
2ad6b513 TT |
667 | #endif |
668 | ||
669 | #ifdef CONFIG_MPC83XX_PCI2 | |
396abba2 | 670 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
72cd4087 | 671 | | BATL_PP_RW \ |
396abba2 JH |
672 | | BATL_MEMCOHERENCE) |
673 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
674 | | BATU_BL_256M \ | |
675 | | BATU_VS \ | |
676 | | BATU_VP) | |
677 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
72cd4087 | 678 | | BATL_PP_RW \ |
396abba2 JH |
679 | | BATL_CACHEINHIBIT \ |
680 | | BATL_GUARDEDSTORAGE) | |
681 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
682 | | BATU_BL_256M \ | |
683 | | BATU_VS \ | |
684 | | BATU_VP) | |
2ad6b513 | 685 | #else |
6d0f6bcf JCPV |
686 | #define CONFIG_SYS_IBAT3L 0 |
687 | #define CONFIG_SYS_IBAT3U 0 | |
688 | #define CONFIG_SYS_IBAT4L 0 | |
689 | #define CONFIG_SYS_IBAT4U 0 | |
2ad6b513 TT |
690 | #endif |
691 | ||
692 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
396abba2 | 693 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 694 | | BATL_PP_RW \ |
396abba2 JH |
695 | | BATL_CACHEINHIBIT \ |
696 | | BATL_GUARDEDSTORAGE) | |
697 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
698 | | BATU_BL_256M \ | |
699 | | BATU_VS \ | |
700 | | BATU_VP) | |
2ad6b513 TT |
701 | |
702 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
396abba2 | 703 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
72cd4087 | 704 | | BATL_PP_RW \ |
396abba2 JH |
705 | | BATL_MEMCOHERENCE \ |
706 | | BATL_GUARDEDSTORAGE) | |
707 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ | |
708 | | BATU_BL_256M \ | |
709 | | BATU_VS \ | |
710 | | BATU_VP) | |
6d0f6bcf JCPV |
711 | |
712 | #define CONFIG_SYS_IBAT7L 0 | |
713 | #define CONFIG_SYS_IBAT7U 0 | |
714 | ||
715 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
716 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
717 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
718 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
719 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
720 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
721 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
722 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
723 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
724 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
725 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
726 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
727 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
728 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
729 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
730 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
2ad6b513 | 731 | |
8ea5499a | 732 | #if defined(CONFIG_CMD_KGDB) |
2ad6b513 TT |
733 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
734 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
735 | #endif | |
736 | ||
737 | ||
738 | /* | |
739 | * Environment Configuration | |
740 | */ | |
741 | #define CONFIG_ENV_OVERWRITE | |
742 | ||
396abba2 | 743 | #define CONFIG_NETDEV "eth0" |
2ad6b513 | 744 | |
7a78f148 | 745 | #ifdef CONFIG_MPC8349ITX |
396abba2 | 746 | #define CONFIG_HOSTNAME "mpc8349emitx" |
7a78f148 | 747 | #else |
396abba2 | 748 | #define CONFIG_HOSTNAME "mpc8349emitxgp" |
be5e6181 TT |
749 | #endif |
750 | ||
7a78f148 | 751 | /* Default path and filenames */ |
8b3637c6 | 752 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
b3f44c21 | 753 | #define CONFIG_BOOTFILE "uImage" |
396abba2 JH |
754 | /* U-Boot image on TFTP server */ |
755 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
2ad6b513 | 756 | |
7a78f148 | 757 | #ifdef CONFIG_MPC8349ITX |
396abba2 | 758 | #define CONFIG_FDTFILE "mpc8349emitx.dtb" |
2ad6b513 | 759 | #else |
396abba2 | 760 | #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" |
2ad6b513 TT |
761 | #endif |
762 | ||
05f91a65 | 763 | #define CONFIG_BOOTDELAY 6 |
7a78f148 | 764 | |
98883332 TT |
765 | #define CONFIG_BOOTARGS \ |
766 | "root=/dev/nfs rw" \ | |
5368c55d MV |
767 | " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ |
768 | " ip=" __stringify(CONFIG_IPADDR) ":" \ | |
769 | __stringify(CONFIG_SERVERIP) ":" \ | |
770 | __stringify(CONFIG_GATEWAYIP) ":" \ | |
771 | __stringify(CONFIG_NETMASK) ":" \ | |
396abba2 | 772 | CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ |
5368c55d | 773 | " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) |
98883332 | 774 | |
dd520bf3 | 775 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d | 776 | "console=" __stringify(CONFIG_CONSOLE) "\0" \ |
396abba2 JH |
777 | "netdev=" CONFIG_NETDEV "\0" \ |
778 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
53677ef1 | 779 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
780 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
781 | " +$filesize; " \ | |
782 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
783 | " +$filesize; " \ | |
784 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
785 | " $filesize; " \ | |
786 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
787 | " +$filesize; " \ | |
788 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
789 | " $filesize\0" \ | |
05f91a65 | 790 | "fdtaddr=780000\0" \ |
396abba2 | 791 | "fdtfile=" CONFIG_FDTFILE "\0" |
bf0b542d | 792 | |
dd520bf3 | 793 | #define CONFIG_NFSBOOTCOMMAND \ |
7a78f148 | 794 | "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ |
396abba2 | 795 | " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ |
7a78f148 TT |
796 | " console=$console,$baudrate $othbootargs; " \ |
797 | "tftp $loadaddr $bootfile;" \ | |
798 | "tftp $fdtaddr $fdtfile;" \ | |
799 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d | 800 | |
dd520bf3 | 801 | #define CONFIG_RAMBOOTCOMMAND \ |
7a78f148 TT |
802 | "setenv bootargs root=/dev/ram rw" \ |
803 | " console=$console,$baudrate $othbootargs; " \ | |
804 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
805 | "tftp $loadaddr $bootfile;" \ | |
806 | "tftp $fdtaddr $fdtfile;" \ | |
807 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
2ad6b513 | 808 | |
2ad6b513 | 809 | #endif |