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Commit | Line | Data |
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fab6f556 AV |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
5 | * Copyright (C) 2007 Logic Product Development, Inc. | |
6 | * Peter Barada <peterb@logicpd.com> | |
7 | * | |
8 | * Copyright (C) 2007 MontaVista Software, Inc. | |
9 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
10 | * | |
1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
fab6f556 AV |
12 | */ |
13 | ||
14 | #ifndef __CONFIG_H | |
15 | #define __CONFIG_H | |
16 | ||
fab6f556 AV |
17 | /* |
18 | * High Level Configuration Options | |
19 | */ | |
20 | #define CONFIG_E300 1 /* E300 family */ | |
21 | #define CONFIG_QE 1 /* Has QE */ | |
0f898604 | 22 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
fab6f556 AV |
23 | #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ |
24 | #define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ | |
25 | ||
2ae18241 WD |
26 | #define CONFIG_SYS_TEXT_BASE 0xFF800000 |
27 | ||
fab6f556 AV |
28 | /* |
29 | * System Clock Setup | |
30 | */ | |
31 | #ifdef CONFIG_CLKIN_33MHZ | |
f700e7df AV |
32 | #define CONFIG_83XX_CLKIN 33333333 |
33 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
2ae18241 | 34 | #define CONFIG_PCI_33M 1 |
fab6f556 AV |
35 | #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1 |
36 | #else | |
37 | #define CONFIG_83XX_CLKIN 66000000 | |
38 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
2ae18241 | 39 | #define CONFIG_PCI_66M 1 |
fab6f556 AV |
40 | #define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1 |
41 | #endif /* CONFIG_CLKIN_33MHZ */ | |
42 | ||
43 | /* | |
44 | * Hardware Reset Configuration Word | |
45 | */ | |
6d0f6bcf | 46 | #define CONFIG_SYS_HRCW_LOW (\ |
fab6f556 AV |
47 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
48 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
49 | HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\ | |
50 | HRCWL_CORE_TO_CSB_2X1 |\ | |
51 | HRCWL_CE_TO_PLL_1X15) | |
52 | ||
6d0f6bcf | 53 | #define CONFIG_SYS_HRCW_HIGH (\ |
fab6f556 AV |
54 | HRCWH_PCI_HOST |\ |
55 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
56 | HRCWH_PCICKDRV_ENABLE |\ | |
57 | HRCWH_CORE_ENABLE |\ | |
58 | HRCWH_FROM_0X00000100 |\ | |
59 | HRCWH_BOOTSEQ_DISABLE |\ | |
60 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
61 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
62 | HRCWH_SECONDARY_DDR_DISABLE |\ | |
63 | HRCWH_BIG_ENDIAN |\ | |
64 | HRCWH_LALE_EARLY) | |
65 | ||
66 | /* | |
67 | * System IO Config | |
68 | */ | |
6d0f6bcf JCPV |
69 | #define CONFIG_SYS_SICRH 0x00000000 |
70 | #define CONFIG_SYS_SICRL 0x40000000 | |
fab6f556 | 71 | |
fab6f556 AV |
72 | #define CONFIG_BOARD_EARLY_INIT_R |
73 | ||
74 | /* | |
75 | * IMMR new address | |
76 | */ | |
6d0f6bcf | 77 | #define CONFIG_SYS_IMMR 0xE0000000 |
fab6f556 AV |
78 | |
79 | /* | |
80 | * DDR Setup | |
81 | */ | |
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
83 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
84 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
9a986550 JH |
85 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
86 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
fab6f556 | 87 | |
6d0f6bcf | 88 | #define CONFIG_SYS_83XX_DDR_USES_CS0 |
fab6f556 | 89 | |
d892b2db AV |
90 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
91 | #define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
fab6f556 AV |
92 | |
93 | /* | |
94 | * DDRCDR - DDR Control Driver Register | |
95 | */ | |
2fef4020 JH |
96 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ |
97 | | DDRCDR_ODT \ | |
98 | | DDRCDR_Q_DRN) | |
99 | /* 0x80080001 */ | |
fab6f556 AV |
100 | |
101 | #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ | |
102 | ||
103 | /* | |
104 | * Manually set up DDR parameters | |
105 | */ | |
106 | #define CONFIG_DDR_II | |
6d0f6bcf | 107 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
2fef4020 | 108 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f |
9a986550 JH |
109 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
110 | | CSCONFIG_ROW_BIT_13 \ | |
111 | | CSCONFIG_COL_BIT_10 \ | |
2fef4020 | 112 | | CSCONFIG_ODT_WR_ONLY_CURRENT) |
9a986550 JH |
113 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
114 | | SDRAM_CFG_ECC_EN) | |
6d0f6bcf | 115 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 |
9a986550 JH |
116 | #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) |
117 | #define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \ | |
118 | | (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_DDR_MODE 0x47800432 |
120 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
d892b2db | 121 | |
6d0f6bcf | 122 | #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ |
d892b2db AV |
123 | (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ |
124 | (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ | |
125 | (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ | |
126 | (0 << TIMING_CFG0_WWT_SHIFT) | \ | |
127 | (0 << TIMING_CFG0_RRT_SHIFT) | \ | |
128 | (0 << TIMING_CFG0_WRT_SHIFT) | \ | |
129 | (0 << TIMING_CFG0_RWT_SHIFT)) | |
130 | ||
9a986550 JH |
131 | #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \ |
132 | (2 << TIMING_CFG1_WRTORD_SHIFT) | \ | |
133 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ | |
134 | (3 << TIMING_CFG1_WRREC_SHIFT) | \ | |
d892b2db | 135 | (10 << TIMING_CFG1_REFREC_SHIFT) | \ |
9a986550 JH |
136 | (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ |
137 | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ | |
138 | (3 << TIMING_CFG1_PRETOACT_SHIFT)) | |
d892b2db | 139 | |
6d0f6bcf | 140 | #define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ |
d892b2db AV |
141 | (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \ |
142 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ | |
143 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ | |
144 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ | |
145 | (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ | |
146 | (0 << TIMING_CFG2_CPO_SHIFT)) | |
147 | ||
6d0f6bcf | 148 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
fab6f556 AV |
149 | |
150 | /* | |
151 | * Memory test | |
152 | */ | |
6d0f6bcf JCPV |
153 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
154 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
155 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
fab6f556 AV |
156 | |
157 | /* | |
158 | * The reserved memory | |
159 | */ | |
14d0a02a | 160 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
6d0f6bcf | 161 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */ |
fab6f556 | 162 | |
6d0f6bcf JCPV |
163 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
164 | #define CONFIG_SYS_RAMBOOT | |
fab6f556 | 165 | #else |
6d0f6bcf | 166 | #undef CONFIG_SYS_RAMBOOT |
fab6f556 AV |
167 | #endif |
168 | ||
9a986550 | 169 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
c8a90646 | 170 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
fab6f556 AV |
171 | |
172 | /* | |
173 | * Initial RAM Base Address Setup | |
174 | */ | |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
176 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 177 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
9a986550 JH |
178 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
179 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
fab6f556 AV |
180 | |
181 | /* | |
182 | * Local Bus Configuration & Clock Setup | |
183 | */ | |
c7190f02 KP |
184 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
185 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
9a986550 | 186 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
fab6f556 AV |
187 | |
188 | /* | |
189 | * FLASH on the Local Bus | |
190 | */ | |
6d0f6bcf | 191 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
9a986550 | 192 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ |
194 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */ | |
fab6f556 | 195 | |
9a986550 JH |
196 | /* Window base at flash base */ |
197 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 198 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
fab6f556 | 199 | |
9a986550 | 200 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
201 | | BR_PS_16 /* 16 bit port */ \ |
202 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
203 | | BR_V) /* valid */ | |
204 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
9a986550 JH |
205 | | OR_UPM_XAM \ |
206 | | OR_GPCM_CSNT \ | |
207 | | OR_GPCM_ACS_DIV2 \ | |
208 | | OR_GPCM_XACS \ | |
209 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
210 | | OR_GPCM_TRLX_SET \ |
211 | | OR_GPCM_EHTR_SET \ | |
9a986550 | 212 | | OR_GPCM_EAD) |
fab6f556 | 213 | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
215 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
fab6f556 | 216 | |
6d0f6bcf | 217 | #undef CONFIG_SYS_FLASH_CHECKSUM |
fab6f556 AV |
218 | |
219 | /* | |
220 | * NAND flash on the local bus | |
221 | */ | |
6d0f6bcf | 222 | #define CONFIG_SYS_NAND_BASE 0x60000000 |
7ad95949 AV |
223 | #define CONFIG_CMD_NAND 1 |
224 | #define CONFIG_NAND_FSL_UPM 1 | |
6d0f6bcf | 225 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
7ad95949 | 226 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
fab6f556 | 227 | |
6d0f6bcf | 228 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 JH |
229 | /* |
230 | * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB | |
231 | * ... What's correct? | |
232 | */ | |
233 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) | |
fab6f556 AV |
234 | |
235 | /* Port size 8 bit, UPMA */ | |
7d6a0982 JH |
236 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ |
237 | | BR_PS_8 \ | |
238 | | BR_MS_UPMA \ | |
239 | | BR_V) | |
240 | /* 0x60000881 */ | |
241 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD) | |
242 | /* 0xFC000001 */ | |
fab6f556 AV |
243 | |
244 | /* | |
245 | * Fujitsu MB86277 (MINT) graphics controller | |
246 | */ | |
6d0f6bcf | 247 | #define CONFIG_SYS_VIDEO_BASE 0x70000000 |
fab6f556 | 248 | |
6d0f6bcf | 249 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE |
7d6a0982 | 250 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) |
fab6f556 AV |
251 | |
252 | /* Port size 32 bit, UPMB */ | |
7d6a0982 JH |
253 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \ |
254 | | BR_PS_32 \ | |
255 | | BR_MS_UPMB \ | |
256 | | BR_V) | |
257 | /* 0x000018a1 */ | |
258 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD) | |
259 | /* 0xFC000001 */ | |
fab6f556 AV |
260 | |
261 | /* | |
262 | * Serial Port | |
263 | */ | |
264 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_NS16550 |
266 | #define CONFIG_SYS_NS16550_SERIAL | |
267 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
268 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
fab6f556 | 269 | |
6d0f6bcf | 270 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
9a986550 | 271 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
fab6f556 | 272 | |
6d0f6bcf JCPV |
273 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
274 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
fab6f556 AV |
275 | |
276 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
9a986550 | 277 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
fab6f556 | 278 | /* Use the HUSH parser */ |
6d0f6bcf | 279 | #define CONFIG_SYS_HUSH_PARSER |
fab6f556 AV |
280 | |
281 | /* Pass open firmware flat tree */ | |
282 | #define CONFIG_OF_LIBFDT 1 | |
283 | #define CONFIG_OF_BOARD_SETUP 1 | |
3a0cfdd5 | 284 | #define CONFIG_OF_STDOUT_VIA_ALIAS |
fab6f556 AV |
285 | |
286 | /* I2C */ | |
287 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
288 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
289 | #define CONFIG_FSL_I2C | |
290 | #define CONFIG_I2C_MULTI_BUS | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
292 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
9a986550 | 293 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } /* Don't probe these addrs */ |
6d0f6bcf | 294 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
9a986550 | 295 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 |
fab6f556 AV |
296 | |
297 | /* | |
298 | * General PCI | |
299 | * Addresses are mapped 1-1. | |
300 | */ | |
301 | #define CONFIG_PCI | |
fab6f556 | 302 | |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
304 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
305 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
306 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
307 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
308 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
9a986550 JH |
309 | #define CONFIG_SYS_PCI1_IO_BASE 0xE0300000 |
310 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 | |
311 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
fab6f556 AV |
312 | |
313 | #ifdef CONFIG_PCI | |
842033e6 | 314 | #define CONFIG_PCI_INDIRECT_BRIDGE |
fab6f556 | 315 | |
fab6f556 AV |
316 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
317 | ||
318 | #undef CONFIG_EEPRO100 | |
319 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 320 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
fab6f556 AV |
321 | |
322 | #endif /* CONFIG_PCI */ | |
323 | ||
fab6f556 AV |
324 | /* |
325 | * QE UEC ethernet configuration | |
326 | */ | |
327 | #define CONFIG_UEC_ETH | |
78b7a8ef | 328 | #define CONFIG_ETHPRIME "UEC0" |
fab6f556 AV |
329 | |
330 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
331 | ||
332 | #ifdef CONFIG_UEC_ETH1 | |
6d0f6bcf JCPV |
333 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ |
334 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
335 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 | |
336 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
337 | #define CONFIG_SYS_UEC1_PHY_ADDR 2 | |
9a986550 JH |
338 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID |
339 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 | |
fab6f556 AV |
340 | #endif |
341 | ||
342 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
343 | ||
344 | #ifdef CONFIG_UEC_ETH2 | |
6d0f6bcf JCPV |
345 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
346 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
347 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 | |
348 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
349 | #define CONFIG_SYS_UEC2_PHY_ADDR 4 | |
9a986550 JH |
350 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID |
351 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 | |
fab6f556 AV |
352 | #endif |
353 | ||
354 | /* | |
355 | * Environment | |
356 | */ | |
357 | ||
6d0f6bcf | 358 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 359 | #define CONFIG_ENV_IS_IN_FLASH 1 |
9a986550 | 360 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
361 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
362 | #define CONFIG_ENV_SIZE 0x20000 | |
6d0f6bcf | 363 | #else /* CONFIG_SYS_RAMBOOT */ |
9a986550 | 364 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 365 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 366 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 367 | #define CONFIG_ENV_SIZE 0x2000 |
6d0f6bcf | 368 | #endif /* CONFIG_SYS_RAMBOOT */ |
fab6f556 AV |
369 | |
370 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 371 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
fab6f556 AV |
372 | |
373 | /* | |
374 | * BOOTP options | |
375 | */ | |
376 | #define CONFIG_BOOTP_BOOTFILESIZE | |
377 | #define CONFIG_BOOTP_BOOTPATH | |
378 | #define CONFIG_BOOTP_GATEWAY | |
379 | #define CONFIG_BOOTP_HOSTNAME | |
380 | ||
381 | ||
382 | /* | |
383 | * Command line configuration. | |
384 | */ | |
385 | #include <config_cmd_default.h> | |
386 | ||
387 | #define CONFIG_CMD_PING | |
388 | #define CONFIG_CMD_I2C | |
389 | #define CONFIG_CMD_ASKENV | |
3419eb62 | 390 | #define CONFIG_CMD_DHCP |
fab6f556 AV |
391 | |
392 | #if defined(CONFIG_PCI) | |
393 | #define CONFIG_CMD_PCI | |
394 | #endif | |
395 | ||
6d0f6bcf | 396 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 397 | #undef CONFIG_CMD_SAVEENV |
fab6f556 AV |
398 | #undef CONFIG_CMD_LOADS |
399 | #endif | |
400 | ||
401 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
402 | ||
403 | /* | |
404 | * Miscellaneous configurable options | |
405 | */ | |
6d0f6bcf JCPV |
406 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
407 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
408 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
fab6f556 AV |
409 | |
410 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 411 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
fab6f556 | 412 | #else |
6d0f6bcf | 413 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
fab6f556 AV |
414 | #endif |
415 | ||
9a986550 JH |
416 | /* Print Buffer Size */ |
417 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
418 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
419 | /* Boot Argument Buffer Size */ | |
420 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
421 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
fab6f556 AV |
422 | |
423 | /* | |
424 | * For booting Linux, the board info and command line data | |
9f530d59 | 425 | * have to be in the first 256 MB of memory, since this is |
fab6f556 AV |
426 | * the maximum mapped by the Linux kernel during initialization. |
427 | */ | |
9a986550 | 428 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
fab6f556 AV |
429 | |
430 | /* | |
431 | * Core HID Setup | |
432 | */ | |
1a2e203b KP |
433 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
434 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
435 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 436 | #define CONFIG_SYS_HID2 HID2_HBE |
fab6f556 | 437 | |
fab6f556 AV |
438 | /* |
439 | * MMU Setup | |
440 | */ | |
441 | ||
31d82672 BB |
442 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
443 | ||
fab6f556 | 444 | /* DDR: cache cacheable */ |
9a986550 | 445 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 446 | | BATL_PP_RW \ |
9a986550 JH |
447 | | BATL_MEMCOHERENCE) |
448 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
449 | | BATU_BL_256M \ | |
450 | | BATU_VS \ | |
451 | | BATU_VP) | |
6d0f6bcf JCPV |
452 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
453 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
fab6f556 AV |
454 | |
455 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
9a986550 | 456 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
72cd4087 | 457 | | BATL_PP_RW \ |
9a986550 JH |
458 | | BATL_CACHEINHIBIT \ |
459 | | BATL_GUARDEDSTORAGE) | |
460 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ | |
461 | | BATU_BL_4M \ | |
462 | | BATU_VS \ | |
463 | | BATU_VP) | |
6d0f6bcf JCPV |
464 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
465 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
fab6f556 AV |
466 | |
467 | /* NAND: cache-inhibit and guarded */ | |
9a986550 | 468 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \ |
72cd4087 | 469 | | BATL_PP_RW \ |
9a986550 JH |
470 | | BATL_CACHEINHIBIT \ |
471 | | BATL_GUARDEDSTORAGE) | |
472 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \ | |
473 | | BATU_BL_64M \ | |
474 | | BATU_VS \ | |
475 | | BATU_VP) | |
6d0f6bcf JCPV |
476 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
477 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
fab6f556 AV |
478 | |
479 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
9a986550 | 480 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 481 | | BATL_PP_RW \ |
9a986550 JH |
482 | | BATL_MEMCOHERENCE) |
483 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ | |
484 | | BATU_BL_32M \ | |
485 | | BATU_VS \ | |
486 | | BATU_VP) | |
487 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 488 | | BATL_PP_RW \ |
9a986550 JH |
489 | | BATL_CACHEINHIBIT \ |
490 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 491 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U |
fab6f556 AV |
492 | |
493 | /* Stack in dcache: cacheable, no memory coherence */ | |
9a986550 | 494 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \ |
72cd4087 | 495 | | BATL_PP_RW) |
9a986550 JH |
496 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ |
497 | | BATU_BL_128K \ | |
498 | | BATU_VS \ | |
499 | | BATU_VP) | |
6d0f6bcf JCPV |
500 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
501 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
fab6f556 | 502 | |
9a986550 | 503 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \ |
72cd4087 | 504 | | BATL_PP_RW \ |
9a986550 JH |
505 | | BATL_CACHEINHIBIT \ |
506 | | BATL_GUARDEDSTORAGE) | |
507 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \ | |
508 | | BATU_BL_64M \ | |
509 | | BATU_VS \ | |
510 | | BATU_VP) | |
6d0f6bcf JCPV |
511 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
512 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
fab6f556 AV |
513 | |
514 | #ifdef CONFIG_PCI | |
515 | /* PCI MEM space: cacheable */ | |
9a986550 | 516 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ |
72cd4087 | 517 | | BATL_PP_RW \ |
9a986550 JH |
518 | | BATL_MEMCOHERENCE) |
519 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ | |
520 | | BATU_BL_256M \ | |
521 | | BATU_VS \ | |
522 | | BATU_VP) | |
6d0f6bcf JCPV |
523 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
524 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
fab6f556 | 525 | /* PCI MMIO space: cache-inhibit and guarded */ |
9a986550 | 526 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ |
72cd4087 | 527 | | BATL_PP_RW \ |
9a986550 JH |
528 | | BATL_CACHEINHIBIT \ |
529 | | BATL_GUARDEDSTORAGE) | |
530 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ | |
531 | | BATU_BL_256M \ | |
532 | | BATU_VS \ | |
533 | | BATU_VP) | |
6d0f6bcf JCPV |
534 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
535 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
fab6f556 | 536 | #else /* CONFIG_PCI */ |
6d0f6bcf JCPV |
537 | #define CONFIG_SYS_IBAT6L (0) |
538 | #define CONFIG_SYS_IBAT6U (0) | |
539 | #define CONFIG_SYS_IBAT7L (0) | |
540 | #define CONFIG_SYS_IBAT7U (0) | |
541 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
542 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
543 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
544 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
fab6f556 AV |
545 | #endif /* CONFIG_PCI */ |
546 | ||
fab6f556 AV |
547 | #if defined(CONFIG_CMD_KGDB) |
548 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
549 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
550 | #endif | |
551 | ||
552 | /* | |
553 | * Environment Configuration | |
554 | */ | |
555 | #define CONFIG_ENV_OVERWRITE | |
556 | ||
557 | #if defined(CONFIG_UEC_ETH) | |
558 | #define CONFIG_HAS_ETH0 | |
559 | #define CONFIG_HAS_ETH1 | |
560 | #define CONFIG_HAS_ETH2 | |
561 | #define CONFIG_HAS_ETH3 | |
fab6f556 AV |
562 | #endif |
563 | ||
564 | #define CONFIG_BAUDRATE 115200 | |
565 | ||
566 | #define CONFIG_LOADADDR a00000 | |
567 | #define CONFIG_HOSTNAME mpc8360erdk | |
b3f44c21 | 568 | #define CONFIG_BOOTFILE "uImage" |
fab6f556 | 569 | |
8b3637c6 | 570 | #define CONFIG_ROOTPATH "/nfsroot/" |
fab6f556 AV |
571 | |
572 | #define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ | |
573 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
574 | ||
575 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
9a986550 JH |
576 | "netdev=eth0\0" \ |
577 | "consoledev=ttyS0\0" \ | |
578 | "loadaddr=a00000\0" \ | |
579 | "fdtaddr=900000\0" \ | |
580 | "fdtfile=mpc836x_rdk.dtb\0" \ | |
581 | "fsfile=fs\0" \ | |
582 | "ubootfile=u-boot.bin\0" \ | |
583 | "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\ | |
584 | "-(rootfs)\0" \ | |
585 | "setbootargs=setenv bootargs console=$consoledev,$baudrate " \ | |
586 | "$mtdparts panic=1\0" \ | |
587 | "adddhcpargs=setenv bootargs $bootargs ip=on\0" \ | |
588 | "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \ | |
589 | "$gatewayip:$netmask:$hostname:$netdev:off " \ | |
590 | "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \ | |
591 | "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \ | |
592 | "rootfstype=jffs2 rw\0" \ | |
593 | "tftp_get_uboot=tftp 100000 $ubootfile\0" \ | |
594 | "tftp_get_kernel=tftp $loadaddr $bootfile\0" \ | |
595 | "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \ | |
596 | "tftp_get_fs=tftp c00000 $fsfile\0" \ | |
597 | "nand_erase_kernel=nand erase 0 400000\0" \ | |
598 | "nand_erase_dtb=nand erase 400000 20000\0" \ | |
599 | "nand_erase_fs=nand erase 420000 3be0000\0" \ | |
600 | "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \ | |
601 | "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \ | |
602 | "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \ | |
603 | "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \ | |
604 | "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \ | |
605 | "nor_reflash=protect off ff800000 ff87ffff ; " \ | |
606 | "erase ff800000 ff87ffff ; " \ | |
607 | "cp.b 100000 ff800000 $filesize\0" \ | |
608 | "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \ | |
609 | "nand_write_kernel\0" \ | |
610 | "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\ | |
611 | "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \ | |
612 | "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \ | |
613 | "nand_reflash_fs\0" \ | |
614 | "boot_m=bootm $loadaddr - $fdtaddr\0" \ | |
615 | "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\ | |
616 | "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\ | |
617 | "boot_m\0" \ | |
618 | "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\ | |
619 | "boot_m\0" \ | |
620 | "" | |
fab6f556 AV |
621 | |
622 | #define CONFIG_BOOTCOMMAND "run dhcpboot" | |
623 | ||
624 | #endif /* __CONFIG_H */ |