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Commit | Line | Data |
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19580e66 DL |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
19580e66 DL |
6 | */ |
7 | ||
8 | #ifndef __CONFIG_H | |
9 | #define __CONFIG_H | |
10 | ||
fdfaa29e KP |
11 | #define CONFIG_DISPLAY_BOARDINFO |
12 | ||
19580e66 DL |
13 | /* |
14 | * High Level Configuration Options | |
15 | */ | |
16 | #define CONFIG_E300 1 /* E300 family */ | |
2c7920af | 17 | #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ |
19580e66 DL |
18 | #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ |
19 | ||
2ae18241 WD |
20 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
21 | ||
19580e66 DL |
22 | /* |
23 | * System Clock Setup | |
24 | */ | |
25 | #ifdef CONFIG_PCISLAVE | |
26 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
27 | #else | |
28 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
29 | #endif | |
30 | ||
31 | #ifndef CONFIG_SYS_CLK_FREQ | |
32 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
33 | #endif | |
34 | ||
35 | /* | |
36 | * Hardware Reset Configuration Word | |
37 | * if CLKIN is 66MHz, then | |
38 | * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz | |
39 | */ | |
6d0f6bcf | 40 | #define CONFIG_SYS_HRCW_LOW (\ |
19580e66 DL |
41 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
42 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
43 | HRCWL_SVCOD_DIV_2 |\ | |
44 | HRCWL_CSB_TO_CLKIN_6X1 |\ | |
45 | HRCWL_CORE_TO_CSB_1_5X1) | |
46 | ||
47 | #ifdef CONFIG_PCISLAVE | |
6d0f6bcf | 48 | #define CONFIG_SYS_HRCW_HIGH (\ |
19580e66 DL |
49 | HRCWH_PCI_AGENT |\ |
50 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
51 | HRCWH_CORE_ENABLE |\ | |
52 | HRCWH_FROM_0XFFF00100 |\ | |
53 | HRCWH_BOOTSEQ_DISABLE |\ | |
54 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
55 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
56 | HRCWH_RL_EXT_LEGACY |\ | |
57 | HRCWH_TSEC1M_IN_RGMII |\ | |
58 | HRCWH_TSEC2M_IN_RGMII |\ | |
59 | HRCWH_BIG_ENDIAN |\ | |
60 | HRCWH_LDP_CLEAR) | |
61 | #else | |
6d0f6bcf | 62 | #define CONFIG_SYS_HRCW_HIGH (\ |
19580e66 DL |
63 | HRCWH_PCI_HOST |\ |
64 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
65 | HRCWH_CORE_ENABLE |\ | |
66 | HRCWH_FROM_0X00000100 |\ | |
67 | HRCWH_BOOTSEQ_DISABLE |\ | |
68 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
69 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
70 | HRCWH_RL_EXT_LEGACY |\ | |
71 | HRCWH_TSEC1M_IN_RGMII |\ | |
72 | HRCWH_TSEC2M_IN_RGMII |\ | |
73 | HRCWH_BIG_ENDIAN |\ | |
74 | HRCWH_LDP_CLEAR) | |
75 | #endif | |
76 | ||
bd4458cb | 77 | /* Arbiter Configuration Register */ |
6d0f6bcf | 78 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ |
8d85808f | 79 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ |
bd4458cb DL |
80 | |
81 | /* System Priority Control Register */ | |
8d85808f | 82 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ |
bd4458cb | 83 | |
19580e66 | 84 | /* |
bd4458cb | 85 | * IP blocks clock configuration |
19580e66 | 86 | */ |
6d0f6bcf JCPV |
87 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ |
88 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ | |
8d85808f | 89 | #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ |
19580e66 DL |
90 | |
91 | /* | |
92 | * System IO Config | |
93 | */ | |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_SICRH 0x00000000 |
95 | #define CONFIG_SYS_SICRL 0x00000000 | |
19580e66 DL |
96 | |
97 | /* | |
98 | * Output Buffer Impedance | |
99 | */ | |
6d0f6bcf | 100 | #define CONFIG_SYS_OBIR 0x31100000 |
19580e66 DL |
101 | |
102 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
103 | #define CONFIG_BOARD_EARLY_INIT_R | |
c78c6783 | 104 | #define CONFIG_HWCONFIG |
19580e66 DL |
105 | |
106 | /* | |
107 | * IMMR new address | |
108 | */ | |
6d0f6bcf | 109 | #define CONFIG_SYS_IMMR 0xE0000000 |
19580e66 DL |
110 | |
111 | /* | |
112 | * DDR Setup | |
113 | */ | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
115 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
116 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
117 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
118 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
2fef4020 JH |
119 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ |
120 | | DDRCDR_ODT \ | |
121 | | DDRCDR_Q_DRN) | |
122 | /* 0x80080001 */ /* ODT 150ohm on SoC */ | |
19580e66 DL |
123 | |
124 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
125 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
126 | ||
127 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
128 | #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
129 | ||
130 | #if defined(CONFIG_SPD_EEPROM) | |
131 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ | |
132 | #else | |
133 | /* | |
134 | * Manually set up DDR parameters | |
7e74d63d | 135 | * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM |
19580e66 DL |
136 | * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 |
137 | */ | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_DDR_SIZE 512 /* MB */ |
139 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f | |
8d85808f | 140 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
2fef4020 JH |
141 | | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ |
142 | | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ | |
143 | | CSCONFIG_ROW_BIT_14 \ | |
144 | | CSCONFIG_COL_BIT_10) | |
145 | /* 0x80010202 */ | |
6d0f6bcf | 146 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
8d85808f JH |
147 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
148 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
149 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
150 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
151 | | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
152 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
153 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
154 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
19580e66 | 155 | /* 0x00620802 */ |
8d85808f JH |
156 | #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ |
157 | | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
158 | | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
159 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
160 | | (13 << TIMING_CFG1_REFREC_SHIFT) \ | |
161 | | (3 << TIMING_CFG1_WRREC_SHIFT) \ | |
162 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
163 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
19580e66 | 164 | /* 0x3935d322 */ |
8d85808f JH |
165 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
166 | | (6 << TIMING_CFG2_CPO_SHIFT) \ | |
167 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
168 | | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
169 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
170 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
171 | | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
7e74d63d | 172 | /* 0x131088c8 */ |
8d85808f JH |
173 | #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ |
174 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
19580e66 | 175 | /* 0x03E00100 */ |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
177 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ | |
8d85808f JH |
178 | #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ |
179 | | (0x1432 << SDRAM_MODE_SD_SHIFT)) | |
7e74d63d | 180 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
8d85808f | 181 | #define CONFIG_SYS_DDR_MODE2 0x00000000 |
19580e66 DL |
182 | #endif |
183 | ||
184 | /* | |
185 | * Memory test | |
186 | */ | |
6d0f6bcf JCPV |
187 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
188 | #define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ | |
189 | #define CONFIG_SYS_MEMTEST_END 0x00140000 | |
19580e66 DL |
190 | |
191 | /* | |
192 | * The reserved memory | |
193 | */ | |
14d0a02a | 194 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
19580e66 | 195 | |
6d0f6bcf JCPV |
196 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
197 | #define CONFIG_SYS_RAMBOOT | |
19580e66 | 198 | #else |
6d0f6bcf | 199 | #undef CONFIG_SYS_RAMBOOT |
19580e66 DL |
200 | #endif |
201 | ||
6d0f6bcf | 202 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
8d85808f JH |
203 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
204 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
19580e66 DL |
205 | |
206 | /* | |
207 | * Initial RAM Base Address Setup | |
208 | */ | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
210 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
553f0982 | 211 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ |
8d85808f JH |
212 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
213 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
19580e66 DL |
214 | |
215 | /* | |
216 | * Local Bus Configuration & Clock Setup | |
217 | */ | |
c7190f02 KP |
218 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
219 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 | |
6d0f6bcf | 220 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
0914f483 | 221 | #define CONFIG_FSL_ELBC 1 |
19580e66 DL |
222 | |
223 | /* | |
224 | * FLASH on the Local Bus | |
225 | */ | |
8d85808f | 226 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 227 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
8d85808f JH |
228 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
229 | #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ | |
230 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
19580e66 | 231 | |
8d85808f JH |
232 | /* Window base at flash base */ |
233 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 234 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
19580e66 | 235 | |
8d85808f | 236 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
237 | | BR_PS_16 /* 16 bit port */ \ |
238 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
239 | | BR_V) /* valid */ | |
240 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
ded08317 DL |
241 | | OR_UPM_XAM \ |
242 | | OR_GPCM_CSNT \ | |
f9023afb | 243 | | OR_GPCM_ACS_DIV2 \ |
ded08317 DL |
244 | | OR_GPCM_XACS \ |
245 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
246 | | OR_GPCM_TRLX_SET \ |
247 | | OR_GPCM_EHTR_SET \ | |
8d85808f | 248 | | OR_GPCM_EAD) |
ded08317 | 249 | /* 0xFE000FF7 */ |
19580e66 | 250 | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
252 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
19580e66 | 253 | |
6d0f6bcf JCPV |
254 | #undef CONFIG_SYS_FLASH_CHECKSUM |
255 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
256 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
19580e66 DL |
257 | |
258 | /* | |
259 | * BCSR on the Local Bus | |
260 | */ | |
6d0f6bcf | 261 | #define CONFIG_SYS_BCSR 0xF8000000 |
8d85808f JH |
262 | /* Access window base at BCSR base */ |
263 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
7d6a0982 JH |
264 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
265 | ||
266 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
267 | | BR_PS_8 \ | |
268 | | BR_MS_GPCM \ | |
269 | | BR_V) | |
270 | /* 0xF8000801 */ | |
271 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
272 | | OR_GPCM_XAM \ | |
273 | | OR_GPCM_CSNT \ | |
274 | | OR_GPCM_XACS \ | |
275 | | OR_GPCM_SCY_15 \ | |
276 | | OR_GPCM_TRLX_SET \ | |
277 | | OR_GPCM_EHTR_SET \ | |
278 | | OR_GPCM_EAD) | |
279 | /* 0xFFFFE9F7 */ | |
19580e66 DL |
280 | |
281 | /* | |
282 | * NAND Flash on the Local Bus | |
283 | */ | |
b3379f3f | 284 | #define CONFIG_CMD_NAND 1 |
b3379f3f | 285 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
8d85808f | 286 | #define CONFIG_NAND_FSL_ELBC 1 |
b3379f3f | 287 | |
7d6a0982 | 288 | #define CONFIG_SYS_NAND_BASE 0xE0600000 |
8d85808f | 289 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \ |
7d6a0982 | 290 | | BR_DECC_CHK_GEN /* Use HW ECC */ \ |
8d85808f | 291 | | BR_PS_8 /* 8 bit port */ \ |
19580e66 | 292 | | BR_MS_FCM /* MSEL = FCM */ \ |
7d6a0982 JH |
293 | | BR_V) /* valid */ |
294 | #define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \ | |
b3379f3f | 295 | | OR_FCM_BCTLD \ |
19580e66 DL |
296 | | OR_FCM_CST \ |
297 | | OR_FCM_CHT \ | |
298 | | OR_FCM_SCY_1 \ | |
b3379f3f | 299 | | OR_FCM_RST \ |
19580e66 | 300 | | OR_FCM_TRLX \ |
8d85808f | 301 | | OR_FCM_EHTR) |
b3379f3f | 302 | /* 0xFFFF919E */ |
19580e66 | 303 | |
6d0f6bcf | 304 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE |
7d6a0982 | 305 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
19580e66 DL |
306 | |
307 | /* | |
308 | * Serial Port | |
309 | */ | |
310 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_NS16550_SERIAL |
312 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
313 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
19580e66 | 314 | |
6d0f6bcf | 315 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
8d85808f | 316 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
19580e66 | 317 | |
6d0f6bcf JCPV |
318 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
319 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
19580e66 | 320 | |
19580e66 | 321 | /* I2C */ |
00f792e0 HS |
322 | #define CONFIG_SYS_I2C |
323 | #define CONFIG_SYS_I2C_FSL | |
324 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
325 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
326 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
327 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
19580e66 DL |
328 | |
329 | /* | |
330 | * Config on-board RTC | |
331 | */ | |
332 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
6d0f6bcf | 333 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
19580e66 DL |
334 | |
335 | /* | |
336 | * General PCI | |
337 | * Addresses are mapped 1-1. | |
338 | */ | |
8d85808f JH |
339 | #define CONFIG_SYS_PCI_MEM_BASE 0x80000000 |
340 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
341 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
6d0f6bcf JCPV |
342 | #define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 |
343 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
344 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
345 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
346 | #define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 | |
347 | #define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ | |
19580e66 | 348 | |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE |
350 | #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 | |
351 | #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 | |
19580e66 | 352 | |
8b34557c AV |
353 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 |
354 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 | |
355 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 | |
356 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 | |
357 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 | |
358 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
359 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
360 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 | |
361 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
362 | ||
363 | #define CONFIG_SYS_PCIE2_BASE 0xC0000000 | |
364 | #define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 | |
365 | #define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 | |
366 | #define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 | |
367 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 | |
368 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 | |
369 | #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 | |
370 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 | |
371 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 | |
372 | ||
19580e66 | 373 | #ifdef CONFIG_PCI |
842033e6 | 374 | #define CONFIG_PCI_INDIRECT_BRIDGE |
00f7bbae AV |
375 | #ifndef __ASSEMBLY__ |
376 | extern int board_pci_host_broken(void); | |
377 | #endif | |
be9b56df | 378 | #define CONFIG_PCIE |
19580e66 DL |
379 | #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ |
380 | ||
3bf1be3c | 381 | #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ |
6c3c5750 NB |
382 | #define CONFIG_USB_STORAGE |
383 | #define CONFIG_USB_EHCI | |
384 | #define CONFIG_USB_EHCI_FSL | |
385 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
3bf1be3c | 386 | |
19580e66 DL |
387 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
388 | ||
389 | #undef CONFIG_EEPRO100 | |
390 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 391 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
19580e66 DL |
392 | #endif /* CONFIG_PCI */ |
393 | ||
19580e66 DL |
394 | /* |
395 | * TSEC | |
396 | */ | |
397 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
6d0f6bcf | 398 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
8d85808f | 399 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 400 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
8d85808f | 401 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
19580e66 DL |
402 | |
403 | /* | |
404 | * TSEC ethernet configuration | |
405 | */ | |
406 | #define CONFIG_MII 1 /* MII PHY management */ | |
407 | #define CONFIG_TSEC1 1 | |
408 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
409 | #define CONFIG_TSEC2 1 | |
410 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
411 | #define TSEC1_PHY_ADDR 2 | |
412 | #define TSEC2_PHY_ADDR 3 | |
1da83a63 AV |
413 | #define TSEC1_PHY_ADDR_SGMII 8 |
414 | #define TSEC2_PHY_ADDR_SGMII 4 | |
19580e66 DL |
415 | #define TSEC1_PHYIDX 0 |
416 | #define TSEC2_PHYIDX 0 | |
417 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
418 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
419 | ||
420 | /* Options are: TSEC[0-1] */ | |
421 | #define CONFIG_ETHPRIME "eTSEC1" | |
422 | ||
6f8c85e8 DL |
423 | /* SERDES */ |
424 | #define CONFIG_FSL_SERDES | |
425 | #define CONFIG_FSL_SERDES1 0xe3000 | |
426 | #define CONFIG_FSL_SERDES2 0xe3100 | |
427 | ||
2eeb3e4f DL |
428 | /* |
429 | * SATA | |
430 | */ | |
431 | #define CONFIG_LIBATA | |
432 | #define CONFIG_FSL_SATA | |
433 | ||
6d0f6bcf | 434 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
2eeb3e4f | 435 | #define CONFIG_SATA1 |
6d0f6bcf | 436 | #define CONFIG_SYS_SATA1_OFFSET 0x18000 |
8d85808f JH |
437 | #define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) |
438 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
2eeb3e4f | 439 | #define CONFIG_SATA2 |
6d0f6bcf | 440 | #define CONFIG_SYS_SATA2_OFFSET 0x19000 |
8d85808f JH |
441 | #define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) |
442 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
2eeb3e4f DL |
443 | |
444 | #ifdef CONFIG_FSL_SATA | |
445 | #define CONFIG_LBA48 | |
446 | #define CONFIG_CMD_SATA | |
447 | #define CONFIG_DOS_PARTITION | |
2eeb3e4f DL |
448 | #endif |
449 | ||
19580e66 DL |
450 | /* |
451 | * Environment | |
452 | */ | |
6d0f6bcf | 453 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 454 | #define CONFIG_ENV_IS_IN_FLASH 1 |
8d85808f JH |
455 | #define CONFIG_ENV_ADDR \ |
456 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
457 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
458 | #define CONFIG_ENV_SIZE 0x2000 | |
19580e66 | 459 | #else |
8d85808f | 460 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 461 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 462 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 463 | #define CONFIG_ENV_SIZE 0x2000 |
19580e66 DL |
464 | #endif |
465 | ||
466 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 467 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
19580e66 DL |
468 | |
469 | /* | |
470 | * BOOTP options | |
471 | */ | |
472 | #define CONFIG_BOOTP_BOOTFILESIZE | |
473 | #define CONFIG_BOOTP_BOOTPATH | |
474 | #define CONFIG_BOOTP_GATEWAY | |
475 | #define CONFIG_BOOTP_HOSTNAME | |
476 | ||
19580e66 DL |
477 | /* |
478 | * Command line configuration. | |
479 | */ | |
19580e66 DL |
480 | #define CONFIG_CMD_DATE |
481 | ||
482 | #if defined(CONFIG_PCI) | |
483 | #define CONFIG_CMD_PCI | |
484 | #endif | |
485 | ||
19580e66 | 486 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
a059e90e | 487 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
19580e66 DL |
488 | |
489 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
490 | ||
e1ac387f AF |
491 | #define CONFIG_MMC 1 |
492 | ||
493 | #ifdef CONFIG_MMC | |
494 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 495 | #define CONFIG_FSL_ESDHC_PIN_MUX |
e1ac387f | 496 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR |
e1ac387f | 497 | #define CONFIG_GENERIC_MMC |
e1ac387f AF |
498 | #define CONFIG_DOS_PARTITION |
499 | #endif | |
500 | ||
19580e66 DL |
501 | /* |
502 | * Miscellaneous configurable options | |
503 | */ | |
6d0f6bcf JCPV |
504 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
505 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
19580e66 DL |
506 | |
507 | #if defined(CONFIG_CMD_KGDB) | |
6d0f6bcf | 508 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
19580e66 | 509 | #else |
6d0f6bcf | 510 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
19580e66 DL |
511 | #endif |
512 | ||
8d85808f JH |
513 | /* Print Buffer Size */ |
514 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
515 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
516 | /* Boot Argument Buffer Size */ | |
517 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
19580e66 DL |
518 | |
519 | /* | |
520 | * For booting Linux, the board info and command line data | |
9f530d59 | 521 | * have to be in the first 256 MB of memory, since this is |
19580e66 DL |
522 | * the maximum mapped by the Linux kernel during initialization. |
523 | */ | |
8d85808f | 524 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ |
19580e66 DL |
525 | |
526 | /* | |
527 | * Core HID Setup | |
528 | */ | |
1a2e203b KP |
529 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
530 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
531 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 532 | #define CONFIG_SYS_HID2 HID2_HBE |
19580e66 | 533 | |
19580e66 DL |
534 | /* |
535 | * MMU Setup | |
536 | */ | |
31d82672 | 537 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
19580e66 DL |
538 | |
539 | /* DDR: cache cacheable */ | |
6d0f6bcf JCPV |
540 | #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE |
541 | #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) | |
19580e66 | 542 | |
8d85808f | 543 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ |
72cd4087 | 544 | | BATL_PP_RW \ |
8d85808f JH |
545 | | BATL_MEMCOHERENCE) |
546 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ | |
547 | | BATU_BL_256M \ | |
548 | | BATU_VS \ | |
549 | | BATU_VP) | |
6d0f6bcf JCPV |
550 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
551 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
19580e66 | 552 | |
8d85808f | 553 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ |
72cd4087 | 554 | | BATL_PP_RW \ |
8d85808f JH |
555 | | BATL_MEMCOHERENCE) |
556 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ | |
557 | | BATU_BL_256M \ | |
558 | | BATU_VS \ | |
559 | | BATU_VP) | |
6d0f6bcf JCPV |
560 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
561 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
19580e66 DL |
562 | |
563 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
8d85808f | 564 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ |
72cd4087 | 565 | | BATL_PP_RW \ |
8d85808f JH |
566 | | BATL_CACHEINHIBIT \ |
567 | | BATL_GUARDEDSTORAGE) | |
568 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ | |
569 | | BATU_BL_8M \ | |
570 | | BATU_VS \ | |
571 | | BATU_VP) | |
6d0f6bcf JCPV |
572 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L |
573 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
19580e66 DL |
574 | |
575 | /* BCSR: cache-inhibit and guarded */ | |
8d85808f | 576 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \ |
72cd4087 | 577 | | BATL_PP_RW \ |
8d85808f JH |
578 | | BATL_CACHEINHIBIT \ |
579 | | BATL_GUARDEDSTORAGE) | |
580 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \ | |
581 | | BATU_BL_128K \ | |
582 | | BATU_VS \ | |
583 | | BATU_VP) | |
6d0f6bcf JCPV |
584 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L |
585 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
19580e66 DL |
586 | |
587 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
8d85808f | 588 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 589 | | BATL_PP_RW \ |
8d85808f JH |
590 | | BATL_MEMCOHERENCE) |
591 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ | |
592 | | BATU_BL_32M \ | |
593 | | BATU_VS \ | |
594 | | BATU_VP) | |
595 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 596 | | BATL_PP_RW \ |
8d85808f JH |
597 | | BATL_CACHEINHIBIT \ |
598 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 599 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U |
19580e66 DL |
600 | |
601 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 602 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
8d85808f JH |
603 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ |
604 | | BATU_BL_128K \ | |
605 | | BATU_VS \ | |
606 | | BATU_VP) | |
6d0f6bcf JCPV |
607 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
608 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
19580e66 DL |
609 | |
610 | #ifdef CONFIG_PCI | |
611 | /* PCI MEM space: cacheable */ | |
8d85808f | 612 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ |
72cd4087 | 613 | | BATL_PP_RW \ |
8d85808f JH |
614 | | BATL_MEMCOHERENCE) |
615 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ | |
616 | | BATU_BL_256M \ | |
617 | | BATU_VS \ | |
618 | | BATU_VP) | |
6d0f6bcf JCPV |
619 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
620 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
19580e66 | 621 | /* PCI MMIO space: cache-inhibit and guarded */ |
8d85808f | 622 | #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ |
72cd4087 | 623 | | BATL_PP_RW \ |
8d85808f JH |
624 | | BATL_CACHEINHIBIT \ |
625 | | BATL_GUARDEDSTORAGE) | |
626 | #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ | |
627 | | BATU_BL_256M \ | |
628 | | BATU_VS \ | |
629 | | BATU_VP) | |
6d0f6bcf JCPV |
630 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L |
631 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
19580e66 | 632 | #else |
6d0f6bcf JCPV |
633 | #define CONFIG_SYS_IBAT6L (0) |
634 | #define CONFIG_SYS_IBAT6U (0) | |
635 | #define CONFIG_SYS_IBAT7L (0) | |
636 | #define CONFIG_SYS_IBAT7U (0) | |
637 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
638 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
639 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
640 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
19580e66 DL |
641 | #endif |
642 | ||
19580e66 DL |
643 | #if defined(CONFIG_CMD_KGDB) |
644 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
19580e66 DL |
645 | #endif |
646 | ||
647 | /* | |
648 | * Environment Configuration | |
649 | */ | |
650 | ||
651 | #define CONFIG_ENV_OVERWRITE | |
652 | ||
653 | #if defined(CONFIG_TSEC_ENET) | |
654 | #define CONFIG_HAS_ETH0 | |
19580e66 | 655 | #define CONFIG_HAS_ETH1 |
19580e66 DL |
656 | #endif |
657 | ||
658 | #define CONFIG_BAUDRATE 115200 | |
659 | ||
79f516bc | 660 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
19580e66 | 661 | |
19580e66 DL |
662 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
663 | ||
664 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8d85808f JH |
665 | "netdev=eth0\0" \ |
666 | "consoledev=ttyS0\0" \ | |
667 | "ramdiskaddr=1000000\0" \ | |
668 | "ramdiskfile=ramfs.83xx\0" \ | |
669 | "fdtaddr=780000\0" \ | |
670 | "fdtfile=mpc8379_mds.dtb\0" \ | |
671 | "" | |
19580e66 DL |
672 | |
673 | #define CONFIG_NFSBOOTCOMMAND \ | |
8d85808f JH |
674 | "setenv bootargs root=/dev/nfs rw " \ |
675 | "nfsroot=$serverip:$rootpath " \ | |
676 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
677 | "$netdev:off " \ | |
678 | "console=$consoledev,$baudrate $othbootargs;" \ | |
679 | "tftp $loadaddr $bootfile;" \ | |
680 | "tftp $fdtaddr $fdtfile;" \ | |
681 | "bootm $loadaddr - $fdtaddr" | |
19580e66 DL |
682 | |
683 | #define CONFIG_RAMBOOTCOMMAND \ | |
8d85808f JH |
684 | "setenv bootargs root=/dev/ram rw " \ |
685 | "console=$consoledev,$baudrate $othbootargs;" \ | |
686 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
687 | "tftp $loadaddr $bootfile;" \ | |
688 | "tftp $fdtaddr $fdtfile;" \ | |
689 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
19580e66 | 690 | |
19580e66 DL |
691 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
692 | ||
693 | #endif /* __CONFIG_H */ |