]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/MPC8536DS.h
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / include / configs / MPC8536DS.h
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1/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8536ds board configuration file
25 *
26 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/* High Level Configuration Options */
31#define CONFIG_BOOKE 1 /* BOOKE */
32#define CONFIG_E500 1 /* BOOKE e500 family */
33#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
34#define CONFIG_MPC8536 1
35#define CONFIG_MPC8536DS 1
36
37#define CONFIG_PCI 1 /* Enable PCI/PCIE */
38#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
39#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
40#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
41#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
42#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
43#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
44
45#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
46
47#define CONFIG_TSEC_ENET /* tsec ethernet support */
48#define CONFIG_ENV_OVERWRITE
49
50/*
51 * When initializing flash, if we cannot find the manufacturer ID,
52 * assume this is the AMD flash associated with the CDS board.
53 * This allows booting from a promjet.
54 */
55#define CONFIG_ASSUME_AMD_FLASH
56
57#ifndef __ASSEMBLY__
58extern unsigned long get_board_sys_clk(unsigned long dummy);
59extern unsigned long get_board_ddr_clk(unsigned long dummy);
60#endif
61#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
c0391111 62#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
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63#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
64#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq
65 from ICS307 instead of switches */
66
67/*
68 * These can be toggled for performance analysis, otherwise use default.
69 */
70#define CONFIG_L2_CACHE /* toggle L2 cache */
71#define CONFIG_BTB /* toggle branch predition */
72#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
73
74#define CONFIG_ENABLE_36BIT_PHYS 1
75
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76#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
77#define CONFIG_SYS_MEMTEST_END 0x7fffffff
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78#define CONFIG_PANIC_HANG /* do not reset board on panic */
79
80/*
81 * Base addresses -- Note these are effective addresses where the
82 * actual resources get mapped (not physical addresses)
83 */
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84#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
85#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
86#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
87#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
9490a7f1 88
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89#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
90#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
91#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
92#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
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93
94/* DDR Setup */
95#define CONFIG_FSL_DDR2
96#undef CONFIG_FSL_DDR_INTERACTIVE
97#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
98#define CONFIG_DDR_SPD
99#undef CONFIG_DDR_DLL
100
101#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
102#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
103
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104#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
105#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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106
107#define CONFIG_NUM_DDR_CONTROLLERS 1
108#define CONFIG_DIMM_SLOTS_PER_CTLR 1
109#define CONFIG_CHIP_SELECTS_PER_CTRL 2
110
111/* I2C addresses of SPD EEPROMs */
112#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
6d0f6bcf 113#define CONFIG_SYS_SPD_BUS_NUM 1
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114
115/* These are used when DDR doesn't use SPD. */
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116#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
117#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
118#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
119#define CONFIG_SYS_DDR_TIMING_3 0x00000000
120#define CONFIG_SYS_DDR_TIMING_0 0x00260802
121#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
122#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
123#define CONFIG_SYS_DDR_MODE_1 0x00480432
124#define CONFIG_SYS_DDR_MODE_2 0x00000000
125#define CONFIG_SYS_DDR_INTERVAL 0x06180100
126#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
127#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
128#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
129#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
130#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
131#define CONFIG_SYS_DDR_CONTROL2 0x04400010
132
133#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
134#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
135#define CONFIG_SYS_DDR_SBE 0x00010000
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136
137/* FIXME: Not used in fixed_sdram function */
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138#define CONFIG_SYS_DDR_MODE 0x00000022
139#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
140#define CONFIG_SYS_DDR_CS2_BNDS 0x00000FFF /* Not done */
141#define CONFIG_SYS_DDR_CS3_BNDS 0x00000FFF /* Not done */
142#define CONFIG_SYS_DDR_CS4_BNDS 0x00000FFF /* Not done */
143#define CONFIG_SYS_DDR_CS5_BNDS 0x00000FFF /* Not done */
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144
145/* Make sure required options are set */
146#ifndef CONFIG_SPD_EEPROM
147#error ("CONFIG_SPD_EEPROM is required")
148#endif
149
150#undef CONFIG_CLOCKS_IN_MHZ
151
152
153/*
154 * Memory map -- xxx -this is wrong, needs updating
155 *
156 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
157 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
158 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
159 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
160 *
161 * Localbus cacheable (TBD)
162 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
163 *
164 * Localbus non-cacheable
165 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
166 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
167 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
168 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
169 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
170 */
171
172/*
173 * Local Bus Definitions
174 */
6d0f6bcf 175#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
9490a7f1 176
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177#define CONFIG_SYS_BR0_PRELIM 0xe8001001
178#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
9490a7f1 179
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180#define CONFIG_SYS_BR1_PRELIM 0xe0001001
181#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
9490a7f1 182
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183#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
184#define CONFIG_SYS_FLASH_QUIET_TEST
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185#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
186
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187#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
188#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
189#undef CONFIG_SYS_FLASH_CHECKSUM
190#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
191#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
9490a7f1 192
6d0f6bcf 193#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
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194
195#define CONFIG_FLASH_CFI_DRIVER
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196#define CONFIG_SYS_FLASH_CFI
197#define CONFIG_SYS_FLASH_EMPTY_INFO
198#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
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199
200#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
201
202#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
203#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
204
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205#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */
206#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
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207
208#define PIXIS_ID 0x0 /* Board ID at offset 0 */
209#define PIXIS_VER 0x1 /* Board version at offset 1 */
210#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
211#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
212#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
213#define PIXIS_PWR 0x5 /* PIXIS Power status register */
214#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
215#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
216#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
217#define PIXIS_VCTL 0x10 /* VELA Control Register */
218#define PIXIS_VSTAT 0x11 /* VELA Status Register */
219#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
220#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
221#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
222#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
223#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
224#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
225#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
226#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
227#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
228#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
229#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
230#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
231#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
232#define PIXIS_VWATCH 0x24 /* Watchdog Register */
233#define PIXIS_LED 0x25 /* LED Register */
234
235/* old pixis referenced names */
236#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
237#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
6d0f6bcf 238#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
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239
240/* define to use L1 as initial stack */
241#define CONFIG_L1_INIT_RAM
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242#define CONFIG_SYS_INIT_RAM_LOCK 1
243#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
244#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
9490a7f1 245
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246#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
247#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
248#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
9490a7f1 249
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250#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
251#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
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252
253/* Serial Port - controlled on board with jumper J8
254 * open - index 2
255 * shorted - index 1
256 */
257#define CONFIG_CONS_INDEX 1
258#undef CONFIG_SERIAL_SOFTWARE_FIFO
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259#define CONFIG_SYS_NS16550
260#define CONFIG_SYS_NS16550_SERIAL
261#define CONFIG_SYS_NS16550_REG_SIZE 1
262#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
9490a7f1 263
6d0f6bcf 264#define CONFIG_SYS_BAUDRATE_TABLE \
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265 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
266
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267#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
268#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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269
270/* Use the HUSH parser */
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271#define CONFIG_SYS_HUSH_PARSER
272#ifdef CONFIG_SYS_HUSH_PARSER
273#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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274#endif
275
276/*
277 * Pass open firmware flat tree
278 */
279#define CONFIG_OF_LIBFDT 1
280#define CONFIG_OF_BOARD_SETUP 1
281#define CONFIG_OF_STDOUT_VIA_ALIAS 1
282
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283#define CONFIG_SYS_64BIT_STRTOUL 1
284#define CONFIG_SYS_64BIT_VSPRINTF 1
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285
286
287/*
288 * I2C
289 */
290#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
291#define CONFIG_HARD_I2C /* I2C with hardware support */
292#undef CONFIG_SOFT_I2C /* I2C bit-banged */
293#define CONFIG_I2C_MULTI_BUS
294#define CONFIG_I2C_CMD_TREE
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295#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
296#define CONFIG_SYS_I2C_SLAVE 0x7F
297#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */
298#define CONFIG_SYS_I2C_OFFSET 0x3000
299#define CONFIG_SYS_I2C2_OFFSET 0x3100
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300
301/*
302 * I2C2 EEPROM
303 */
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304#define CONFIG_ID_EEPROM
305#ifdef CONFIG_ID_EEPROM
6d0f6bcf 306#define CONFIG_SYS_I2C_EEPROM_NXID
9490a7f1 307#endif
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308#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
309#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
310#define CONFIG_SYS_EEPROM_BUS_NUM 1
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311
312/*
313 * General PCI
314 * Memory space is mapped 1-1, but I/O space must start from 0.
315 */
316
317/* PCI view of System Memory */
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318#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
319#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
320#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
9490a7f1 321
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322#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
323#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
324#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
325#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
326#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
327#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
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328
329/* controller 1, Slot 1, tgtid 1, Base address a000 */
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330#define CONFIG_SYS_PCIE1_MEM_BASE 0x90000000
331#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
332#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
333#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
334#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
335#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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336
337/* controller 2, Slot 2, tgtid 2, Base address 9000 */
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338#define CONFIG_SYS_PCIE2_MEM_BASE 0x98000000
339#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
340#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
341#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
342#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
343#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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344
345/* controller 3, direct to uli, tgtid 3, Base address 8000 */
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346#define CONFIG_SYS_PCIE3_MEM_BASE 0xa0000000
347#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE
348#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
349#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000
350#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
351#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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352
353#if defined(CONFIG_PCI)
354
355#define CONFIG_NET_MULTI
356#define CONFIG_PCI_PNP /* do pci plug-and-play */
357
358/*PCIE video card used*/
6d0f6bcf 359#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_PHYS
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360
361/*PCI video card used*/
6d0f6bcf 362/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/
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363
364/* video */
365#define CONFIG_VIDEO
366
367#if defined(CONFIG_VIDEO)
368#define CONFIG_BIOSEMU
369#define CONFIG_CFB_CONSOLE
370#define CONFIG_VIDEO_SW_CURSOR
371#define CONFIG_VGA_AS_SINGLE_DEVICE
372#define CONFIG_ATI_RADEON_FB
373#define CONFIG_VIDEO_LOGO
374/*#define CONFIG_CONSOLE_CURSOR*/
6d0f6bcf 375#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_PHYS
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376#endif
377
378#undef CONFIG_EEPRO100
379#undef CONFIG_TULIP
380#undef CONFIG_RTL8139
381
382#ifdef CONFIG_RTL8139
383/* This macro is used by RTL8139 but not defined in PPC architecture */
384#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
385#define _IO_BASE 0x00000000
386#endif
387
388#ifndef CONFIG_PCI_PNP
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389 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
390 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE
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391 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
392#endif
393
394#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
395
396#endif /* CONFIG_PCI */
397
398/* SATA */
399#define CONFIG_LIBATA
400#define CONFIG_FSL_SATA
401
6d0f6bcf 402#define CONFIG_SYS_SATA_MAX_DEVICE 2
9490a7f1 403#define CONFIG_SATA1
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404#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
405#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
9490a7f1 406#define CONFIG_SATA2
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407#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
408#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
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409
410#ifdef CONFIG_FSL_SATA
411#define CONFIG_LBA48
412#define CONFIG_CMD_SATA
413#define CONFIG_DOS_PARTITION
414#define CONFIG_CMD_EXT2
415#endif
416
417#if defined(CONFIG_TSEC_ENET)
418
419#ifndef CONFIG_NET_MULTI
420#define CONFIG_NET_MULTI 1
421#endif
422
423#define CONFIG_MII 1 /* MII PHY management */
424#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
425#define CONFIG_TSEC1 1
426#define CONFIG_TSEC1_NAME "eTSEC1"
427#define CONFIG_TSEC3 1
428#define CONFIG_TSEC3_NAME "eTSEC3"
429
430#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
431#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
432
433#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
434#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
435
436#define TSEC1_PHYIDX 0
437#define TSEC3_PHYIDX 0
438
439#define CONFIG_ETHPRIME "eTSEC1"
440
441#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
442
443#endif /* CONFIG_TSEC_ENET */
444
445/*
446 * Environment
447 */
5a1aceb0 448#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf 449#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
0e8d1586 450#define CONFIG_ENV_ADDR 0xfff80000
9490a7f1 451#else
6d0f6bcf 452#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
9490a7f1 453#endif
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454#define CONFIG_ENV_SIZE 0x2000
455#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
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456
457#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 458#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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459
460/*
461 * Command line configuration.
462 */
463#include <config_cmd_default.h>
464
465#define CONFIG_CMD_IRQ
466#define CONFIG_CMD_PING
467#define CONFIG_CMD_I2C
468#define CONFIG_CMD_MII
469#define CONFIG_CMD_ELF
470
471#if defined(CONFIG_PCI)
472#define CONFIG_CMD_PCI
473#define CONFIG_CMD_BEDBUG
474#define CONFIG_CMD_NET
475#endif
476
477#undef CONFIG_WATCHDOG /* watchdog disabled */
478
479/*
480 * Miscellaneous configurable options
481 */
6d0f6bcf 482#define CONFIG_SYS_LONGHELP /* undef to save memory */
9490a7f1 483#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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484#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
485#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
9490a7f1 486#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 487#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
9490a7f1 488#else
6d0f6bcf 489#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
9490a7f1 490#endif
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491#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
492#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
493#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
494#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
9490a7f1
KG
495
496/*
497 * For booting Linux, the board info and command line data
498 * have to be in the first 8 MB of memory, since this is
499 * the maximum mapped by the Linux kernel during initialization.
500 */
6d0f6bcf 501#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
9490a7f1
KG
502
503/*
504 * Internal Definitions
505 *
506 * Boot Flags
507 */
508#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
509#define BOOTFLAG_WARM 0x02 /* Software reboot */
510
511#if defined(CONFIG_CMD_KGDB)
512#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
513#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
514#endif
515
516/*
517 * Environment Configuration
518 */
519
520/* The mac addresses for all ethernet interface */
521#if defined(CONFIG_TSEC_ENET)
522#define CONFIG_HAS_ETH0
523#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
524#define CONFIG_HAS_ETH1
525#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
526#define CONFIG_HAS_ETH2
527#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
528#define CONFIG_HAS_ETH3
529#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
530#endif
531
532#define CONFIG_IPADDR 192.168.1.254
533
534#define CONFIG_HOSTNAME unknown
535#define CONFIG_ROOTPATH /opt/nfsroot
536#define CONFIG_BOOTFILE uImage
537#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
538
539#define CONFIG_SERVERIP 192.168.1.1
540#define CONFIG_GATEWAYIP 192.168.1.1
541#define CONFIG_NETMASK 255.255.255.0
542
543/* default location for tftp and bootm */
544#define CONFIG_LOADADDR 1000000
545
546#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
547#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
548
549#define CONFIG_BAUDRATE 115200
550
551#define CONFIG_EXTRA_ENV_SETTINGS \
552 "netdev=eth0\0" \
553 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
554 "tftpflash=tftpboot $loadaddr $uboot; " \
555 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
556 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
557 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
558 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
559 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
560 "consoledev=ttyS0\0" \
561 "ramdiskaddr=2000000\0" \
562 "ramdiskfile=8536ds/ramdisk.uboot\0" \
563 "fdtaddr=c00000\0" \
564 "fdtfile=8536ds/mpc8536ds.dtb\0" \
565 "bdev=sda3\0"
566
567#define CONFIG_HDBOOT \
568 "setenv bootargs root=/dev/$bdev rw " \
569 "console=$consoledev,$baudrate $othbootargs;" \
570 "tftp $loadaddr $bootfile;" \
571 "tftp $fdtaddr $fdtfile;" \
572 "bootm $loadaddr - $fdtaddr"
573
574#define CONFIG_NFSBOOTCOMMAND \
575 "setenv bootargs root=/dev/nfs rw " \
576 "nfsroot=$serverip:$rootpath " \
577 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
578 "console=$consoledev,$baudrate $othbootargs;" \
579 "tftp $loadaddr $bootfile;" \
580 "tftp $fdtaddr $fdtfile;" \
581 "bootm $loadaddr - $fdtaddr"
582
583#define CONFIG_RAMBOOTCOMMAND \
584 "setenv bootargs root=/dev/ram rw " \
585 "console=$consoledev,$baudrate $othbootargs;" \
586 "tftp $ramdiskaddr $ramdiskfile;" \
587 "tftp $loadaddr $bootfile;" \
588 "tftp $fdtaddr $fdtfile;" \
589 "bootm $loadaddr $ramdiskaddr $fdtaddr"
590
591#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
592
593#endif /* __CONFIG_H */