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9490a7f1 KG |
1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8536ds board configuration file | |
25 | * | |
26 | */ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* High Level Configuration Options */ | |
31 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
32 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
33 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
34 | #define CONFIG_MPC8536 1 | |
35 | #define CONFIG_MPC8536DS 1 | |
36 | ||
37 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ | |
38 | #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ | |
39 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
40 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
41 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
42 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
43 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
0151cbac | 44 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
9490a7f1 KG |
45 | |
46 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
47 | ||
48 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
49 | #define CONFIG_ENV_OVERWRITE | |
50 | ||
51 | /* | |
52 | * When initializing flash, if we cannot find the manufacturer ID, | |
53 | * assume this is the AMD flash associated with the CDS board. | |
54 | * This allows booting from a promjet. | |
55 | */ | |
56 | #define CONFIG_ASSUME_AMD_FLASH | |
57 | ||
58 | #ifndef __ASSEMBLY__ | |
59 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
60 | extern unsigned long get_board_ddr_clk(unsigned long dummy); | |
61 | #endif | |
62 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
c0391111 | 63 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) |
9490a7f1 KG |
64 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
65 | #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq | |
66 | from ICS307 instead of switches */ | |
67 | ||
68 | /* | |
69 | * These can be toggled for performance analysis, otherwise use default. | |
70 | */ | |
71 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
72 | #define CONFIG_BTB /* toggle branch predition */ | |
9490a7f1 KG |
73 | |
74 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
75 | ||
6d0f6bcf JCPV |
76 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
77 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff | |
9490a7f1 KG |
78 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
79 | ||
80 | /* | |
81 | * Base addresses -- Note these are effective addresses where the | |
82 | * actual resources get mapped (not physical addresses) | |
83 | */ | |
6d0f6bcf JCPV |
84 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
85 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ | |
86 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
87 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
9490a7f1 | 88 | |
6d0f6bcf JCPV |
89 | #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) |
90 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) | |
91 | #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) | |
92 | #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) | |
9490a7f1 KG |
93 | |
94 | /* DDR Setup */ | |
95 | #define CONFIG_FSL_DDR2 | |
96 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
97 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
98 | #define CONFIG_DDR_SPD | |
99 | #undef CONFIG_DDR_DLL | |
100 | ||
9b0ad1b1 | 101 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
9490a7f1 KG |
102 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
103 | ||
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
105 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
9490a7f1 KG |
106 | |
107 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
108 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
109 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
110 | ||
111 | /* I2C addresses of SPD EEPROMs */ | |
112 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
9490a7f1 KG |
114 | |
115 | /* These are used when DDR doesn't use SPD. */ | |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
117 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F | |
118 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
119 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
120 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
121 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 | |
122 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
123 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
124 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
125 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 | |
126 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
127 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
128 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
129 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
130 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ | |
131 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 | |
132 | ||
133 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
134 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
135 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
9490a7f1 | 136 | |
9490a7f1 KG |
137 | /* Make sure required options are set */ |
138 | #ifndef CONFIG_SPD_EEPROM | |
139 | #error ("CONFIG_SPD_EEPROM is required") | |
140 | #endif | |
141 | ||
142 | #undef CONFIG_CLOCKS_IN_MHZ | |
143 | ||
144 | ||
145 | /* | |
146 | * Memory map -- xxx -this is wrong, needs updating | |
147 | * | |
148 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
149 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
150 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
151 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
152 | * | |
153 | * Localbus cacheable (TBD) | |
154 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
155 | * | |
156 | * Localbus non-cacheable | |
c57fc289 | 157 | * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable |
9490a7f1 | 158 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
c57fc289 | 159 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
9490a7f1 KG |
160 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
161 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
162 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
163 | */ | |
164 | ||
165 | /* | |
166 | * Local Bus Definitions | |
167 | */ | |
6d0f6bcf | 168 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
c953ddfd | 169 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
9490a7f1 | 170 | |
c953ddfd KG |
171 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) |
172 | #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 | |
9490a7f1 | 173 | |
c953ddfd KG |
174 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
175 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
9490a7f1 | 176 | |
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} |
178 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
9490a7f1 KG |
179 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
180 | ||
6d0f6bcf JCPV |
181 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
182 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
183 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
184 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
185 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
9490a7f1 | 186 | |
6d0f6bcf | 187 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
9490a7f1 KG |
188 | |
189 | #define CONFIG_FLASH_CFI_DRIVER | |
6d0f6bcf JCPV |
190 | #define CONFIG_SYS_FLASH_CFI |
191 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
192 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
9490a7f1 KG |
193 | |
194 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
195 | ||
196 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ | |
197 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
52b565f5 | 198 | #define PIXIS_BASE_PHYS PIXIS_BASE |
9490a7f1 | 199 | |
52b565f5 | 200 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
6d0f6bcf | 201 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
9490a7f1 KG |
202 | |
203 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
204 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
205 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
206 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
207 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
208 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
209 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
210 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
211 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
212 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
213 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
214 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
215 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
216 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
217 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
218 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
219 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
220 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
221 | #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ | |
222 | #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ | |
223 | #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ | |
224 | #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ | |
225 | #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ | |
226 | #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ | |
227 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
228 | #define PIXIS_LED 0x25 /* LED Register */ | |
229 | ||
230 | /* old pixis referenced names */ | |
231 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
232 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
6d0f6bcf | 233 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
9490a7f1 | 234 | |
6d0f6bcf JCPV |
235 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
236 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
237 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
9490a7f1 | 238 | |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
240 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
241 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
9490a7f1 | 242 | |
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
244 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
9490a7f1 | 245 | |
c57fc289 JJ |
246 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
247 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
248 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ | |
249 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
250 | CONFIG_SYS_NAND_BASE + 0x80000, \ | |
251 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
252 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
c57fc289 JJ |
253 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
254 | #define CONFIG_CMD_NAND 1 | |
255 | #define CONFIG_NAND_FSL_ELBC 1 | |
256 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
257 | ||
258 | /* NAND flash config */ | |
259 | #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ | |
260 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
261 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
262 | | BR_MS_FCM /* MSEL = FCM */ \ | |
263 | | BR_V) /* valid */ | |
264 | #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
265 | | OR_FCM_PGS /* Large Page*/ \ | |
266 | | OR_FCM_CSCT \ | |
267 | | OR_FCM_CST \ | |
268 | | OR_FCM_CHT \ | |
269 | | OR_FCM_SCY_1 \ | |
270 | | OR_FCM_TRLX \ | |
271 | | OR_FCM_EHTR) | |
272 | ||
273 | #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ | |
274 | #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
275 | ||
276 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ | |
277 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
278 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
279 | | BR_MS_FCM /* MSEL = FCM */ \ | |
280 | | BR_V) /* valid */ | |
281 | #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
282 | #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ | |
283 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
284 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
285 | | BR_MS_FCM /* MSEL = FCM */ \ | |
286 | | BR_V) /* valid */ | |
287 | #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
288 | ||
289 | #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ | |
290 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
291 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
292 | | BR_MS_FCM /* MSEL = FCM */ \ | |
293 | | BR_V) /* valid */ | |
294 | #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
295 | ||
9490a7f1 KG |
296 | /* Serial Port - controlled on board with jumper J8 |
297 | * open - index 2 | |
298 | * shorted - index 1 | |
299 | */ | |
300 | #define CONFIG_CONS_INDEX 1 | |
301 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
6d0f6bcf JCPV |
302 | #define CONFIG_SYS_NS16550 |
303 | #define CONFIG_SYS_NS16550_SERIAL | |
304 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
305 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
9490a7f1 | 306 | |
6d0f6bcf | 307 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
9490a7f1 KG |
308 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
309 | ||
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
311 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
9490a7f1 KG |
312 | |
313 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
314 | #define CONFIG_SYS_HUSH_PARSER |
315 | #ifdef CONFIG_SYS_HUSH_PARSER | |
316 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
9490a7f1 KG |
317 | #endif |
318 | ||
319 | /* | |
320 | * Pass open firmware flat tree | |
321 | */ | |
322 | #define CONFIG_OF_LIBFDT 1 | |
323 | #define CONFIG_OF_BOARD_SETUP 1 | |
324 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
325 | ||
6d0f6bcf JCPV |
326 | #define CONFIG_SYS_64BIT_STRTOUL 1 |
327 | #define CONFIG_SYS_64BIT_VSPRINTF 1 | |
9490a7f1 KG |
328 | |
329 | ||
330 | /* | |
331 | * I2C | |
332 | */ | |
333 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
334 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
335 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
336 | #define CONFIG_I2C_MULTI_BUS | |
337 | #define CONFIG_I2C_CMD_TREE | |
6d0f6bcf JCPV |
338 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
339 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
340 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ | |
341 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
342 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
9490a7f1 KG |
343 | |
344 | /* | |
345 | * I2C2 EEPROM | |
346 | */ | |
32628c50 JCPV |
347 | #define CONFIG_ID_EEPROM |
348 | #ifdef CONFIG_ID_EEPROM | |
6d0f6bcf | 349 | #define CONFIG_SYS_I2C_EEPROM_NXID |
9490a7f1 | 350 | #endif |
6d0f6bcf JCPV |
351 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
352 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
353 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
9490a7f1 KG |
354 | |
355 | /* | |
356 | * General PCI | |
357 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
358 | */ | |
359 | ||
10795f42 KG |
360 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
361 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS | |
6d0f6bcf | 362 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
5f91ef6a | 363 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
364 | #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 |
365 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ | |
9490a7f1 KG |
366 | |
367 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
10795f42 KG |
368 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 |
369 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS | |
6d0f6bcf | 370 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ |
5f91ef6a | 371 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
372 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 |
373 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
9490a7f1 KG |
374 | |
375 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
10795f42 KG |
376 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 |
377 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS | |
6d0f6bcf | 378 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ |
5f91ef6a | 379 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
380 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 |
381 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
9490a7f1 KG |
382 | |
383 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ | |
10795f42 KG |
384 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 |
385 | #define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS | |
6d0f6bcf | 386 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
5f91ef6a | 387 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
388 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 |
389 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
9490a7f1 KG |
390 | |
391 | #if defined(CONFIG_PCI) | |
392 | ||
393 | #define CONFIG_NET_MULTI | |
394 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
395 | ||
396 | /*PCIE video card used*/ | |
6d0f6bcf | 397 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_PHYS |
9490a7f1 KG |
398 | |
399 | /*PCI video card used*/ | |
6d0f6bcf | 400 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/ |
9490a7f1 KG |
401 | |
402 | /* video */ | |
403 | #define CONFIG_VIDEO | |
404 | ||
405 | #if defined(CONFIG_VIDEO) | |
406 | #define CONFIG_BIOSEMU | |
407 | #define CONFIG_CFB_CONSOLE | |
408 | #define CONFIG_VIDEO_SW_CURSOR | |
409 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
410 | #define CONFIG_ATI_RADEON_FB | |
411 | #define CONFIG_VIDEO_LOGO | |
412 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
6d0f6bcf | 413 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_PHYS |
9490a7f1 KG |
414 | #endif |
415 | ||
416 | #undef CONFIG_EEPRO100 | |
417 | #undef CONFIG_TULIP | |
418 | #undef CONFIG_RTL8139 | |
419 | ||
420 | #ifdef CONFIG_RTL8139 | |
421 | /* This macro is used by RTL8139 but not defined in PPC architecture */ | |
422 | #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) | |
423 | #define _IO_BASE 0x00000000 | |
424 | #endif | |
425 | ||
426 | #ifndef CONFIG_PCI_PNP | |
5f91ef6a KG |
427 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
428 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
9490a7f1 KG |
429 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
430 | #endif | |
431 | ||
432 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
433 | ||
434 | #endif /* CONFIG_PCI */ | |
435 | ||
436 | /* SATA */ | |
437 | #define CONFIG_LIBATA | |
438 | #define CONFIG_FSL_SATA | |
439 | ||
6d0f6bcf | 440 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
9490a7f1 | 441 | #define CONFIG_SATA1 |
6d0f6bcf JCPV |
442 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
443 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
9490a7f1 | 444 | #define CONFIG_SATA2 |
6d0f6bcf JCPV |
445 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
446 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
9490a7f1 KG |
447 | |
448 | #ifdef CONFIG_FSL_SATA | |
449 | #define CONFIG_LBA48 | |
450 | #define CONFIG_CMD_SATA | |
451 | #define CONFIG_DOS_PARTITION | |
452 | #define CONFIG_CMD_EXT2 | |
453 | #endif | |
454 | ||
455 | #if defined(CONFIG_TSEC_ENET) | |
456 | ||
457 | #ifndef CONFIG_NET_MULTI | |
458 | #define CONFIG_NET_MULTI 1 | |
459 | #endif | |
460 | ||
461 | #define CONFIG_MII 1 /* MII PHY management */ | |
462 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
463 | #define CONFIG_TSEC1 1 | |
464 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
465 | #define CONFIG_TSEC3 1 | |
466 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
467 | ||
2e26d837 JJ |
468 | #define CONFIG_FSL_SGMII_RISER 1 |
469 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
470 | ||
9490a7f1 KG |
471 | #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ |
472 | #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ | |
473 | ||
474 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
475 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
476 | ||
477 | #define TSEC1_PHYIDX 0 | |
478 | #define TSEC3_PHYIDX 0 | |
479 | ||
480 | #define CONFIG_ETHPRIME "eTSEC1" | |
481 | ||
482 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
483 | ||
484 | #endif /* CONFIG_TSEC_ENET */ | |
485 | ||
486 | /* | |
487 | * Environment | |
488 | */ | |
5a1aceb0 | 489 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 490 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
0e8d1586 | 491 | #define CONFIG_ENV_ADDR 0xfff80000 |
9490a7f1 | 492 | #else |
c57fc289 | 493 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
9490a7f1 | 494 | #endif |
0e8d1586 JCPV |
495 | #define CONFIG_ENV_SIZE 0x2000 |
496 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
9490a7f1 KG |
497 | |
498 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 499 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
9490a7f1 KG |
500 | |
501 | /* | |
502 | * Command line configuration. | |
503 | */ | |
504 | #include <config_cmd_default.h> | |
505 | ||
506 | #define CONFIG_CMD_IRQ | |
507 | #define CONFIG_CMD_PING | |
508 | #define CONFIG_CMD_I2C | |
509 | #define CONFIG_CMD_MII | |
510 | #define CONFIG_CMD_ELF | |
1c9aa76b KG |
511 | #define CONFIG_CMD_IRQ |
512 | #define CONFIG_CMD_SETEXPR | |
9490a7f1 KG |
513 | |
514 | #if defined(CONFIG_PCI) | |
515 | #define CONFIG_CMD_PCI | |
516 | #define CONFIG_CMD_BEDBUG | |
517 | #define CONFIG_CMD_NET | |
518 | #endif | |
519 | ||
520 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
521 | ||
522 | /* | |
523 | * Miscellaneous configurable options | |
524 | */ | |
6d0f6bcf | 525 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
9490a7f1 | 526 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
6d0f6bcf JCPV |
527 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
528 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
9490a7f1 | 529 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 530 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
9490a7f1 | 531 | #else |
6d0f6bcf | 532 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
9490a7f1 | 533 | #endif |
6d0f6bcf JCPV |
534 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
535 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
536 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
537 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
9490a7f1 KG |
538 | |
539 | /* | |
540 | * For booting Linux, the board info and command line data | |
541 | * have to be in the first 8 MB of memory, since this is | |
542 | * the maximum mapped by the Linux kernel during initialization. | |
543 | */ | |
6d0f6bcf | 544 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
9490a7f1 KG |
545 | |
546 | /* | |
547 | * Internal Definitions | |
548 | * | |
549 | * Boot Flags | |
550 | */ | |
551 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
552 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
553 | ||
554 | #if defined(CONFIG_CMD_KGDB) | |
555 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
556 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
557 | #endif | |
558 | ||
559 | /* | |
560 | * Environment Configuration | |
561 | */ | |
562 | ||
563 | /* The mac addresses for all ethernet interface */ | |
564 | #if defined(CONFIG_TSEC_ENET) | |
565 | #define CONFIG_HAS_ETH0 | |
566 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD | |
567 | #define CONFIG_HAS_ETH1 | |
568 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
569 | #define CONFIG_HAS_ETH2 | |
570 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD | |
571 | #define CONFIG_HAS_ETH3 | |
572 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD | |
573 | #endif | |
574 | ||
575 | #define CONFIG_IPADDR 192.168.1.254 | |
576 | ||
577 | #define CONFIG_HOSTNAME unknown | |
578 | #define CONFIG_ROOTPATH /opt/nfsroot | |
579 | #define CONFIG_BOOTFILE uImage | |
580 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
581 | ||
582 | #define CONFIG_SERVERIP 192.168.1.1 | |
583 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
584 | #define CONFIG_NETMASK 255.255.255.0 | |
585 | ||
586 | /* default location for tftp and bootm */ | |
587 | #define CONFIG_LOADADDR 1000000 | |
588 | ||
589 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
590 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
591 | ||
592 | #define CONFIG_BAUDRATE 115200 | |
593 | ||
594 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
595 | "netdev=eth0\0" \ | |
596 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
597 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
598 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
599 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
600 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
601 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
602 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
603 | "consoledev=ttyS0\0" \ | |
604 | "ramdiskaddr=2000000\0" \ | |
605 | "ramdiskfile=8536ds/ramdisk.uboot\0" \ | |
606 | "fdtaddr=c00000\0" \ | |
607 | "fdtfile=8536ds/mpc8536ds.dtb\0" \ | |
608 | "bdev=sda3\0" | |
609 | ||
610 | #define CONFIG_HDBOOT \ | |
611 | "setenv bootargs root=/dev/$bdev rw " \ | |
612 | "console=$consoledev,$baudrate $othbootargs;" \ | |
613 | "tftp $loadaddr $bootfile;" \ | |
614 | "tftp $fdtaddr $fdtfile;" \ | |
615 | "bootm $loadaddr - $fdtaddr" | |
616 | ||
617 | #define CONFIG_NFSBOOTCOMMAND \ | |
618 | "setenv bootargs root=/dev/nfs rw " \ | |
619 | "nfsroot=$serverip:$rootpath " \ | |
620 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
621 | "console=$consoledev,$baudrate $othbootargs;" \ | |
622 | "tftp $loadaddr $bootfile;" \ | |
623 | "tftp $fdtaddr $fdtfile;" \ | |
624 | "bootm $loadaddr - $fdtaddr" | |
625 | ||
626 | #define CONFIG_RAMBOOTCOMMAND \ | |
627 | "setenv bootargs root=/dev/ram rw " \ | |
628 | "console=$consoledev,$baudrate $othbootargs;" \ | |
629 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
630 | "tftp $loadaddr $bootfile;" \ | |
631 | "tftp $fdtaddr $fdtfile;" \ | |
632 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
633 | ||
634 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
635 | ||
636 | #endif /* __CONFIG_H */ |