[people/ms/u-boot.git] / include / configs / MPC8540ADS.h

/*
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8540ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
#define CONFIG_MPC8540		1	/* MPC8540 specific */
#define CONFIG_MPC8540ADS	1	/* MPC8540ADS board specific */

#ifndef CONFIG_HAS_FEC
#define CONFIG_HAS_FEC		1	/* 8540 has FEC */
#endif

#define CONFIG_PCI
#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL			/* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 *
 * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
 * 33MHz to accommodate, based on a PCI pin.
 * Note that PCI-X won't work at 33MHz.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif


/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#undef	CFG_DRAM_TEST			/* memory test, takes time */
#define CFG_MEMTEST_START	0x00200000	/* memtest region */
#define CFG_MEMTEST_END		0x00400000


/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */


/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#if defined(CONFIG_SPD_EEPROM)
    /*
     * Determine DDR configuration from I2C interface.
     */
    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */

#else
    /*
     * Manually set up DDR parameters
     */
    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
    #define CFG_DDR_CS0_CONFIG	0x80000002
    #define CFG_DDR_TIMING_1	0x37344321
    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
#endif


/*
 * SDRAM on the Local Bus
 */
#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CFG_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef  CFG_RAMBOOT
#endif

#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ


/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CFG_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CFG_OR2_PRELIM		0xfc006901

#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

/*
 * LSDMR masks
 */
#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))

#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))

#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_BSMA1516	\
				| CFG_LBC_LSDMR_RFCR5		\
				| CFG_LBC_LSDMR_PRETOACT3	\
				| CFG_LBC_LSDMR_ACTTORW3	\
				| CFG_LBC_LSDMR_BL8		\
				| CFG_LBC_LSDMR_WRC2		\
				| CFG_LBC_LSDMR_CL3		\
				| CFG_LBC_LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_NORMAL)


/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CFG_BR4_PRELIM          0xf8000801
#define CFG_OR4_PRELIM		0xffffe1f1
#define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 	1
#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN	    	(256 * 1024)    /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

#define CFG_64BIT_VSPRINTF	1
#define CFG_64BIT_STRTOUL	1

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
#define CFG_I2C_OFFSET		0x3000

/* RapidIO MMU */
#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI1_IO_BASE	0x00000000
#define CFG_PCI1_IO_PHYS	0xe2000000
#define CFG_PCI1_IO_SIZE	0x100000	/* 1M */

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT


#if CONFIG_HAS_FEC
#define CONFIG_MPC85XX_FEC	1
#define CONFIG_MPC85XX_FEC_NAME		"FEC"
#define FEC_PHY_ADDR		3
#define FEC_PHYIDX		0
#define FEC_FLAGS		0
#endif

/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */


/*
 * Environment
 */
#ifndef CFG_RAMBOOT
  #define CFG_ENV_IS_IN_FLASH	1
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
  #define CFG_ENV_SIZE		0x2000
#else
  #define CFG_NO_FLASH		1	/* Flash is not usable now */
  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
  #define CFG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ELF

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CFG_RAMBOOT)
    #undef CONFIG_CMD_ENV
    #undef CONFIG_CMD_LOADS
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
#define CFG_LOAD_ADDR	0x2000000	/* default load address */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif


/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		/nfsroot
#define CONFIG_BOOTFILE		your.uImage

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=1000000\0"						\
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
42d1f039	1	/*
0ac6f8b7	2	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2002,2003 Motorola,Inc.
	4	* Xianghua Xiao <X.Xiao@motorola.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
0ac6f8b7 WD	25	/*
	26	* mpc8540ads board configuration file
	27	*
	28	* Please refer to doc/README.mpc85xx for more info.
	29	*
	30	* Make sure you change the MAC address and other network params first,
	31	* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
42d1f039 WD	32	*/
	33
	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/* High Level Configuration Options */
0ac6f8b7 WD	38	#define CONFIG_BOOKE 1 /* BOOKE */
	39	#define CONFIG_E500 1 /* BOOKE e500 family */
	40	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
	41	#define CONFIG_MPC8540 1 /* MPC8540 specific */
	42	#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
	43
288693ab JL	44	#ifndef CONFIG_HAS_FEC
	45	#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
	46	#endif
	47
0ac6f8b7 WD	48	#define CONFIG_PCI
0ac6f8b7 WD	49	#define CONFIG_TSEC_ENET /* tsec ethernet support */
42d1f039	50	#define CONFIG_ENV_OVERWRITE
0ac6f8b7	51	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
0ac6f8b7 WD	52	#define CONFIG_DDR_DLL /* possible DLL fix needed */
0ac6f8b7 WD	53	#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
42d1f039	54
d9b94f28 JL	55	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	56	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	57
7232a272	58	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
42d1f039	59
0ac6f8b7 WD	60	/*
	61	* sysclk for MPC85xx
	62	*
	63	* Two valid values are:
	64	* 33000000
	65	* 66000000
	66	*
	67	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	68	* is likely the desired value here, so that is now the default.
	69	* The board, however, can run at 66MHz. In any event, this value
	70	* must match the settings of some switches. Details can be found
	71	* in the README.mpc85xxads.
34c3c0e0 MM	72	*
	73	* XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
	74	* 33MHz to accommodate, based on a PCI pin.
	75	* Note that PCI-X won't work at 33MHz.
0ac6f8b7 WD	76	*/
0ac6f8b7 WD	77
9aea9530	78	#ifndef CONFIG_SYS_CLK_FREQ
34c3c0e0	79	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	80	#endif
42d1f039 WD	81
9aea9530	82
0ac6f8b7 WD	83	/*
	84	* These can be toggled for performance analysis, otherwise use default.
	85	*/
	86	#define CONFIG_L2_CACHE /* toggle L2 cache */
	87	#define CONFIG_BTB /* toggle branch predition */
	88	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
42d1f039	89
0ac6f8b7	90	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
42d1f039	91
0ac6f8b7 WD	92	#undef CFG_DRAM_TEST /* memory test, takes time */
0ac6f8b7 WD	93	#define CFG_MEMTEST_START 0x00200000 /* memtest region */
42d1f039 WD	94	#define CFG_MEMTEST_END 0x00400000
42d1f039 WD	95
42d1f039 WD	96
	97	/*
	98	* Base addresses -- Note these are effective addresses where the
	99	* actual resources get mapped (not physical addresses)
	100	*/
0ac6f8b7 WD	101	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
0ac6f8b7 WD	102	#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
f69766e4	103	#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
0ac6f8b7	104	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
42d1f039	105
9aea9530 WD	106
	107	/*
	108	* DDR Setup
	109	*/
0ac6f8b7	110	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
42d1f039	111	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
9aea9530 WD	112
	113	#if defined(CONFIG_SPD_EEPROM)
	114	/*
	115	* Determine DDR configuration from I2C interface.
	116	*/
	117	#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
	118
	119	#else
	120	/*
	121	* Manually set up DDR parameters
	122	*/
	123	#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
	124	#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	125	#define CFG_DDR_CS0_CONFIG 0x80000002
	126	#define CFG_DDR_TIMING_1 0x37344321
	127	#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	128	#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	129	#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	130	#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
	131	#endif
	132
42d1f039	133
0ac6f8b7 WD	134	/*
	135	* SDRAM on the Local Bus
	136	*/
0ac6f8b7	137	#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
0ac6f8b7	138	#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	139
0ac6f8b7 WD	140	#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
0ac6f8b7 WD	141	#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	142
0ac6f8b7 WD	143	#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	144	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
	145	#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
42d1f039	146	#undef CFG_FLASH_CHECKSUM
0ac6f8b7 WD	147	#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	148	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	149
	150	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
42d1f039	151
42d1f039 WD	152	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	153	#define CFG_RAMBOOT
	154	#else
0ac6f8b7	155	#undef CFG_RAMBOOT
42d1f039 WD	156	#endif
42d1f039 WD	157
cf33678e WD	158	#define CFG_FLASH_CFI_DRIVER
	159	#define CFG_FLASH_CFI
	160	#define CFG_FLASH_EMPTY_INFO
42d1f039	161
0ac6f8b7 WD	162	#undef CONFIG_CLOCKS_IN_MHZ
0ac6f8b7 WD	163
42d1f039	164
0ac6f8b7 WD	165	/*
	166	* Local Bus Definitions
	167	*/
	168
	169	/*
	170	* Base Register 2 and Option Register 2 configure SDRAM.
	171	* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
	172	*
	173	* For BR2, need:
	174	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	175	* port-size = 32-bits = BR2[19:20] = 11
	176	* no parity checking = BR2[21:22] = 00
	177	* SDRAM for MSEL = BR2[24:26] = 011
	178	* Valid = BR[31] = 1
	179	*
	180	* 0 4 8 12 16 20 24 28
	181	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	182	*
	183	* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
	184	* FIXME: the top 17 bits of BR2.
	185	*/
	186
	187	#define CFG_BR2_PRELIM 0xf0001861
	188
	189	/*
	190	* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
	191	*
	192	* For OR2, need:
	193	* 64MB mask for AM, OR2[0:7] = 1111 1100
	194	* XAM, OR2[17:18] = 11
	195	* 9 columns OR2[19-21] = 010
	196	* 13 rows OR2[23-25] = 100
	197	* EAD set for extra time OR[31] = 1
	198	*
	199	* 0 4 8 12 16 20 24 28
	200	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	201	*/
	202
42d1f039	203	#define CFG_OR2_PRELIM 0xfc006901
0ac6f8b7 WD	204
	205	#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	206	#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
	207	#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	208	#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
	209
	210	/*
	211	* LSDMR masks
	212	*/
	213	#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
	214	#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
	215	#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
	216	#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
	217	#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
	218	#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
	219	#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
	220	#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
	221	#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
	222	#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
	223	#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
	224	#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
	225	#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
	226	#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
	227	#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
	228
	229	#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
	230	#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
	231	#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
	232	#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
	233	#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
	234	#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
	235	#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
	236	#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
	237
	238	#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
	239	\| CFG_LBC_LSDMR_RFCR5 \
	240	\| CFG_LBC_LSDMR_PRETOACT3 \
	241	\| CFG_LBC_LSDMR_ACTTORW3 \
	242	\| CFG_LBC_LSDMR_BL8 \
	243	\| CFG_LBC_LSDMR_WRC2 \
	244	\| CFG_LBC_LSDMR_CL3 \
	245	\| CFG_LBC_LSDMR_RFEN \
	246	)
	247
	248	/*
	249	* SDRAM Controller configuration sequence.
	250	*/
	251	#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
9aea9530	252	\| CFG_LBC_LSDMR_OP_PCHALL)
0ac6f8b7	253	#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
9aea9530	254	\| CFG_LBC_LSDMR_OP_ARFRSH)
0ac6f8b7	255	#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
9aea9530	256	\| CFG_LBC_LSDMR_OP_ARFRSH)
0ac6f8b7	257	#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
9aea9530	258	\| CFG_LBC_LSDMR_OP_MRW)
0ac6f8b7	259	#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
9aea9530	260	\| CFG_LBC_LSDMR_OP_NORMAL)
0ac6f8b7	261
42d1f039	262
9aea9530 WD	263	/*
	264	* 32KB, 8-bit wide for ADS config reg
	265	*/
	266	#define CFG_BR4_PRELIM 0xf8000801
c837dcb1 WD	267	#define CFG_OR4_PRELIM 0xffffe1f1
c837dcb1 WD	268	#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
42d1f039 WD	269
42d1f039 WD	270	#define CONFIG_L1_INIT_RAM
0ac6f8b7	271	#define CFG_INIT_RAM_LOCK 1
9aea9530	272	#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
0ac6f8b7	273	#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
42d1f039	274
0ac6f8b7	275	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
42d1f039 WD	276	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	277	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	278
a1191902	279	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
0ac6f8b7	280	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	281
	282	/* Serial Port */
	283	#define CONFIG_CONS_INDEX 1
	284	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	285	#define CFG_NS16550
	286	#define CFG_NS16550_SERIAL
0ac6f8b7	287	#define CFG_NS16550_REG_SIZE 1
42d1f039	288	#define CFG_NS16550_CLK get_bus_freq(0)
42d1f039 WD	289
	290	#define CFG_BAUDRATE_TABLE \
	291	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	292
0ac6f8b7 WD	293	#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
0ac6f8b7 WD	294	#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
42d1f039 WD	295
	296	/* Use the HUSH parser */
	297	#define CFG_HUSH_PARSER
0ac6f8b7	298	#ifdef CFG_HUSH_PARSER
42d1f039 WD	299	#define CFG_PROMPT_HUSH_PS2 "> "
	300	#endif
	301
0e16387d	302	/* pass open firmware flat tree */
0fd5ec66 KG	303	#define CONFIG_OF_LIBFDT 1
	304	#define CONFIG_OF_BOARD_SETUP 1
	305	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
0e16387d MM	306
	307	#define CFG_64BIT_VSPRINTF 1
	308	#define CFG_64BIT_STRTOUL 1
	309
20476726 JL	310	/*
	311	* I2C
	312	*/
	313	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	314	#define CONFIG_HARD_I2C /* I2C with hardware support*/
0ac6f8b7 WD	315	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
0ac6f8b7 WD	316	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
42d1f039	317	#define CFG_I2C_SLAVE 0x7F
0ac6f8b7	318	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
20476726	319	#define CFG_I2C_OFFSET 0x3000
0ac6f8b7 WD	320
	321	/* RapidIO MMU */
	322	#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
	323	#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
	324	#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
	325
	326	/*
	327	* General PCI
362dd830	328	* Memory space is mapped 1-1, but I/O space must start from 0.
0ac6f8b7 WD	329	*/
	330	#define CFG_PCI1_MEM_BASE 0x80000000
	331	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	332	#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
362dd830	333	#define CFG_PCI1_IO_BASE 0x00000000
c88f9fe6 MM	334	#define CFG_PCI1_IO_PHYS 0xe2000000
c88f9fe6 MM	335	#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
42d1f039	336
42d1f039	337	#if defined(CONFIG_PCI)
0ac6f8b7	338
42d1f039	339	#define CONFIG_NET_MULTI
9aea9530	340	#define CONFIG_PCI_PNP /* do pci plug-and-play */
0ac6f8b7	341
42d1f039	342	#undef CONFIG_EEPRO100
0ac6f8b7 WD	343	#undef CONFIG_TULIP
	344
	345	#if !defined(CONFIG_PCI_PNP)
	346	#define PCI_ENET0_IOADDR 0xe0000000
	347	#define PCI_ENET0_MEMADDR 0xe0000000
	348	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	349	#endif
0ac6f8b7 WD	350
	351	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	352	#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
	353
	354	#endif /* CONFIG_PCI */
	355
	356
	357	#if defined(CONFIG_TSEC_ENET)
	358
	359	#ifndef CONFIG_NET_MULTI
	360	#define CONFIG_NET_MULTI 1
42d1f039 WD	361	#endif
42d1f039 WD	362
0ac6f8b7	363	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	364	#define CONFIG_TSEC1 1
	365	#define CONFIG_TSEC1_NAME "TSEC0"
	366	#define CONFIG_TSEC2 1
	367	#define CONFIG_TSEC2_NAME "TSEC1"
0ac6f8b7 WD	368	#define TSEC1_PHY_ADDR 0
0ac6f8b7 WD	369	#define TSEC2_PHY_ADDR 1
0ac6f8b7 WD	370	#define TSEC1_PHYIDX 0
0ac6f8b7 WD	371	#define TSEC2_PHYIDX 0
3a79013e AF	372	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	373	#define TSEC2_FLAGS TSEC_GIGABIT
9aea9530	374
288693ab JL	375
288693ab JL	376	#if CONFIG_HAS_FEC
9aea9530	377	#define CONFIG_MPC85XX_FEC 1
d9b94f28	378	#define CONFIG_MPC85XX_FEC_NAME "FEC"
9aea9530	379	#define FEC_PHY_ADDR 3
0ac6f8b7	380	#define FEC_PHYIDX 0
3a79013e	381	#define FEC_FLAGS 0
288693ab	382	#endif
9aea9530	383
d9b94f28 JL	384	/* Options are: TSEC[0-1], FEC */
d9b94f28 JL	385	#define CONFIG_ETHPRIME "TSEC0"
0ac6f8b7 WD	386
	387	#endif /* CONFIG_TSEC_ENET */
	388
	389
	390	/*
	391	* Environment
	392	*/
42d1f039	393	#ifndef CFG_RAMBOOT
42d1f039 WD	394	#define CFG_ENV_IS_IN_FLASH 1
42d1f039 WD	395	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
0ac6f8b7	396	#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
42d1f039 WD	397	#define CFG_ENV_SIZE 0x2000
42d1f039 WD	398	#else
9aea9530 WD	399	#define CFG_NO_FLASH 1 /* Flash is not usable now */
	400	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	401	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	402	#define CFG_ENV_SIZE 0x2000
42d1f039 WD	403	#endif
42d1f039 WD	404
0ac6f8b7 WD	405	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
0ac6f8b7 WD	406	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	407
2835e518	408
659e2f67 JL	409	/*
	410	* BOOTP options
	411	*/
	412	#define CONFIG_BOOTP_BOOTFILESIZE
	413	#define CONFIG_BOOTP_BOOTPATH
	414	#define CONFIG_BOOTP_GATEWAY
	415	#define CONFIG_BOOTP_HOSTNAME
	416
	417
2835e518 JL	418	/*
	419	* Command line configuration.
	420	*/
	421	#include <config_cmd_default.h>
	422
	423	#define CONFIG_CMD_PING
	424	#define CONFIG_CMD_I2C
82ac8c97	425	#define CONFIG_CMD_ELF
2835e518 JL	426
	427	#if defined(CONFIG_PCI)
	428	#define CONFIG_CMD_PCI
	429	#endif
	430
9aea9530	431	#if defined(CFG_RAMBOOT)
2835e518 JL	432	#undef CONFIG_CMD_ENV
2835e518 JL	433	#undef CONFIG_CMD_LOADS
42d1f039	434	#endif
0ac6f8b7	435
42d1f039	436
0ac6f8b7	437	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	438
	439	/*
	440	* Miscellaneous configurable options
	441	*/
0ac6f8b7	442	#define CFG_LONGHELP /* undef to save memory */
22abb2d2	443	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
0ac6f8b7 WD	444	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	445	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	446
2835e518	447	#if defined(CONFIG_CMD_KGDB)
0ac6f8b7	448	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
42d1f039	449	#else
0ac6f8b7	450	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
42d1f039	451	#endif
0ac6f8b7	452
42d1f039	453	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
0ac6f8b7 WD	454	#define CFG_MAXARGS 16 /* max number of command args */
	455	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	456	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
42d1f039 WD	457
	458	/*
	459	* For booting Linux, the board info and command line data
	460	* have to be in the first 8 MB of memory, since this is
	461	* the maximum mapped by the Linux kernel during initialization.
	462	*/
0ac6f8b7	463	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
42d1f039	464
42d1f039 WD	465	/*
	466	* Internal Definitions
	467	*
	468	* Boot Flags
	469	*/
	470	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
0ac6f8b7	471	#define BOOTFLAG_WARM 0x02 /* Software reboot */
42d1f039	472
2835e518	473	#if defined(CONFIG_CMD_KGDB)
42d1f039 WD	474	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	475	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	476	#endif
	477
9aea9530 WD	478
	479	/*
	480	* Environment Configuration
	481	*/
0ac6f8b7 WD	482
0ac6f8b7 WD	483	/* The mac addresses for all ethernet interface */
42d1f039	484	#if defined(CONFIG_TSEC_ENET)
10327dc5	485	#define CONFIG_HAS_ETH0
0ac6f8b7	486	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
e2ffd59b	487	#define CONFIG_HAS_ETH1
0ac6f8b7	488	#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
e2ffd59b	489	#define CONFIG_HAS_ETH2
0ac6f8b7	490	#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
42d1f039 WD	491	#endif
42d1f039 WD	492
0ac6f8b7 WD	493	#define CONFIG_IPADDR 192.168.1.253
	494
	495	#define CONFIG_HOSTNAME unknown
	496	#define CONFIG_ROOTPATH /nfsroot
	497	#define CONFIG_BOOTFILE your.uImage
	498
	499	#define CONFIG_SERVERIP 192.168.1.1
	500	#define CONFIG_GATEWAYIP 192.168.1.1
	501	#define CONFIG_NETMASK 255.255.255.0
	502
	503	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	504
	505	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
	506	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	507
	508	#define CONFIG_BAUDRATE 115200
	509
9aea9530	510	#define CONFIG_EXTRA_ENV_SETTINGS \
0ac6f8b7 WD	511	"netdev=eth0\0" \
0ac6f8b7 WD	512	"consoledev=ttyS0\0" \
d3ec0d94	513	"ramdiskaddr=1000000\0" \
8272dc2f AF	514	"ramdiskfile=your.ramdisk.u-boot\0" \
	515	"fdtaddr=400000\0" \
	516	"fdtfile=your.fdt.dtb\0"
0ac6f8b7	517
9aea9530	518	#define CONFIG_NFSBOOTCOMMAND \
0ac6f8b7 WD	519	"setenv bootargs root=/dev/nfs rw " \
	520	"nfsroot=$serverip:$rootpath " \
	521	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	522	"console=$consoledev,$baudrate $othbootargs;" \
	523	"tftp $loadaddr $bootfile;" \
8272dc2f AF	524	"tftp $fdtaddr $fdtfile;" \
8272dc2f AF	525	"bootm $loadaddr - $fdtaddr"
0ac6f8b7 WD	526
	527	#define CONFIG_RAMBOOTCOMMAND \
	528	"setenv bootargs root=/dev/ram rw " \
	529	"console=$consoledev,$baudrate $othbootargs;" \
	530	"tftp $ramdiskaddr $ramdiskfile;" \
	531	"tftp $loadaddr $bootfile;" \
8272dc2f	532	"tftp $fdtaddr $fdtfile;" \
d3ec0d94	533	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0ac6f8b7 WD	534
0ac6f8b7 WD	535	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	536
42d1f039 WD	537	#endif /* __CONFIG_H */