[people/ms/u-boot.git] / include / configs / MPC8540EVAL.h

/*
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Modified by Lunsheng Wang, lunsheng@sohu.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* mpc8540eval board configuration file */
/* please refer to doc/README.mpc85xxads for more info */
/* make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
 */

#ifndef __CONFIG_H
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_BOOKE		1	    /* BOOKE			*/
#define CONFIG_E500		1	    /* BOOKE e500 family	*/
#define CONFIG_MPC85xx		1	    /* MPC8540/MPC8560		*/
#define CONFIG_MPC8540		1	    /* MPC8540 specific	        */
#define CONFIG_MPC8540EVAL	1	    /* MPC8540EVAL board specific */

#undef  CONFIG_PCI			    /* pci ethernet support	*/
#define CONFIG_TSEC_ENET		    /* tsec ethernet support  */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/* Using Localbus SDRAM to emulate flash before we can program the flash,
 * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
 * Not availabe for EVAL board
 */
#undef CONFIG_RAM_AS_FLASH

/* sysclk for MPC8540EVAL */
#if defined(CONFIG_SYSCLK_66M)
	/*
	 * the oscillator on board is 66Mhz
	 * can also get 66M clock from external PCI
	 */
	#define CONFIG_SYS_CLK_FREQ   66000000
#else
	#define CONFIG_SYS_CLK_FREQ   33000000   /* most pci cards are 33Mhz */
#endif

/* below can be toggled for performance analysis. otherwise use default */
#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
#undef  CONFIG_BTB			    /* toggle branch predition */

#define CONFIG_BOARD_PRE_INIT	1	    /* Call board_pre_init	*/

#undef	CONFIG_SYS_DRAM_TEST			    /* memory test, takes time  */
#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00400000

#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
#endif

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
#define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/

#define CONFIG_SYS_SDRAM_SIZE		256             /* DDR is now 256MB     */

#if defined(CONFIG_RAM_AS_FLASH)
#define CONFIG_SYS_LBC_SDRAM_BASE	0xfc000000	/* Localbus SDRAM */
#else
#define CONFIG_SYS_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
#endif
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 0MB	*/

#if defined(CONFIG_RAM_AS_FLASH)
#define CONFIG_SYS_FLASH_BASE          0xf8000000      /* start of FLASH  16M  */
#define CONFIG_SYS_BR0_PRELIM          0xf8001801      /* port size 32bit */
#else /* Boot from real Flash */
#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M    */
#define CONFIG_SYS_BR0_PRELIM		0xff801001	/* port size 16bit	*/
#endif

#define	CONFIG_SYS_OR0_PRELIM		0xff806f67	/* 8MB Flash		*/
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device   */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)*/
#define CONFIG_SYS_FLASH_CFI		1

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

/* DDR Setup */
#define CONFIG_FSL_DDR1
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_DDR_DLL                      /* possible DLL fix needed */

#undef  CONFIG_DDR_ECC			    /* only for ECC DDR module */
#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

#undef CONFIG_CLOCKS_IN_MHZ

/* local bus definitions */
#define CONFIG_SYS_BR2_PRELIM		0xf0001861	/* 64MB localbus SDRAM  */
#define CONFIG_SYS_OR2_PRELIM		0xfc006901
#define CONFIG_SYS_LBC_LCRR		0x00030004	/* local bus freq divider*/
#define CONFIG_SYS_LBC_LBCR		0x00000000
#define CONFIG_SYS_LBC_LSRT		0x20000000
#define CONFIG_SYS_LBC_MRTPR		0x20000000
#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723

#if defined(CONFIG_RAM_AS_FLASH)
#define CONFIG_SYS_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
#else
#define CONFIG_SYS_BR4_PRELIM          0xf8000801      /* 32KB, 8-bit wide for ADS config reg */
#endif
#define CONFIG_SYS_OR4_PRELIM          0xffffe1f1
#define CONFIG_SYS_BCSR                (CONFIG_SYS_BR4_PRELIM & 0xffff8000)

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000	/* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
#define CONFIG_BAUDRATE		115200

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef  CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET		0x3000

/* General PCI */
#define CONFIG_SYS_PCI_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI_MEM_SIZE	0x20000000
#define CONFIG_SYS_PCI_IO_BASE         0xe2000000

#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#undef CONFIG_EEPRO100
#define CONFIG_TULIP
#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR      0xe0000000
#define PCI_ENET0_MEMADDR     0xe0000000
#define PCI_IDSEL_NUMBER      0x0c	/*slot0->3(IDSEL)=12->15*/
#endif
#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0008
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1	/* MII PHY management	*/
#define CONFIG_TSEC1    1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME      "TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME      "TSEC1"
#define CONFIG_MPC85XX_FEC      1
#define CONFIG_HAS_ETH2
#define CONFIG_MPC85XX_FEC_NAME                "FEC"
#define TSEC1_PHY_ADDR          7
#define	TSEC2_PHY_ADDR		4
#define FEC_PHY_ADDR            2
#define TSEC1_PHYIDX            0
#define TSEC2_PHYIDX            0
#define FEC_PHYIDX              0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT
#define FEC_FLAGS		0

/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME                "TSEC0"

#define CONFIG_PHY_M88E1011     1       /* GigaBit Ether PHY    */
#define INTEL_LXT971_PHY	1
#endif

/* Environment */
#ifndef CONFIG_SYS_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x100000)
#define CONFIG_ENV_SIZE		0x2000
#else
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
#endif
#define CONFIG_ENV_SIZE		0x2000
#else
/* #define CONFIG_SYS_NO_FLASH		1 */	/* Flash is not usable now	*/
#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_BOOTARGS	"root=/dev/ram rw console=ttyS0,115200"
#define CONFIG_BOOTCOMMAND	"bootm 0xff800000 0xffa00000"
#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
    #undef CONFIG_CMD_SAVEENV
    #undef CONFIG_CMD_LOADS
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
#define CONFIG_SYS_PROMPT	"MPC8540EVAL=> "/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*****************************/
/* Environment Configuration */
/*****************************/
/* The mac addresses for all ethernet interface */
/* NOTE: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR  00:01:af:07:9b:8a
#define CONFIG_ETH1ADDR  00:01:af:07:9b:8b
#define CONFIG_ETH2ADDR  00:01:af:07:9b:8c
#endif

#define CONFIG_ROOTPATH  /nfsroot
#define CONFIG_BOOTFILE  your.uImage

#define CONFIG_SERVERIP         192.168.101.1
#define CONFIG_IPADDR           192.168.101.11
#define CONFIG_GATEWAYIP        192.168.101.0
#define CONFIG_NETMASK          255.255.255.0

#define CONFIG_LOADADDR  200000   /* default location for tftp and bootm */

#define CONFIG_HOSTNAME         MPC8540EVAL

#endif	/* __CONFIG_H */
Commit	Line	Data
b0e32949 LW	1	/*
	2	* (C) Copyright 2002,2003 Motorola,Inc.
	3	* Modified by Lunsheng Wang, lunsheng@sohu.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/* mpc8540eval board configuration file */
	25	/* please refer to doc/README.mpc85xxads for more info */
	26	/* make sure you change the MAC address and other network params first,
	27	* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32	/* High Level Configuration Options */
53677ef1	33	#define CONFIG_BOOKE 1 /* BOOKE */
b0e32949 LW	34	#define CONFIG_E500 1 /* BOOKE e500 family */
	35	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
	36	#define CONFIG_MPC8540 1 /* MPC8540 specific */
	37	#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */
	38
53677ef1 WD	39	#undef CONFIG_PCI /* pci ethernet support */
53677ef1 WD	40	#define CONFIG_TSEC_ENET /* tsec ethernet support */
b0e32949	41	#define CONFIG_ENV_OVERWRITE
b0e32949	42
4d3521cc KG	43	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
4d3521cc KG	44
b0e32949 LW	45	/* Using Localbus SDRAM to emulate flash before we can program the flash,
	46	* normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
	47	* Not availabe for EVAL board
	48	*/
	49	#undef CONFIG_RAM_AS_FLASH
	50
	51	/* sysclk for MPC8540EVAL */
	52	#if defined(CONFIG_SYSCLK_66M)
de1d0a69 JL	53	/*
	54	* the oscillator on board is 66Mhz
	55	* can also get 66M clock from external PCI
	56	*/
	57	#define CONFIG_SYS_CLK_FREQ 66000000
b0e32949	58	#else
de1d0a69	59	#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
b0e32949 LW	60	#endif
	61
	62	/* below can be toggled for performance analysis. otherwise use default */
53677ef1	63	#define CONFIG_L2_CACHE /* toggle L2 cache */
b0e32949	64	#undef CONFIG_BTB /* toggle branch predition */
b0e32949 LW	65
	66	#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
	67
6d0f6bcf JCPV	68	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	69	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
	70	#define CONFIG_SYS_MEMTEST_END 0x00400000
b0e32949 LW	71
	72	#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
	73	#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
	74	#endif
	75
	76	/*
	77	* Base addresses -- Note these are effective addresses where the
	78	* actual resources get mapped (not physical addresses)
	79	*/
6d0f6bcf JCPV	80	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
	81	#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
	82	#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
	83	#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
b0e32949	84
6d0f6bcf	85	#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is now 256MB */
b0e32949 LW	86
b0e32949 LW	87	#if defined(CONFIG_RAM_AS_FLASH)
6d0f6bcf	88	#define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
b0e32949	89	#else
6d0f6bcf	90	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
b0e32949	91	#endif
6d0f6bcf	92	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */
b0e32949 LW	93
b0e32949 LW	94	#if defined(CONFIG_RAM_AS_FLASH)
6d0f6bcf JCPV	95	#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
6d0f6bcf JCPV	96	#define CONFIG_SYS_BR0_PRELIM 0xf8001801 /* port size 32bit */
b0e32949	97	#else /* Boot from real Flash */
6d0f6bcf JCPV	98	#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
6d0f6bcf JCPV	99	#define CONFIG_SYS_BR0_PRELIM 0xff801001 /* port size 16bit */
b0e32949 LW	100	#endif
b0e32949 LW	101
6d0f6bcf JCPV	102	#define CONFIG_SYS_OR0_PRELIM 0xff806f67 /* 8MB Flash */
	103	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	104	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
	105	#undef CONFIG_SYS_FLASH_CHECKSUM
	106	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
	107	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
	108	#define CONFIG_SYS_FLASH_CFI 1
b0e32949	109
6d0f6bcf	110	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
b0e32949	111
6d0f6bcf JCPV	112	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	113	#define CONFIG_SYS_RAMBOOT
b0e32949	114	#else
6d0f6bcf	115	#undef CONFIG_SYS_RAMBOOT
b0e32949 LW	116	#endif
b0e32949 LW	117
9658bec2 KG	118	/* DDR Setup */
	119	#define CONFIG_FSL_DDR1
	120	#undef CONFIG_FSL_DDR_INTERACTIVE
	121	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	122	#define CONFIG_DDR_SPD
	123	#define CONFIG_DDR_DLL /* possible DLL fix needed */
	124
	125	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	126	#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
	127	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	128
6d0f6bcf JCPV	129	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	130	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
9658bec2	131	#define CONFIG_VERY_BIG_RAM
b0e32949	132
9658bec2 KG	133	#define CONFIG_NUM_DDR_CONTROLLERS 1
	134	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	135	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
b0e32949	136
9658bec2 KG	137	/* I2C addresses of SPD EEPROMs */
9658bec2 KG	138	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
b0e32949 LW	139
	140	#undef CONFIG_CLOCKS_IN_MHZ
	141
	142	/* local bus definitions */
6d0f6bcf JCPV	143	#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
	144	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
	145	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq divider*/
	146	#define CONFIG_SYS_LBC_LBCR 0x00000000
	147	#define CONFIG_SYS_LBC_LSRT 0x20000000
	148	#define CONFIG_SYS_LBC_MRTPR 0x20000000
	149	#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
	150	#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
	151	#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
	152	#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
	153	#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
b0e32949 LW	154
b0e32949 LW	155	#if defined(CONFIG_RAM_AS_FLASH)
6d0f6bcf	156	#define CONFIG_SYS_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
b0e32949	157	#else
6d0f6bcf	158	#define CONFIG_SYS_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
b0e32949	159	#endif
6d0f6bcf JCPV	160	#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
6d0f6bcf JCPV	161	#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
b0e32949	162
6d0f6bcf JCPV	163	#define CONFIG_SYS_INIT_RAM_LOCK 1
	164	#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
	165	#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
b0e32949	166
6d0f6bcf JCPV	167	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
	168	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	169	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
b0e32949	170
6d0f6bcf JCPV	171	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	172	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
b0e32949 LW	173
	174	/* Serial Port */
	175	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	176	#define CONFIG_SYS_NS16550
	177	#define CONFIG_SYS_NS16550_SERIAL
	178	#define CONFIG_SYS_NS16550_REG_SIZE 1
	179	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
53677ef1	180	#define CONFIG_BAUDRATE 115200
b0e32949	181
6d0f6bcf	182	#define CONFIG_SYS_BAUDRATE_TABLE \
b0e32949 LW	183	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
b0e32949 LW	184
6d0f6bcf JCPV	185	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	186	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
b0e32949 LW	187
b0e32949 LW	188	/* Use the HUSH parser */
6d0f6bcf JCPV	189	#define CONFIG_SYS_HUSH_PARSER
	190	#ifdef CONFIG_SYS_HUSH_PARSER
	191	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
b0e32949 LW	192	#endif
b0e32949 LW	193
20476726 JL	194	/*
	195	* I2C
	196	*/
	197	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	198	#define CONFIG_HARD_I2C /* I2C with hardware support*/
b0e32949	199	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	200	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	201	#define CONFIG_SYS_I2C_SLAVE 0x7F
	202	#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	203	#define CONFIG_SYS_I2C_OFFSET 0x3000
b0e32949 LW	204
b0e32949 LW	205	/* General PCI */
6d0f6bcf JCPV	206	#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
	207	#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
	208	#define CONFIG_SYS_PCI_MEM_SIZE 0x20000000
	209	#define CONFIG_SYS_PCI_IO_BASE 0xe2000000
b0e32949 LW	210
	211	#if defined(CONFIG_PCI)
	212	#define CONFIG_NET_MULTI
	213	#undef CONFIG_EEPRO100
	214	#define CONFIG_TULIP
53677ef1	215	#define CONFIG_PCI_PNP /* do pci plug-and-play */
de1d0a69 JL	216	#if !defined(CONFIG_PCI_PNP)
	217	#define PCI_ENET0_IOADDR 0xe0000000
	218	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	219	#define PCI_IDSEL_NUMBER 0x0c /slot0->3(IDSEL)=12->15/
de1d0a69	220	#endif
b0e32949	221	#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
6d0f6bcf JCPV	222	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
6d0f6bcf JCPV	223	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0008
b0e32949	224	#elif defined(CONFIG_TSEC_ENET)
53677ef1	225	#define CONFIG_NET_MULTI 1
b0e32949	226	#define CONFIG_MII 1 /* MII PHY management */
255a3577	227	#define CONFIG_TSEC1 1
10327dc5	228	#define CONFIG_HAS_ETH0
255a3577 KP	229	#define CONFIG_TSEC1_NAME "TSEC0"
255a3577 KP	230	#define CONFIG_TSEC2 1
10327dc5	231	#define CONFIG_HAS_ETH1
255a3577	232	#define CONFIG_TSEC2_NAME "TSEC1"
b0e32949	233	#define CONFIG_MPC85XX_FEC 1
10327dc5	234	#define CONFIG_HAS_ETH2
b0e32949 LW	235	#define CONFIG_MPC85XX_FEC_NAME "FEC"
	236	#define TSEC1_PHY_ADDR 7
	237	#define TSEC2_PHY_ADDR 4
	238	#define FEC_PHY_ADDR 2
	239	#define TSEC1_PHYIDX 0
	240	#define TSEC2_PHYIDX 0
	241	#define FEC_PHYIDX 0
3a79013e AF	242	#define TSEC1_FLAGS TSEC_GIGABIT
	243	#define TSEC2_FLAGS TSEC_GIGABIT
	244	#define FEC_FLAGS 0
	245
b0e32949 LW	246	/* Options are: TSEC[0-1], FEC */
	247	#define CONFIG_ETHPRIME "TSEC0"
	248
	249	#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
de1d0a69	250	#define INTEL_LXT971_PHY 1
b0e32949 LW	251	#endif
b0e32949 LW	252
b0e32949	253	/* Environment */
6d0f6bcf	254	#ifndef CONFIG_SYS_RAMBOOT
de1d0a69	255	#if defined(CONFIG_RAM_AS_FLASH)
93f6d725	256	#define CONFIG_ENV_IS_NOWHERE
6d0f6bcf	257	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
0e8d1586	258	#define CONFIG_ENV_SIZE 0x2000
de1d0a69	259	#else
5a1aceb0	260	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	261	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586	262	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
de1d0a69	263	#endif
0e8d1586	264	#define CONFIG_ENV_SIZE 0x2000
b0e32949	265	#else
6d0f6bcf	266	/* #define CONFIG_SYS_NO_FLASH 1 / / Flash is not usable now */
93f6d725	267	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf	268	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	269	#define CONFIG_ENV_SIZE 0x2000
b0e32949 LW	270	#endif
b0e32949 LW	271
b0e32949 LW	272	#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
b0e32949 LW	273	#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
53677ef1	274	#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
b0e32949 LW	275
b0e32949 LW	276	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	277	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
b0e32949	278
2835e518	279
659e2f67 JL	280	/*
	281	* BOOTP options
	282	*/
	283	#define CONFIG_BOOTP_BOOTFILESIZE
	284	#define CONFIG_BOOTP_BOOTPATH
	285	#define CONFIG_BOOTP_GATEWAY
	286	#define CONFIG_BOOTP_HOSTNAME
	287
	288
2835e518 JL	289	/*
	290	* Command line configuration.
	291	*/
	292	#include <config_cmd_default.h>
	293
	294	#define CONFIG_CMD_PING
	295	#define CONFIG_CMD_I2C
199e262e	296	#define CONFIG_CMD_REGINFO
2835e518	297
de1d0a69	298	#if defined(CONFIG_PCI)
2835e518	299	#define CONFIG_CMD_PCI
de1d0a69	300	#endif
2835e518	301
6d0f6bcf	302	#if defined(CONFIG_SYS_RAMBOOT) \|\| defined(CONFIG_RAM_AS_FLASH)
bdab39d3	303	#undef CONFIG_CMD_SAVEENV
2835e518	304	#undef CONFIG_CMD_LOADS
de1d0a69 JL	305	#endif
de1d0a69 JL	306
b0e32949 LW	307
	308	#undef CONFIG_WATCHDOG /* watchdog disabled */
	309
	310	/*
	311	* Miscellaneous configurable options
	312	*/
6d0f6bcf JCPV	313	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	314	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
	315	#define CONFIG_SYS_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */
2835e518	316	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	317	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
b0e32949	318	#else
6d0f6bcf	319	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b0e32949	320	#endif
6d0f6bcf JCPV	321	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	322	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	323	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	324	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
b0e32949 LW	325
	326	/*
	327	* For booting Linux, the board info and command line data
	328	* have to be in the first 8 MB of memory, since this is
	329	* the maximum mapped by the Linux kernel during initialization.
	330	*/
6d0f6bcf	331	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
b0e32949	332
b0e32949 LW	333	/*
	334	* Internal Definitions
	335	*
	336	* Boot Flags
	337	*/
	338	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	339	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	340
2835e518	341	#if defined(CONFIG_CMD_KGDB)
b0e32949 LW	342	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	343	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	344	#endif
	345
	346	/*****************************/
	347	/* Environment Configuration */
	348	/*****************************/
	349	/* The mac addresses for all ethernet interface */
	350	/* NOTE: change below for your network setting!!! */
	351	#if defined(CONFIG_TSEC_ENET)
	352	#define CONFIG_ETHADDR 00:01:af:07:9b:8a
	353	#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
	354	#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
	355	#endif
	356
	357	#define CONFIG_ROOTPATH /nfsroot
	358	#define CONFIG_BOOTFILE your.uImage
	359
	360	#define CONFIG_SERVERIP 192.168.101.1
	361	#define CONFIG_IPADDR 192.168.101.11
	362	#define CONFIG_GATEWAYIP 192.168.101.0
	363	#define CONFIG_NETMASK 255.255.255.0
	364
	365	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	366
	367	#define CONFIG_HOSTNAME MPC8540EVAL
	368
	369	#endif /* __CONFIG_H */