[people/ms/u-boot.git] / include / configs / MPC8544DS.h

/*
 * Copyright 2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8544ds board configuration file
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
#define CONFIG_MPC8544		1
#define CONFIG_MPC8544DS	1

#define CONFIG_PCI		1	/* Enable PCI/PCIE */
#define CONFIG_PCI1		1	/* PCI controller 1 */
#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */

#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_DLL
#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_DDR_ECC_CMD
#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */

/*
 * When initializing flash, if we cannot find the manufacturer ID,
 * assume this is the AMD flash associated with the CDS board.
 * This allows booting from a promjet.
 */
#define CONFIG_ASSUME_AMD_FLASH

#define MPC85xx_DDR_SDRAM_CLK_CNTL	/* 85xx has clock control reg */

#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
#define CONFIG_CLEAR_LAW0		/* Clear LAW0 in cpu_init_r */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#undef	CFG_DRAM_TEST			/* memory test, takes time */
#define CFG_MEMTEST_START	0x00200000	/* memtest works on */
#define CFG_MEMTEST_END		0x00400000
#define CFG_ALT_MEMTEST
#define CONFIG_PANIC_HANG	/* do not reset board on panic */

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */

#define CFG_PCI1_ADDR		(CFG_CCSRBAR+0x8000)
#define CFG_PCIE1_ADDR		(CFG_CCSRBAR+0xa000)
#define CFG_PCIE2_ADDR		(CFG_CCSRBAR+0x9000)
#define CFG_PCIE3_ADDR		(CFG_CCSRBAR+0xb000)

/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */

/*
 * Make sure required options are set
 */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required")
#endif

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Memory map
 *
 * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
 *
 * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
 *
 * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
 *
 * 0xe000_0000	0xe00f_ffff	CCSR			1M non-cacheable
 * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
 *
 * Localbus cacheable
 *
 * 0xf000_0000	0xf3ff_ffff	SDRAM			64M Cacheable
 * 0xf401_0000	0xf401_3fff	L1 for stack		4K Cacheable TLB0
 *
 * Localbus non-cacheable
 *
 * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS (*)	1M non-cacheable
 * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M non-cacheable
 * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M non-cacheable
 *
 */

/*
 * Local Bus Definitions
 */
#define CFG_BOOT_BLOCK		0xfc000000	/* boot TLB */

#define CFG_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable */

#define CFG_FLASH_BASE		0xff800000	/* start of FLASH 8M */

#define CFG_BR0_PRELIM		0xff801001
#define CFG_BR1_PRELIM		0xfe801001

#define CFG_OR0_PRELIM		0xff806e65
#define CFG_OR1_PRELIM		0xff806e65

#define CFG_FLASH_BANKS_LIST	{0xfe800000,CFG_FLASH_BASE}

#define CFG_MAX_FLASH_BANKS	2		/* number of banks */
#define CFG_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */

#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */

#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO

#define CFG_LBC_NONCACHE_BASE	0xf8000000

#define CFG_BR2_PRELIM		0xf8201001	/* port size 16bit */
#define CFG_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/

#define CFG_BR3_PRELIM		0xf8100801	/* port size 8bit */
#define CFG_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/

#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
#define PIXIS_ID		0x0	/* Board ID at offset 0 */
#define PIXIS_VER		0x1	/* Board version at offset 1 */
#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch
					 * register */
#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
#define PIXIS_VCTL		0x10	/* VELA Control Register */
#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
#define CFG_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/


/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM	1
#define CFG_INIT_L1_LOCK	1
#define CFG_INIT_L1_ADDR	0xf4010000	/* Initial L1 address */
#define CFG_INIT_L1_END		0x00004000	/* End of used area in RAM */

/* define to use L2SRAM as initial stack */
#undef CONFIG_L2_INIT_RAM
#define CFG_INIT_L2_ADDR	0xf8fc0000
#define CFG_INIT_L2_END		0x00040000	/* End of used area in RAM */

#ifdef CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_ADDR	CFG_INIT_L1_ADDR
#define CFG_INIT_RAM_END	CFG_INIT_L1_END
#else
#define CFG_INIT_RAM_ADDR	CFG_INIT_L2_ADDR
#define CFG_INIT_RAM_END	CFG_INIT_L2_END
#endif

#define CFG_GBL_DATA_SIZE	128	/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/* Serial Port - controlled on board with jumper J8
 * open - index 2
 * shorted - index 1
 */
#define CONFIG_CONS_INDEX	1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/* I2C */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR	0x57
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
#define CFG_I2C_OFFSET		0x3100

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CFG_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
#define CFG_PCI_PHYS		0xc0000000	/* 512M PCI TLB */

#define CFG_PCI1_MEM_BASE	0xc0000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI1_IO_BASE	0x00000000
#define CFG_PCI1_IO_PHYS	0xe1000000
#define CFG_PCI1_IO_SIZE	0x00010000	/* 64k */

/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS	0x00000000
#define CFG_PCI_MEMORY_PHYS	0x00000000
#define CFG_PCI_MEMORY_SIZE	0x80000000

/* controller 2, Slot 1, tgtid 1, Base address 9000 */
#define CFG_PCIE2_MEM_BASE	0x80000000
#define CFG_PCIE2_MEM_PHYS	CFG_PCIE2_MEM_BASE
#define CFG_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCIE2_IO_BASE	0x00000000
#define CFG_PCIE2_IO_PHYS	0xe1010000
#define CFG_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 1, Slot 2,tgtid 2, Base address a000 */
#define CFG_PCIE1_MEM_BASE	0xa0000000
#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
#define CFG_PCIE1_MEM_SIZE	0x10000000	/* 256M */
#define CFG_PCIE1_IO_BASE	0x00000000
#define CFG_PCIE1_IO_PHYS	0xe1020000
#define CFG_PCIE1_IO_SIZE	0x00010000	/* 64k */

/* controller 3, direct to uli, tgtid 3, Base address b000 */
#define CFG_PCIE3_MEM_BASE	0xb0000000
#define CFG_PCIE3_MEM_PHYS	CFG_PCIE3_MEM_BASE
#define CFG_PCIE3_MEM_SIZE	0x00100000	/* 1M */
#define CFG_PCIE3_IO_BASE	0x00000000
#define CFG_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
#define CFG_PCIE3_IO_SIZE	0x00100000	/* 1M */
#define CFG_PCIE3_MEM_BASE2	0xb0200000
#define CFG_PCIE3_MEM_PHYS2	CFG_PCIE3_MEM_BASE2
#define CFG_PCIE3_MEM_SIZE2	0x00200000	/* 1M */

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#define CONFIG_RTL8139

#ifdef CONFIG_RTL8139
/* This macro is used by RTL8139 but not defined in PPC architecture */
#define KSEG1ADDR(x)		(x)
#define _IO_BASE	0x00000000
#endif

#ifndef CONFIG_PCI_PNP
	#define PCI_ENET0_IOADDR	CFG_PCI1_IO_BASE
	#define PCI_ENET0_MEMADDR	CFG_PCI1_IO_BASE
	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
#endif

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_DOS_PARTITION
#define CONFIG_SCSI_AHCI

#ifdef CONFIG_SCSI_AHCI
#define CONFIG_SATA_ULI5288
#define CFG_SCSI_MAX_SCSI_ID	4
#define CFG_SCSI_MAX_LUN	1
#define CFG_SCSI_MAX_DEVICE	(CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
#define CFG_SCSI_MAXDEVICE	CFG_SCSI_MAX_DEVICE
#endif /* SCSCI */

#endif	/* CONFIG_PCI */


#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"eTSEC3"

#define TSEC1_PHY_ADDR		0
#define TSEC3_PHY_ADDR		1

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX		0
#define TSEC3_PHYIDX		0

#define CONFIG_ETHPRIME		"eTSEC1"

#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CFG_ENV_IS_IN_FLASH	1
#if CFG_MONITOR_BASE > 0xfff80000
#define CFG_ENV_ADDR		0xfff80000
#else
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
#endif
#define CFG_ENV_SIZE		0x2000
#define CFG_ENV_SECT_SIZE	0x10000 /* 64K (one sector) */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
    #define CONFIG_CMD_BEDBUG
    #define CONFIG_CMD_NET
    #define CONFIG_CMD_SCSI
    #define CONFIG_CMD_EXT2
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
#define CFG_LOAD_ADDR	0x2000000	/* default load address */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/* Cache Configuration */
#define CFG_DCACHE_SIZE		32768
#define CFG_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR	00:E0:0C:02:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
#endif

#define CONFIG_IPADDR	192.168.1.251

#define CONFIG_HOSTNAME	8544ds_unknown
#define CONFIG_ROOTPATH	/nfs/mpc85xx
#define CONFIG_BOOTFILE	8544ds/uImage.uboot
#define CONFIG_UBOOTPATH	8544ds/u-boot.bin	/* TFTP server */

#define CONFIG_SERVERIP	192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK	255.255.0.0

#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/

#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				\
 "netdev=eth0\0"						\
 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
 "tftpflash=tftpboot $loadaddr $uboot; "			\
	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
 "consoledev=ttyS0\0"				\
 "ramdiskaddr=2000000\0"			\
 "ramdiskfile=8544ds/ramdisk.uboot\0"		\
 "fdtaddr=c00000\0"				\
 "fdtfile=8544ds/mpc8544ds.dtb\0"		\
 "bdev=sda3\0"

#define CONFIG_NFSBOOTCOMMAND		\
 "setenv bootargs root=/dev/nfs rw "	\
 "nfsroot=$serverip:$rootpath "		\
 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $loadaddr $bootfile;"		\
 "tftp $fdtaddr $fdtfile;"		\
 "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND		\
 "setenv bootargs root=/dev/ram rw "	\
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $ramdiskaddr $ramdiskfile;"	\
 "tftp $loadaddr $bootfile;"		\
 "tftp $fdtaddr $fdtfile;"		\
 "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND		\
 "setenv bootargs root=/dev/$bdev rw "	\
 "console=$consoledev,$baudrate $othbootargs;"	\
 "tftp $loadaddr $bootfile;"		\
 "tftp $fdtaddr $fdtfile;"		\
 "bootm $loadaddr - $fdtaddr"

#endif	/* __CONFIG_H */
Commit	Line	Data
0cde4b00 JL	1	/*
	2	* Copyright 2007 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
	23	/*
	24	* mpc8544ds board configuration file
	25	*
	26	*/
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/* High Level Configuration Options */
	31	#define CONFIG_BOOKE 1 /* BOOKE */
	32	#define CONFIG_E500 1 /* BOOKE e500 family */
	33	#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
	34	#define CONFIG_MPC8544 1
	35	#define CONFIG_MPC8544DS 1
	36
837f1ba0 ES	37	#define CONFIG_PCI 1 /* Enable PCI/PCIE */
	38	#define CONFIG_PCI1 1 /* PCI controller 1 */
	39	#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
	40	#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
	41	#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
	42	#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
	43
	44	#define CONFIG_TSEC_ENET /* tsec ethernet support */
0cde4b00 JL	45	#define CONFIG_ENV_OVERWRITE
	46	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	47	#undef CONFIG_DDR_DLL
	48	#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
	49
	50	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	51	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
	52	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	53
	54	#define CONFIG_DDR_ECC_CMD
837f1ba0	55	#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
0cde4b00 JL	56
	57	/*
	58	* When initializing flash, if we cannot find the manufacturer ID,
	59	* assume this is the AMD flash associated with the CDS board.
	60	* This allows booting from a promjet.
	61	*/
	62	#define CONFIG_ASSUME_AMD_FLASH
	63
	64	#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
	65
	66	#ifndef __ASSEMBLY__
	67	extern unsigned long get_board_sys_clk(unsigned long dummy);
	68	#endif
	69	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
	70
	71	/*
	72	* These can be toggled for performance analysis, otherwise use default.
	73	*/
837f1ba0	74	#define CONFIG_L2_CACHE /* toggle L2 cache */
0cde4b00 JL	75	#define CONFIG_BTB /* toggle branch predition */
	76	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
	77	#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
	78
	79	/*
	80	* Only possible on E500 Version 2 or newer cores.
	81	*/
	82	#define CONFIG_ENABLE_36BIT_PHYS 1
	83
	84	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
	85
	86	#undef CFG_DRAM_TEST /* memory test, takes time */
	87	#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
	88	#define CFG_MEMTEST_END 0x00400000
	89	#define CFG_ALT_MEMTEST
837f1ba0	90	#define CONFIG_PANIC_HANG /* do not reset board on panic */
0cde4b00 JL	91
	92	/*
	93	* Base addresses -- Note these are effective addresses where the
	94	* actual resources get mapped (not physical addresses)
	95	*/
837f1ba0	96	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
0cde4b00 JL	97	#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
	98	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
	99
	100	#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
	101	#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
	102	#define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000)
	103	#define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000)
	104
	105	/*
	106	* DDR Setup
	107	*/
	108	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
	109	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
	110
	111	#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
	112
	113	/*
	114	* Make sure required options are set
	115	*/
	116	#ifndef CONFIG_SPD_EEPROM
	117	#error ("CONFIG_SPD_EEPROM is required")
	118	#endif
	119
	120	#undef CONFIG_CLOCKS_IN_MHZ
	121
	122	/*
	123	* Memory map
	124	*
	125	* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
	126	*
	127	* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
	128	*
	129	* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
	130	*
	131	* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
	132	* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
	133	*
	134	* Localbus cacheable
	135	*
	136	* 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
	137	* 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
	138	*
	139	* Localbus non-cacheable
	140	*
	141	* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
	142	* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
	143	* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
	144	*
	145	*/
	146
	147	/*
	148	* Local Bus Definitions
	149	*/
	150	#define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */
	151
	152	#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
	153
	154	#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
	155
	156	#define CFG_BR0_PRELIM 0xff801001
	157	#define CFG_BR1_PRELIM 0xfe801001
	158
	159	#define CFG_OR0_PRELIM 0xff806e65
	160	#define CFG_OR1_PRELIM 0xff806e65
161
162	#define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE}
163
164	#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
165	#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
166	#undef CFG_FLASH_CHECKSUM
167	#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
168	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
169
170	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
171
172	#define CFG_FLASH_CFI_DRIVER
173	#define CFG_FLASH_CFI
174	#define CFG_FLASH_EMPTY_INFO
175
176	#define CFG_LBC_NONCACHE_BASE 0xf8000000
177
178	#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */
179	#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
180
181	#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
182	#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
183
7608d75f	184	#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
0cde4b00 JL	185	#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
	186	#define PIXIS_ID 0x0 /* Board ID at offset 0 */
	187	#define PIXIS_VER 0x1 /* Board version at offset 1 */
	188	#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
	189	#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
	190	#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
	191	* register */
	192	#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
	193	#define PIXIS_VCTL 0x10 /* VELA Control Register */
	194	#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
	195	#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
	196	#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
	197	#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
	198	#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
	199	#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
	200	#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
db74b3c1	201	#define CFG_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
0cde4b00 JL	202
	203
	204	/* define to use L1 as initial stack */
	205	#define CONFIG_L1_INIT_RAM 1
	206	#define CFG_INIT_L1_LOCK 1
	207	#define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */
	208	#define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */
	209
	210	/* define to use L2SRAM as initial stack */
	211	#undef CONFIG_L2_INIT_RAM
	212	#define CFG_INIT_L2_ADDR 0xf8fc0000
	213	#define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */
	214
	215	#ifdef CONFIG_L1_INIT_RAM
	216	#define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR
	217	#define CFG_INIT_RAM_END CFG_INIT_L1_END
	218	#else
	219	#define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR
	220	#define CFG_INIT_RAM_END CFG_INIT_L2_END
	221	#endif
	222
	223	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
	224	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	225	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	226
	227	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
	228	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
	229
	230	/* Serial Port - controlled on board with jumper J8
	231	* open - index 2
	232	* shorted - index 1
	233	*/
	234	#define CONFIG_CONS_INDEX 1
	235	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	236	#define CFG_NS16550
	237	#define CFG_NS16550_SERIAL
	238	#define CFG_NS16550_REG_SIZE 1
	239	#define CFG_NS16550_CLK get_bus_freq(0)
	240
	241	#define CFG_BAUDRATE_TABLE \
	242	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	243
	244	#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
	245	#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
	246
	247	/* Use the HUSH parser */
	248	#define CFG_HUSH_PARSER
	249	#ifdef CFG_HUSH_PARSER
	250	#define CFG_PROMPT_HUSH_PS2 "> "
	251	#endif
	252
	253	/* pass open firmware flat tree */
addce57e KG	254	#define CONFIG_OF_LIBFDT 1
	255	#define CONFIG_OF_BOARD_SETUP 1
	256	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
0cde4b00 JL	257
	258	/* I2C */
	259	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	260	#define CONFIG_HARD_I2C /* I2C with hardware support */
	261	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	262	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	263	#define CFG_I2C_EEPROM_ADDR 0x57
	264	#define CFG_I2C_SLAVE 0x7F
	265	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	266	#define CFG_I2C_OFFSET 0x3100
	267
	268	/*
	269	* General PCI
	270	* Memory space is mapped 1-1, but I/O space must start from 0.
	271	*/
	272	#define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
	273	#define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
	274
	275	#define CFG_PCI1_MEM_BASE 0xc0000000
	276	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	277	#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
	278	#define CFG_PCI1_IO_BASE 0x00000000
	279	#define CFG_PCI1_IO_PHYS 0xe1000000
d64ee908	280	#define CFG_PCI1_IO_SIZE 0x00010000 /* 64k */
0cde4b00 JL	281
	282	/* PCI view of System Memory */
	283	#define CFG_PCI_MEMORY_BUS 0x00000000
	284	#define CFG_PCI_MEMORY_PHYS 0x00000000
	285	#define CFG_PCI_MEMORY_SIZE 0x80000000
	286
	287	/* controller 2, Slot 1, tgtid 1, Base address 9000 */
	288	#define CFG_PCIE2_MEM_BASE 0x80000000
	289	#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
	290	#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
	291	#define CFG_PCIE2_IO_BASE 0x00000000
d64ee908 KG	292	#define CFG_PCIE2_IO_PHYS 0xe1010000
d64ee908 KG	293	#define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */
0cde4b00 JL	294
	295	/* controller 1, Slot 2,tgtid 2, Base address a000 */
	296	#define CFG_PCIE1_MEM_BASE 0xa0000000
	297	#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
d64ee908 KG	298	#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 256M */
	299	#define CFG_PCIE1_IO_BASE 0x00000000
	300	#define CFG_PCIE1_IO_PHYS 0xe1020000
	301	#define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */
0cde4b00 JL	302
	303	/* controller 3, direct to uli, tgtid 3, Base address b000 */
	304	#define CFG_PCIE3_MEM_BASE 0xb0000000
	305	#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
d64ee908	306	#define CFG_PCIE3_MEM_SIZE 0x00100000 /* 1M */
0cde4b00	307	#define CFG_PCIE3_IO_BASE 0x00000000
d64ee908	308	#define CFG_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
0cde4b00	309	#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
56a92705 KG	310	#define CFG_PCIE3_MEM_BASE2 0xb0200000
	311	#define CFG_PCIE3_MEM_PHYS2 CFG_PCIE3_MEM_BASE2
	312	#define CFG_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
0cde4b00 JL	313
	314	#if defined(CONFIG_PCI)
	315
	316	#define CONFIG_NET_MULTI
	317	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	318
	319	#undef CONFIG_EEPRO100
	320	#undef CONFIG_TULIP
	321	#define CONFIG_RTL8139
	322
	323	#ifdef CONFIG_RTL8139
	324	/* This macro is used by RTL8139 but not defined in PPC architecture */
	325	#define KSEG1ADDR(x) (x)
	326	#define _IO_BASE 0x00000000
	327	#endif
	328
	329	#ifndef CONFIG_PCI_PNP
	330	#define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
	331	#define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE
	332	#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
	333	#endif
	334
	335	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	336	#define CONFIG_DOS_PARTITION
	337	#define CONFIG_SCSI_AHCI
	338
	339	#ifdef CONFIG_SCSI_AHCI
	340	#define CONFIG_SATA_ULI5288
	341	#define CFG_SCSI_MAX_SCSI_ID 4
	342	#define CFG_SCSI_MAX_LUN 1
837f1ba0	343	#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
0cde4b00 JL	344	#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
	345	#endif /* SCSCI */
	346
	347	#endif /* CONFIG_PCI */
	348
	349
	350	#if defined(CONFIG_TSEC_ENET)
	351
	352	#ifndef CONFIG_NET_MULTI
837f1ba0	353	#define CONFIG_NET_MULTI 1
0cde4b00 JL	354	#endif
	355
	356	#define CONFIG_MII 1 /* MII PHY management */
	357	#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
255a3577 KP	358	#define CONFIG_TSEC1 1
	359	#define CONFIG_TSEC1_NAME "eTSEC1"
	360	#define CONFIG_TSEC3 1
	361	#define CONFIG_TSEC3_NAME "eTSEC3"
837f1ba0	362
0cde4b00 JL	363	#define TSEC1_PHY_ADDR 0
	364	#define TSEC3_PHY_ADDR 1
	365
3a79013e AF	366	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	367	#define TSEC3_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	368
0cde4b00 JL	369	#define TSEC1_PHYIDX 0
	370	#define TSEC3_PHYIDX 0
	371
	372	#define CONFIG_ETHPRIME "eTSEC1"
	373
	374	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
0cde4b00 JL	375	#endif /* CONFIG_TSEC_ENET */
	376
	377	/*
	378	* Environment
	379	*/
	380	#define CFG_ENV_IS_IN_FLASH 1
	381	#if CFG_MONITOR_BASE > 0xfff80000
	382	#define CFG_ENV_ADDR 0xfff80000
	383	#else
	384	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
	385	#endif
	386	#define CFG_ENV_SIZE 0x2000
	387	#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
	388
	389	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	390	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	391
659e2f67 JL	392	/*
	393	* BOOTP options
	394	*/
	395	#define CONFIG_BOOTP_BOOTFILESIZE
	396	#define CONFIG_BOOTP_BOOTPATH
	397	#define CONFIG_BOOTP_GATEWAY
	398	#define CONFIG_BOOTP_HOSTNAME
	399
	400
2835e518 JL	401	/*
	402	* Command line configuration.
	403	*/
	404	#include <config_cmd_default.h>
	405
	406	#define CONFIG_CMD_PING
	407	#define CONFIG_CMD_I2C
	408	#define CONFIG_CMD_MII
82ac8c97	409	#define CONFIG_CMD_ELF
2835e518	410
0cde4b00	411	#if defined(CONFIG_PCI)
2835e518 JL	412	#define CONFIG_CMD_PCI
	413	#define CONFIG_CMD_BEDBUG
	414	#define CONFIG_CMD_NET
837f1ba0 ES	415	#define CONFIG_CMD_SCSI
837f1ba0 ES	416	#define CONFIG_CMD_EXT2
0cde4b00	417	#endif
2835e518	418
0cde4b00 JL	419
	420	#undef CONFIG_WATCHDOG /* watchdog disabled */
	421
	422	/*
	423	* Miscellaneous configurable options
	424	*/
	425	#define CFG_LONGHELP /* undef to save memory */
50c03c8c	426	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
0cde4b00 JL	427	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
0cde4b00 JL	428	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
2835e518	429	#if defined(CONFIG_CMD_KGDB)
0cde4b00 JL	430	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	431	#else
	432	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	433	#endif
	434	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	435	#define CFG_MAXARGS 16 /* max number of command args */
	436	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	437	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	438
	439	/*
	440	* For booting Linux, the board info and command line data
	441	* have to be in the first 8 MB of memory, since this is
	442	* the maximum mapped by the Linux kernel during initialization.
	443	*/
837f1ba0	444	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
0cde4b00 JL	445
0cde4b00 JL	446	/* Cache Configuration */
837f1ba0	447	#define CFG_DCACHE_SIZE 32768
0cde4b00	448	#define CFG_CACHELINE_SIZE 32
2835e518	449	#if defined(CONFIG_CMD_KGDB)
0cde4b00 JL	450	#define CFG_CACHELINE_SHIFT 5 /log base 2 of the above value/
	451	#endif
	452
	453	/*
	454	* Internal Definitions
	455	*
	456	* Boot Flags
	457	*/
	458	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	459	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	460
2835e518	461	#if defined(CONFIG_CMD_KGDB)
0cde4b00 JL	462	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	463	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	464	#endif
	465
	466	/*
	467	* Environment Configuration
	468	*/
	469
	470	/* The mac addresses for all ethernet interface */
	471	#if defined(CONFIG_TSEC_ENET)
ea5877e3	472	#define CONFIG_HAS_ETH0
0cde4b00 JL	473	#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
	474	#define CONFIG_HAS_ETH1
	475	#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
0cde4b00 JL	476	#endif
	477
	478	#define CONFIG_IPADDR 192.168.1.251
	479
	480	#define CONFIG_HOSTNAME 8544ds_unknown
	481	#define CONFIG_ROOTPATH /nfs/mpc85xx
837f1ba0 ES	482	#define CONFIG_BOOTFILE 8544ds/uImage.uboot
837f1ba0 ES	483	#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
0cde4b00	484
50c03c8c KG	485	#define CONFIG_SERVERIP 192.168.1.1
50c03c8c KG	486	#define CONFIG_GATEWAYIP 192.168.1.1
0cde4b00 JL	487	#define CONFIG_NETMASK 255.255.0.0
	488
	489	#define CONFIG_LOADADDR 1000000 /default location for tftp and bootm/
	490
	491	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
837f1ba0	492	#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
0cde4b00 JL	493
	494	#define CONFIG_BAUDRATE 115200
	495
837f1ba0 ES	496	#define CONFIG_EXTRA_ENV_SETTINGS \
	497	"netdev=eth0\0" \
	498	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
	499	"tftpflash=tftpboot $loadaddr $uboot; " \
	500	"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
	501	"erase " MK_STR(TEXT_BASE) " +$filesize; " \
	502	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
	503	"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
	504	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
0cde4b00 JL	505	"consoledev=ttyS0\0" \
0cde4b00 JL	506	"ramdiskaddr=2000000\0" \
837f1ba0	507	"ramdiskfile=8544ds/ramdisk.uboot\0" \
50c03c8c KG	508	"fdtaddr=c00000\0" \
	509	"fdtfile=8544ds/mpc8544ds.dtb\0" \
	510	"bdev=sda3\0"
0cde4b00 JL	511
	512	#define CONFIG_NFSBOOTCOMMAND \
	513	"setenv bootargs root=/dev/nfs rw " \
	514	"nfsroot=$serverip:$rootpath " \
	515	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	516	"console=$consoledev,$baudrate $othbootargs;" \
	517	"tftp $loadaddr $bootfile;" \
50c03c8c KG	518	"tftp $fdtaddr $fdtfile;" \
50c03c8c KG	519	"bootm $loadaddr - $fdtaddr"
0cde4b00	520
837f1ba0	521	#define CONFIG_RAMBOOTCOMMAND \
0cde4b00 JL	522	"setenv bootargs root=/dev/ram rw " \
	523	"console=$consoledev,$baudrate $othbootargs;" \
	524	"tftp $ramdiskaddr $ramdiskfile;" \
	525	"tftp $loadaddr $bootfile;" \
50c03c8c KG	526	"tftp $fdtaddr $fdtfile;" \
50c03c8c KG	527	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0cde4b00	528
837f1ba0 ES	529	#define CONFIG_BOOTCOMMAND \
837f1ba0 ES	530	"setenv bootargs root=/dev/$bdev rw " \
0cde4b00 JL	531	"console=$consoledev,$baudrate $othbootargs;" \
0cde4b00 JL	532	"tftp $loadaddr $bootfile;" \
50c03c8c KG	533	"tftp $fdtaddr $fdtfile;" \
50c03c8c KG	534	"bootm $loadaddr - $fdtaddr"
0cde4b00 JL	535
0cde4b00 JL	536	#endif /* __CONFIG_H */