]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/MPC8548CDS.h
rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / include / configs / MPC8548CDS.h
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d9b94f28 1/*
f2cff6b1 2 * Copyright 2004, 2007 Freescale Semiconductor.
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3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
f2cff6b1 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8548cds board configuration file
25 *
26 * Please refer to doc/README.mpc85xxcds for more info.
27 *
28 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* High Level Configuration Options */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36#define CONFIG_MPC8548 1 /* MPC8548 specific */
37#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
38
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39#define CONFIG_PCI /* enable any pci type devices */
40#define CONFIG_PCI1 /* PCI controller 1 */
41#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
42#undef CONFIG_RIO
43#undef CONFIG_PCI2
44#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
8ff3de61 45#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
f2cff6b1
ES
46
47#define CONFIG_TSEC_ENET /* tsec ethernet support */
d9b94f28 48#define CONFIG_ENV_OVERWRITE
f2cff6b1 49#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
2cfaa1aa 50#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
d9b94f28 51
25eedb2c 52#define CONFIG_FSL_VIA
25eedb2c 53
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54/*
55 * When initializing flash, if we cannot find the manufacturer ID,
56 * assume this is the AMD flash associated with the CDS board.
57 * This allows booting from a promjet.
58 */
59#define CONFIG_ASSUME_AMD_FLASH
60
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61#ifndef __ASSEMBLY__
62extern unsigned long get_clock_freq(void);
63#endif
64#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
65
66/*
67 * These can be toggled for performance analysis, otherwise use default.
68 */
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ES
69#define CONFIG_L2_CACHE /* toggle L2 cache */
70#define CONFIG_BTB /* toggle branch predition */
71#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
72#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
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73
74/*
75 * Only possible on E500 Version 2 or newer cores.
76 */
77#define CONFIG_ENABLE_36BIT_PHYS 1
78
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79#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
80#define CONFIG_SYS_MEMTEST_END 0x00400000
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81
82/*
83 * Base addresses -- Note these are effective addresses where the
84 * actual resources get mapped (not physical addresses)
85 */
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86#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
87#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
88#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
89#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
d9b94f28 90
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91#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
92#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
93#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
f2cff6b1 94
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95/* DDR Setup */
96#define CONFIG_FSL_DDR2
97#undef CONFIG_FSL_DDR_INTERACTIVE
98#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
99#define CONFIG_DDR_SPD
100#define CONFIG_DDR_DLL /* possible DLL fix needed */
101
102#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
103#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
104
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105#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
106#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
d9b94f28 107
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108#define CONFIG_NUM_DDR_CONTROLLERS 1
109#define CONFIG_DIMM_SLOTS_PER_CTLR 1
110#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
d9b94f28 111
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112/* I2C addresses of SPD EEPROMs */
113#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
114
115/* Make sure required options are set */
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116#ifndef CONFIG_SPD_EEPROM
117#error ("CONFIG_SPD_EEPROM is required")
118#endif
119
120#undef CONFIG_CLOCKS_IN_MHZ
121
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122/*
123 * Local Bus Definitions
124 */
125
126/*
127 * FLASH on the Local Bus
128 * Two banks, 8M each, using the CFI driver.
129 * Boot from BR0/OR0 bank at 0xff00_0000
130 * Alternate BR1/OR1 bank at 0xff80_0000
131 *
132 * BR0, BR1:
133 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
134 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
135 * Port Size = 16 bits = BRx[19:20] = 10
136 * Use GPCM = BRx[24:26] = 000
137 * Valid = BRx[31] = 1
138 *
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139 * 0 4 8 12 16 20 24 28
140 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
141 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
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142 *
143 * OR0, OR1:
144 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
145 * Reserved ORx[17:18] = 11, confusion here?
146 * CSNT = ORx[20] = 1
147 * ACS = half cycle delay = ORx[21:22] = 11
148 * SCY = 6 = ORx[24:27] = 0110
149 * TRLX = use relaxed timing = ORx[29] = 1
150 * EAD = use external address latch delay = OR[31] = 1
151 *
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152 * 0 4 8 12 16 20 24 28
153 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
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154 */
155
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156#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */
157#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
d9b94f28 158
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159#define CONFIG_SYS_BR0_PRELIM 0xff801001
160#define CONFIG_SYS_BR1_PRELIM 0xff001001
d9b94f28 161
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162#define CONFIG_SYS_OR0_PRELIM 0xff806e65
163#define CONFIG_SYS_OR1_PRELIM 0xff806e65
d9b94f28 164
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165#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
166#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
167#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
168#undef CONFIG_SYS_FLASH_CHECKSUM
169#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
170#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
d9b94f28 171
6d0f6bcf 172#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
d9b94f28 173
00b1883a 174#define CONFIG_FLASH_CFI_DRIVER
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175#define CONFIG_SYS_FLASH_CFI
176#define CONFIG_SYS_FLASH_EMPTY_INFO
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177
178
179/*
180 * SDRAM on the Local Bus
181 */
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182#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
183#define CONFIG_SYS_LBC_CACHE_SIZE 64
184#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
185#define CONFIG_SYS_LBC_NONCACHE_SIZE 64
f2cff6b1 186
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187#define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */
188#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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189
190/*
191 * Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf 192 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
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193 *
194 * For BR2, need:
195 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
196 * port-size = 32-bits = BR2[19:20] = 11
197 * no parity checking = BR2[21:22] = 00
198 * SDRAM for MSEL = BR2[24:26] = 011
199 * Valid = BR[31] = 1
200 *
f2cff6b1 201 * 0 4 8 12 16 20 24 28
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202 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
203 *
6d0f6bcf 204 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
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205 * FIXME: the top 17 bits of BR2.
206 */
207
6d0f6bcf 208#define CONFIG_SYS_BR2_PRELIM 0xf0001861
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209
210/*
6d0f6bcf 211 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
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212 *
213 * For OR2, need:
214 * 64MB mask for AM, OR2[0:7] = 1111 1100
215 * XAM, OR2[17:18] = 11
216 * 9 columns OR2[19-21] = 010
f2cff6b1 217 * 13 rows OR2[23-25] = 100
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218 * EAD set for extra time OR[31] = 1
219 *
f2cff6b1 220 * 0 4 8 12 16 20 24 28
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221 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
222 */
223
6d0f6bcf 224#define CONFIG_SYS_OR2_PRELIM 0xfc006901
d9b94f28 225
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226#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
227#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
228#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
229#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
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230
231/*
232 * LSDMR masks
233 */
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234#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
235#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
236#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
237#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
238#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
239#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
240#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
241#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
242#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
243#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
244
245#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
246#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
247#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
248#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
249#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
250#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
251#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
252#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
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253
254/*
255 * Common settings for all Local Bus SDRAM commands.
256 * At run time, either BSMA1516 (for CPU 1.1)
f2cff6b1 257 * or BSMA1617 (for CPU 1.0) (old)
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258 * is OR'ed in too.
259 */
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260#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \
261 | CONFIG_SYS_LBC_LSDMR_PRETOACT7 \
262 | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \
263 | CONFIG_SYS_LBC_LSDMR_BL8 \
264 | CONFIG_SYS_LBC_LSDMR_WRC4 \
265 | CONFIG_SYS_LBC_LSDMR_CL3 \
266 | CONFIG_SYS_LBC_LSDMR_RFEN \
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267 )
268
269/*
270 * The CADMUS registers are connected to CS3 on CDS.
271 * The new memory map places CADMUS at 0xf8000000.
272 *
273 * For BR3, need:
274 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
275 * port-size = 8-bits = BR[19:20] = 01
276 * no parity checking = BR[21:22] = 00
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277 * GPMC for MSEL = BR[24:26] = 000
278 * Valid = BR[31] = 1
d9b94f28 279 *
f2cff6b1 280 * 0 4 8 12 16 20 24 28
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281 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
282 *
283 * For OR3, need:
f2cff6b1 284 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
d9b94f28 285 * disable buffer ctrl OR[19] = 0
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286 * CSNT OR[20] = 1
287 * ACS OR[21:22] = 11
288 * XACS OR[23] = 1
d9b94f28 289 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
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290 * SETA OR[28] = 0
291 * TRLX OR[29] = 1
292 * EHTR OR[30] = 1
293 * EAD extra time OR[31] = 1
d9b94f28 294 *
f2cff6b1 295 * 0 4 8 12 16 20 24 28
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296 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
297 */
298
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299#define CONFIG_FSL_CADMUS
300
d9b94f28 301#define CADMUS_BASE_ADDR 0xf8000000
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302#define CONFIG_SYS_BR3_PRELIM 0xf8000801
303#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
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304
305#define CONFIG_L1_INIT_RAM
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306#define CONFIG_SYS_INIT_RAM_LOCK 1
307#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
308#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
f2cff6b1 309
6d0f6bcf 310#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
d9b94f28 311
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312#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
313#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
314#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
d9b94f28 315
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316#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
317#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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318
319/* Serial Port */
f2cff6b1 320#define CONFIG_CONS_INDEX 2
d9b94f28 321#undef CONFIG_SERIAL_SOFTWARE_FIFO
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322#define CONFIG_SYS_NS16550
323#define CONFIG_SYS_NS16550_SERIAL
324#define CONFIG_SYS_NS16550_REG_SIZE 1
325#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
d9b94f28 326
6d0f6bcf 327#define CONFIG_SYS_BAUDRATE_TABLE \
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328 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
329
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330#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
331#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
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332
333/* Use the HUSH parser */
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334#define CONFIG_SYS_HUSH_PARSER
335#ifdef CONFIG_SYS_HUSH_PARSER
336#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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337#endif
338
40d5fa35 339/* pass open firmware flat tree */
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340#define CONFIG_OF_LIBFDT 1
341#define CONFIG_OF_BOARD_SETUP 1
342#define CONFIG_OF_STDOUT_VIA_ALIAS 1
40d5fa35 343
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344#define CONFIG_SYS_64BIT_VSPRINTF 1
345#define CONFIG_SYS_64BIT_STRTOUL 1
e31d2c1e 346
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347/*
348 * I2C
349 */
350#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
351#define CONFIG_HARD_I2C /* I2C with hardware support*/
f2cff6b1 352#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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353#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
354#define CONFIG_SYS_I2C_SLAVE 0x7F
355#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
356#define CONFIG_SYS_I2C_OFFSET 0x3000
d9b94f28 357
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358/* EEPROM */
359#define CONFIG_ID_EEPROM
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360#define CONFIG_SYS_I2C_EEPROM_CCID
361#define CONFIG_SYS_ID_EEPROM
362#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
363#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
e8d18541 364
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365/*
366 * General PCI
362dd830 367 * Memory space is mapped 1-1, but I/O space must start from 0.
d9b94f28 368 */
6d0f6bcf 369#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
f2cff6b1 370
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371#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
372#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
373#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
374#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
375#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
376#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
d9b94f28 377
f2cff6b1 378#ifdef CONFIG_PCI2
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379#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
380#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
381#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
382#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
383#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
384#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
f2cff6b1 385#endif
41fb7e0f 386
f2cff6b1 387#ifdef CONFIG_PCIE1
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388#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
389#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
390#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
391#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
392#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
393#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
f2cff6b1 394#endif
d9b94f28 395
f2cff6b1 396#ifdef CONFIG_RIO
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397/*
398 * RapidIO MMU
399 */
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400#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
401#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
f2cff6b1 402#endif
d9b94f28 403
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404#ifdef CONFIG_LEGACY
405#define BRIDGE_ID 17
406#define VIA_ID 2
407#else
408#define BRIDGE_ID 28
409#define VIA_ID 4
410#endif
411
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412#if defined(CONFIG_PCI)
413
414#define CONFIG_NET_MULTI
f2cff6b1 415#define CONFIG_PCI_PNP /* do pci plug-and-play */
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416
417#undef CONFIG_EEPRO100
418#undef CONFIG_TULIP
419
d9b94f28 420#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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421
422/* PCI view of System Memory */
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423#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
424#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
425#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
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426
427#endif /* CONFIG_PCI */
428
429
430#if defined(CONFIG_TSEC_ENET)
431
432#ifndef CONFIG_NET_MULTI
f2cff6b1 433#define CONFIG_NET_MULTI 1
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434#endif
435
436#define CONFIG_MII 1 /* MII PHY management */
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437#define CONFIG_TSEC1 1
438#define CONFIG_TSEC1_NAME "eTSEC0"
439#define CONFIG_TSEC2 1
440#define CONFIG_TSEC2_NAME "eTSEC1"
441#define CONFIG_TSEC3 1
442#define CONFIG_TSEC3_NAME "eTSEC2"
f2cff6b1 443#define CONFIG_TSEC4
255a3577 444#define CONFIG_TSEC4_NAME "eTSEC3"
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445#undef CONFIG_MPC85XX_FEC
446
447#define TSEC1_PHY_ADDR 0
448#define TSEC2_PHY_ADDR 1
449#define TSEC3_PHY_ADDR 2
450#define TSEC4_PHY_ADDR 3
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451
452#define TSEC1_PHYIDX 0
453#define TSEC2_PHYIDX 0
454#define TSEC3_PHYIDX 0
455#define TSEC4_PHYIDX 0
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456#define TSEC1_FLAGS TSEC_GIGABIT
457#define TSEC2_FLAGS TSEC_GIGABIT
458#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
459#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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460
461/* Options are: eTSEC[0-3] */
462#define CONFIG_ETHPRIME "eTSEC0"
f2cff6b1 463#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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464#endif /* CONFIG_TSEC_ENET */
465
466/*
467 * Environment
468 */
5a1aceb0 469#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf 470#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
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471#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
472#define CONFIG_ENV_SIZE 0x2000
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473
474#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 475#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
d9b94f28 476
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477/*
478 * BOOTP options
479 */
480#define CONFIG_BOOTP_BOOTFILESIZE
481#define CONFIG_BOOTP_BOOTPATH
482#define CONFIG_BOOTP_GATEWAY
483#define CONFIG_BOOTP_HOSTNAME
484
485
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486/*
487 * Command line configuration.
488 */
489#include <config_cmd_default.h>
490
491#define CONFIG_CMD_PING
492#define CONFIG_CMD_I2C
493#define CONFIG_CMD_MII
82ac8c97 494#define CONFIG_CMD_ELF
2835e518 495
d9b94f28 496#if defined(CONFIG_PCI)
2835e518 497 #define CONFIG_CMD_PCI
d9b94f28 498#endif
2835e518 499
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500
501#undef CONFIG_WATCHDOG /* watchdog disabled */
502
503/*
504 * Miscellaneous configurable options
505 */
6d0f6bcf 506#define CONFIG_SYS_LONGHELP /* undef to save memory */
22abb2d2 507#define CONFIG_CMDLINE_EDITING /* Command-line editing */
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508#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
509#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
2835e518 510#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 511#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
d9b94f28 512#else
6d0f6bcf 513#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
d9b94f28 514#endif
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515#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
516#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
517#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
518#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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519
520/*
521 * For booting Linux, the board info and command line data
522 * have to be in the first 8 MB of memory, since this is
523 * the maximum mapped by the Linux kernel during initialization.
524 */
6d0f6bcf 525#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
d9b94f28 526
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527/*
528 * Internal Definitions
529 *
530 * Boot Flags
531 */
532#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
533#define BOOTFLAG_WARM 0x02 /* Software reboot */
534
2835e518 535#if defined(CONFIG_CMD_KGDB)
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536#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
537#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
538#endif
539
540/*
541 * Environment Configuration
542 */
543
544/* The mac addresses for all ethernet interface */
545#if defined(CONFIG_TSEC_ENET)
10327dc5 546#define CONFIG_HAS_ETH0
f2cff6b1 547#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
d9b94f28 548#define CONFIG_HAS_ETH1
f2cff6b1 549#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
d9b94f28 550#define CONFIG_HAS_ETH2
f2cff6b1 551#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
09f3e09e 552#define CONFIG_HAS_ETH3
f2cff6b1 553#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
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554#endif
555
f2cff6b1 556#define CONFIG_IPADDR 192.168.1.253
d9b94f28 557
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558#define CONFIG_HOSTNAME unknown
559#define CONFIG_ROOTPATH /nfsroot
560#define CONFIG_BOOTFILE 8548cds/uImage.uboot
561#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
d9b94f28 562
f2cff6b1 563#define CONFIG_SERVERIP 192.168.1.1
d9b94f28 564#define CONFIG_GATEWAYIP 192.168.1.1
f2cff6b1 565#define CONFIG_NETMASK 255.255.255.0
d9b94f28 566
f2cff6b1 567#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
d9b94f28 568
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569#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
570#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
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571
572#define CONFIG_BAUDRATE 115200
573
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574#define CONFIG_EXTRA_ENV_SETTINGS \
575 "netdev=eth0\0" \
576 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
577 "tftpflash=tftpboot $loadaddr $uboot; " \
578 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
579 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
580 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
581 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
582 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
583 "consoledev=ttyS1\0" \
584 "ramdiskaddr=2000000\0" \
6c543597 585 "ramdiskfile=ramdisk.uboot\0" \
4bf4abb8 586 "fdtaddr=c00000\0" \
22abb2d2 587 "fdtfile=mpc8548cds.dtb\0"
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588
589#define CONFIG_NFSBOOTCOMMAND \
590 "setenv bootargs root=/dev/nfs rw " \
591 "nfsroot=$serverip:$rootpath " \
d9b94f28 592 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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593 "console=$consoledev,$baudrate $othbootargs;" \
594 "tftp $loadaddr $bootfile;" \
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595 "tftp $fdtaddr $fdtfile;" \
596 "bootm $loadaddr - $fdtaddr"
8272dc2f 597
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598
599#define CONFIG_RAMBOOTCOMMAND \
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600 "setenv bootargs root=/dev/ram rw " \
601 "console=$consoledev,$baudrate $othbootargs;" \
602 "tftp $ramdiskaddr $ramdiskfile;" \
603 "tftp $loadaddr $bootfile;" \
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604 "tftp $fdtaddr $fdtfile;" \
605 "bootm $loadaddr $ramdiskaddr $fdtaddr"
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606
607#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
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608
609#endif /* __CONFIG_H */